Commit | Line | Data |
---|---|---|
9274f4a9 BS |
1 | #ifndef __NOUVEAU_CLASS_H__ |
2 | #define __NOUVEAU_CLASS_H__ | |
3 | ||
9456f7d1 BS |
4 | /* Device class |
5 | * | |
6 | * 0080: NV_DEVICE | |
9274f4a9 | 7 | */ |
9456f7d1 | 8 | #define NV_DEVICE_CLASS 0x00000080 |
9274f4a9 BS |
9 | |
10 | #define NV_DEVICE_DISABLE_IDENTIFY 0x0000000000000001ULL | |
11 | #define NV_DEVICE_DISABLE_MMIO 0x0000000000000002ULL | |
12 | #define NV_DEVICE_DISABLE_VBIOS 0x0000000000000004ULL | |
13 | #define NV_DEVICE_DISABLE_CORE 0x0000000000000008ULL | |
14 | #define NV_DEVICE_DISABLE_DISP 0x0000000000010000ULL | |
15 | #define NV_DEVICE_DISABLE_FIFO 0x0000000000020000ULL | |
16 | #define NV_DEVICE_DISABLE_GRAPH 0x0000000100000000ULL | |
17 | #define NV_DEVICE_DISABLE_MPEG 0x0000000200000000ULL | |
18 | #define NV_DEVICE_DISABLE_ME 0x0000000400000000ULL | |
19 | #define NV_DEVICE_DISABLE_VP 0x0000000800000000ULL | |
20 | #define NV_DEVICE_DISABLE_CRYPT 0x0000001000000000ULL | |
21 | #define NV_DEVICE_DISABLE_BSP 0x0000002000000000ULL | |
22 | #define NV_DEVICE_DISABLE_PPP 0x0000004000000000ULL | |
23 | #define NV_DEVICE_DISABLE_COPY0 0x0000008000000000ULL | |
24 | #define NV_DEVICE_DISABLE_COPY1 0x0000010000000000ULL | |
25 | #define NV_DEVICE_DISABLE_UNK1C1 0x0000020000000000ULL | |
206c38a9 | 26 | #define NV_DEVICE_DISABLE_VENC 0x0000040000000000ULL |
9274f4a9 BS |
27 | |
28 | struct nv_device_class { | |
29 | u64 device; /* device identifier, ~0 for client default */ | |
30 | u64 disable; /* disable particular subsystems */ | |
31 | u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */ | |
32 | }; | |
33 | ||
9456f7d1 BS |
34 | /* DMA object classes |
35 | * | |
36 | * 0002: NV_DMA_FROM_MEMORY | |
9274f4a9 BS |
37 | * 0003: NV_DMA_TO_MEMORY |
38 | * 003d: NV_DMA_IN_MEMORY | |
39 | */ | |
9456f7d1 BS |
40 | #define NV_DMA_FROM_MEMORY_CLASS 0x00000002 |
41 | #define NV_DMA_TO_MEMORY_CLASS 0x00000003 | |
42 | #define NV_DMA_IN_MEMORY_CLASS 0x0000003d | |
9274f4a9 BS |
43 | |
44 | #define NV_DMA_TARGET_MASK 0x000000ff | |
45 | #define NV_DMA_TARGET_VM 0x00000000 | |
46 | #define NV_DMA_TARGET_VRAM 0x00000001 | |
47 | #define NV_DMA_TARGET_PCI 0x00000002 | |
48 | #define NV_DMA_TARGET_PCI_US 0x00000003 | |
49 | #define NV_DMA_TARGET_AGP 0x00000004 | |
50 | #define NV_DMA_ACCESS_MASK 0x00000f00 | |
51 | #define NV_DMA_ACCESS_VM 0x00000000 | |
52 | #define NV_DMA_ACCESS_RD 0x00000100 | |
53 | #define NV_DMA_ACCESS_WR 0x00000200 | |
54 | #define NV_DMA_ACCESS_RDWR 0x00000300 | |
55 | ||
f756944a BS |
56 | /* NV50:NVC0 */ |
57 | #define NV50_DMA_CONF0_ENABLE 0x80000000 | |
58 | #define NV50_DMA_CONF0_PRIV 0x00300000 | |
59 | #define NV50_DMA_CONF0_PRIV_VM 0x00000000 | |
60 | #define NV50_DMA_CONF0_PRIV_US 0x00100000 | |
61 | #define NV50_DMA_CONF0_PRIV__S 0x00200000 | |
62 | #define NV50_DMA_CONF0_PART 0x00030000 | |
63 | #define NV50_DMA_CONF0_PART_VM 0x00000000 | |
64 | #define NV50_DMA_CONF0_PART_256 0x00010000 | |
65 | #define NV50_DMA_CONF0_PART_1KB 0x00020000 | |
66 | #define NV50_DMA_CONF0_COMP 0x00000180 | |
67 | #define NV50_DMA_CONF0_COMP_NONE 0x00000000 | |
68 | #define NV50_DMA_CONF0_COMP_VM 0x00000180 | |
69 | #define NV50_DMA_CONF0_TYPE 0x0000007f | |
70 | #define NV50_DMA_CONF0_TYPE_LINEAR 0x00000000 | |
71 | #define NV50_DMA_CONF0_TYPE_VM 0x0000007f | |
72 | ||
80fe155b BS |
73 | /* NVC0:NVD9 */ |
74 | #define NVC0_DMA_CONF0_ENABLE 0x80000000 | |
75 | #define NVC0_DMA_CONF0_PRIV 0x00300000 | |
76 | #define NVC0_DMA_CONF0_PRIV_VM 0x00000000 | |
77 | #define NVC0_DMA_CONF0_PRIV_US 0x00100000 | |
78 | #define NVC0_DMA_CONF0_PRIV__S 0x00200000 | |
79 | #define NVC0_DMA_CONF0_UNKN /* PART? */ 0x00030000 | |
80 | #define NVC0_DMA_CONF0_TYPE 0x000000ff | |
81 | #define NVC0_DMA_CONF0_TYPE_LINEAR 0x00000000 | |
82 | #define NVC0_DMA_CONF0_TYPE_VM 0x000000ff | |
47a1e0fe BS |
83 | |
84 | /* NVD9- */ | |
85 | #define NVD0_DMA_CONF0_ENABLE 0x80000000 | |
86 | #define NVD0_DMA_CONF0_PAGE 0x00000400 | |
87 | #define NVD0_DMA_CONF0_PAGE_LP 0x00000000 | |
88 | #define NVD0_DMA_CONF0_PAGE_SP 0x00000400 | |
89 | #define NVD0_DMA_CONF0_TYPE 0x000000ff | |
90 | #define NVD0_DMA_CONF0_TYPE_LINEAR 0x00000000 | |
91 | #define NVD0_DMA_CONF0_TYPE_VM 0x000000ff | |
80fe155b | 92 | |
9274f4a9 BS |
93 | struct nv_dma_class { |
94 | u32 flags; | |
95 | u32 pad0; | |
96 | u64 start; | |
97 | u64 limit; | |
f756944a | 98 | u32 conf0; |
9274f4a9 BS |
99 | }; |
100 | ||
9456f7d1 BS |
101 | /* DMA FIFO channel classes |
102 | * | |
103 | * 006b: NV03_CHANNEL_DMA | |
9274f4a9 | 104 | * 006e: NV10_CHANNEL_DMA |
503b0f1c | 105 | * 176e: NV17_CHANNEL_DMA |
9274f4a9 | 106 | * 406e: NV40_CHANNEL_DMA |
368be5f1 | 107 | * 506e: NV50_CHANNEL_DMA |
ab285892 | 108 | * 826e: NV84_CHANNEL_DMA |
9274f4a9 | 109 | */ |
9456f7d1 BS |
110 | #define NV03_CHANNEL_DMA_CLASS 0x0000006b |
111 | #define NV10_CHANNEL_DMA_CLASS 0x0000006e | |
112 | #define NV17_CHANNEL_DMA_CLASS 0x0000176e | |
113 | #define NV40_CHANNEL_DMA_CLASS 0x0000406e | |
114 | #define NV50_CHANNEL_DMA_CLASS 0x0000506e | |
115 | #define NV84_CHANNEL_DMA_CLASS 0x0000826e | |
9274f4a9 | 116 | |
a7c6e75e | 117 | struct nv03_channel_dma_class { |
9274f4a9 BS |
118 | u32 pushbuf; |
119 | u32 pad0; | |
120 | u64 offset; | |
121 | }; | |
122 | ||
9456f7d1 BS |
123 | /* Indirect FIFO channel classes |
124 | * | |
125 | * 506f: NV50_CHANNEL_IND | |
9274f4a9 BS |
126 | * 826f: NV84_CHANNEL_IND |
127 | * 906f: NVC0_CHANNEL_IND | |
9456f7d1 | 128 | * a06f: NVE0_CHANNEL_IND |
9274f4a9 BS |
129 | */ |
130 | ||
9456f7d1 BS |
131 | #define NV50_CHANNEL_IND_CLASS 0x0000506f |
132 | #define NV84_CHANNEL_IND_CLASS 0x0000826f | |
133 | #define NVC0_CHANNEL_IND_CLASS 0x0000906f | |
134 | #define NVE0_CHANNEL_IND_CLASS 0x0000a06f | |
135 | ||
dbff2dee | 136 | struct nv50_channel_ind_class { |
9274f4a9 BS |
137 | u32 pushbuf; |
138 | u32 ilength; | |
139 | u64 ioffset; | |
140 | }; | |
141 | ||
9456f7d1 BS |
142 | #define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001 |
143 | #define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002 | |
144 | #define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004 | |
145 | #define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008 | |
146 | #define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010 | |
147 | #define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020 | |
148 | #define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040 | |
dbff2dee BS |
149 | |
150 | struct nve0_channel_ind_class { | |
151 | u32 pushbuf; | |
152 | u32 ilength; | |
153 | u64 ioffset; | |
154 | u32 engine; | |
155 | }; | |
156 | ||
21a5ace0 BS |
157 | /* 0046: NV04_DISP |
158 | */ | |
159 | ||
160 | #define NV04_DISP_CLASS 0x00000046 | |
161 | ||
162 | struct nv04_display_class { | |
163 | }; | |
164 | ||
370c00f9 BS |
165 | /* 5070: NV50_DISP |
166 | * 8270: NV84_DISP | |
167 | * 8370: NVA0_DISP | |
168 | * 8870: NV94_DISP | |
169 | * 8570: NVA3_DISP | |
46654061 BS |
170 | * 9070: NVD0_DISP |
171 | * 9170: NVE0_DISP | |
370c00f9 BS |
172 | */ |
173 | ||
174 | #define NV50_DISP_CLASS 0x00005070 | |
175 | #define NV84_DISP_CLASS 0x00008270 | |
176 | #define NVA0_DISP_CLASS 0x00008370 | |
177 | #define NV94_DISP_CLASS 0x00008870 | |
178 | #define NVA3_DISP_CLASS 0x00008570 | |
46654061 BS |
179 | #define NVD0_DISP_CLASS 0x00009070 |
180 | #define NVE0_DISP_CLASS 0x00009170 | |
370c00f9 | 181 | |
6c5a0424 BS |
182 | #define NV50_DISP_SOR_MTHD 0x00010000 |
183 | #define NV50_DISP_SOR_MTHD_TYPE 0x0000f000 | |
184 | #define NV50_DISP_SOR_MTHD_HEAD 0x00000018 | |
185 | #define NV50_DISP_SOR_MTHD_LINK 0x00000004 | |
186 | #define NV50_DISP_SOR_MTHD_OR 0x00000003 | |
187 | ||
74b66850 BS |
188 | #define NV50_DISP_SOR_PWR 0x00010000 |
189 | #define NV50_DISP_SOR_PWR_STATE 0x00000001 | |
190 | #define NV50_DISP_SOR_PWR_STATE_ON 0x00000001 | |
191 | #define NV50_DISP_SOR_PWR_STATE_OFF 0x00000000 | |
0a9e2b95 | 192 | #define NVA3_DISP_SOR_HDA_ELD 0x00010100 |
1c30cd09 BS |
193 | #define NV84_DISP_SOR_HDMI_PWR 0x00012000 |
194 | #define NV84_DISP_SOR_HDMI_PWR_STATE 0x40000000 | |
195 | #define NV84_DISP_SOR_HDMI_PWR_STATE_OFF 0x00000000 | |
196 | #define NV84_DISP_SOR_HDMI_PWR_STATE_ON 0x40000000 | |
197 | #define NV84_DISP_SOR_HDMI_PWR_MAX_AC_PACKET 0x001f0000 | |
198 | #define NV84_DISP_SOR_HDMI_PWR_REKEY 0x0000007f | |
4a230fa6 BS |
199 | #define NV50_DISP_SOR_LVDS_SCRIPT 0x00013000 |
200 | #define NV50_DISP_SOR_LVDS_SCRIPT_ID 0x0000ffff | |
6c5a0424 | 201 | |
35b21d39 BS |
202 | #define NV50_DISP_DAC_MTHD 0x00020000 |
203 | #define NV50_DISP_DAC_MTHD_TYPE 0x0000f000 | |
204 | #define NV50_DISP_DAC_MTHD_OR 0x00000003 | |
205 | ||
206 | #define NV50_DISP_DAC_PWR 0x00020000 | |
207 | #define NV50_DISP_DAC_PWR_HSYNC 0x00000001 | |
208 | #define NV50_DISP_DAC_PWR_HSYNC_ON 0x00000000 | |
209 | #define NV50_DISP_DAC_PWR_HSYNC_LO 0x00000001 | |
210 | #define NV50_DISP_DAC_PWR_VSYNC 0x00000004 | |
211 | #define NV50_DISP_DAC_PWR_VSYNC_ON 0x00000000 | |
212 | #define NV50_DISP_DAC_PWR_VSYNC_LO 0x00000004 | |
213 | #define NV50_DISP_DAC_PWR_DATA 0x00000010 | |
214 | #define NV50_DISP_DAC_PWR_DATA_ON 0x00000000 | |
215 | #define NV50_DISP_DAC_PWR_DATA_LO 0x00000010 | |
216 | #define NV50_DISP_DAC_PWR_STATE 0x00000040 | |
217 | #define NV50_DISP_DAC_PWR_STATE_ON 0x00000000 | |
218 | #define NV50_DISP_DAC_PWR_STATE_OFF 0x00000040 | |
219 | #define NV50_DISP_DAC_LOAD 0x0002000c | |
220 | #define NV50_DISP_DAC_LOAD_VALUE 0x00000007 | |
221 | ||
370c00f9 BS |
222 | struct nv50_display_class { |
223 | }; | |
224 | ||
225 | /* 507a: NV50_DISP_CURS | |
226 | * 827a: NV84_DISP_CURS | |
227 | * 837a: NVA0_DISP_CURS | |
228 | * 887a: NV94_DISP_CURS | |
229 | * 857a: NVA3_DISP_CURS | |
46654061 BS |
230 | * 907a: NVD0_DISP_CURS |
231 | * 917a: NVE0_DISP_CURS | |
370c00f9 BS |
232 | */ |
233 | ||
234 | #define NV50_DISP_CURS_CLASS 0x0000507a | |
235 | #define NV84_DISP_CURS_CLASS 0x0000827a | |
236 | #define NVA0_DISP_CURS_CLASS 0x0000837a | |
237 | #define NV94_DISP_CURS_CLASS 0x0000887a | |
238 | #define NVA3_DISP_CURS_CLASS 0x0000857a | |
46654061 BS |
239 | #define NVD0_DISP_CURS_CLASS 0x0000907a |
240 | #define NVE0_DISP_CURS_CLASS 0x0000917a | |
370c00f9 BS |
241 | |
242 | struct nv50_display_curs_class { | |
243 | u32 head; | |
244 | }; | |
245 | ||
246 | /* 507b: NV50_DISP_OIMM | |
247 | * 827b: NV84_DISP_OIMM | |
248 | * 837b: NVA0_DISP_OIMM | |
249 | * 887b: NV94_DISP_OIMM | |
250 | * 857b: NVA3_DISP_OIMM | |
46654061 BS |
251 | * 907b: NVD0_DISP_OIMM |
252 | * 917b: NVE0_DISP_OIMM | |
370c00f9 BS |
253 | */ |
254 | ||
255 | #define NV50_DISP_OIMM_CLASS 0x0000507b | |
256 | #define NV84_DISP_OIMM_CLASS 0x0000827b | |
257 | #define NVA0_DISP_OIMM_CLASS 0x0000837b | |
258 | #define NV94_DISP_OIMM_CLASS 0x0000887b | |
259 | #define NVA3_DISP_OIMM_CLASS 0x0000857b | |
46654061 BS |
260 | #define NVD0_DISP_OIMM_CLASS 0x0000907b |
261 | #define NVE0_DISP_OIMM_CLASS 0x0000917b | |
370c00f9 BS |
262 | |
263 | struct nv50_display_oimm_class { | |
264 | u32 head; | |
265 | }; | |
266 | ||
267 | /* 507c: NV50_DISP_SYNC | |
268 | * 827c: NV84_DISP_SYNC | |
269 | * 837c: NVA0_DISP_SYNC | |
270 | * 887c: NV94_DISP_SYNC | |
271 | * 857c: NVA3_DISP_SYNC | |
46654061 BS |
272 | * 907c: NVD0_DISP_SYNC |
273 | * 917c: NVE0_DISP_SYNC | |
370c00f9 BS |
274 | */ |
275 | ||
276 | #define NV50_DISP_SYNC_CLASS 0x0000507c | |
277 | #define NV84_DISP_SYNC_CLASS 0x0000827c | |
278 | #define NVA0_DISP_SYNC_CLASS 0x0000837c | |
279 | #define NV94_DISP_SYNC_CLASS 0x0000887c | |
280 | #define NVA3_DISP_SYNC_CLASS 0x0000857c | |
46654061 BS |
281 | #define NVD0_DISP_SYNC_CLASS 0x0000907c |
282 | #define NVE0_DISP_SYNC_CLASS 0x0000917c | |
370c00f9 BS |
283 | |
284 | struct nv50_display_sync_class { | |
285 | u32 pushbuf; | |
286 | u32 head; | |
287 | }; | |
288 | ||
289 | /* 507d: NV50_DISP_MAST | |
290 | * 827d: NV84_DISP_MAST | |
291 | * 837d: NVA0_DISP_MAST | |
292 | * 887d: NV94_DISP_MAST | |
293 | * 857d: NVA3_DISP_MAST | |
46654061 BS |
294 | * 907d: NVD0_DISP_MAST |
295 | * 917d: NVE0_DISP_MAST | |
370c00f9 BS |
296 | */ |
297 | ||
298 | #define NV50_DISP_MAST_CLASS 0x0000507d | |
299 | #define NV84_DISP_MAST_CLASS 0x0000827d | |
300 | #define NVA0_DISP_MAST_CLASS 0x0000837d | |
301 | #define NV94_DISP_MAST_CLASS 0x0000887d | |
302 | #define NVA3_DISP_MAST_CLASS 0x0000857d | |
46654061 BS |
303 | #define NVD0_DISP_MAST_CLASS 0x0000907d |
304 | #define NVE0_DISP_MAST_CLASS 0x0000917d | |
370c00f9 BS |
305 | |
306 | struct nv50_display_mast_class { | |
307 | u32 pushbuf; | |
308 | }; | |
309 | ||
310 | /* 507e: NV50_DISP_OVLY | |
311 | * 827e: NV84_DISP_OVLY | |
312 | * 837e: NVA0_DISP_OVLY | |
313 | * 887e: NV94_DISP_OVLY | |
314 | * 857e: NVA3_DISP_OVLY | |
46654061 BS |
315 | * 907e: NVD0_DISP_OVLY |
316 | * 917e: NVE0_DISP_OVLY | |
370c00f9 BS |
317 | */ |
318 | ||
319 | #define NV50_DISP_OVLY_CLASS 0x0000507e | |
320 | #define NV84_DISP_OVLY_CLASS 0x0000827e | |
321 | #define NVA0_DISP_OVLY_CLASS 0x0000837e | |
322 | #define NV94_DISP_OVLY_CLASS 0x0000887e | |
323 | #define NVA3_DISP_OVLY_CLASS 0x0000857e | |
46654061 BS |
324 | #define NVD0_DISP_OVLY_CLASS 0x0000907e |
325 | #define NVE0_DISP_OVLY_CLASS 0x0000917e | |
370c00f9 BS |
326 | |
327 | struct nv50_display_ovly_class { | |
328 | u32 pushbuf; | |
329 | u32 head; | |
330 | }; | |
331 | ||
9274f4a9 | 332 | #endif |