[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / include / core / class.h

#ifndef __NOUVEAU_CLASS_H__
#define __NOUVEAU_CLASS_H__

/* Device class
 *
 * 0080: NV_DEVICE
 */
#define NV_DEVICE_CLASS                                              0x00000080

#define NV_DEVICE_DISABLE_IDENTIFY                        0x0000000000000001ULL
#define NV_DEVICE_DISABLE_MMIO                            0x0000000000000002ULL
#define NV_DEVICE_DISABLE_VBIOS                           0x0000000000000004ULL
#define NV_DEVICE_DISABLE_CORE                            0x0000000000000008ULL
#define NV_DEVICE_DISABLE_DISP                            0x0000000000010000ULL
#define NV_DEVICE_DISABLE_FIFO                            0x0000000000020000ULL
#define NV_DEVICE_DISABLE_GRAPH                           0x0000000100000000ULL
#define NV_DEVICE_DISABLE_MPEG                            0x0000000200000000ULL
#define NV_DEVICE_DISABLE_ME                              0x0000000400000000ULL
#define NV_DEVICE_DISABLE_VP                              0x0000000800000000ULL
#define NV_DEVICE_DISABLE_CRYPT                           0x0000001000000000ULL
#define NV_DEVICE_DISABLE_BSP                             0x0000002000000000ULL
#define NV_DEVICE_DISABLE_PPP                             0x0000004000000000ULL
#define NV_DEVICE_DISABLE_COPY0                           0x0000008000000000ULL
#define NV_DEVICE_DISABLE_COPY1                           0x0000010000000000ULL
#define NV_DEVICE_DISABLE_UNK1C1                          0x0000020000000000ULL

struct nv_device_class {
	u64 device;	/* device identifier, ~0 for client default */
	u64 disable;	/* disable particular subsystems */
	u64 debug0;	/* as above, but *internal* ids, and *NOT* ABI */
};

/* DMA object classes
 *
 * 0002: NV_DMA_FROM_MEMORY
 * 0003: NV_DMA_TO_MEMORY
 * 003d: NV_DMA_IN_MEMORY
 */
#define NV_DMA_FROM_MEMORY_CLASS                                     0x00000002
#define NV_DMA_TO_MEMORY_CLASS                                       0x00000003
#define NV_DMA_IN_MEMORY_CLASS                                       0x0000003d

#define NV_DMA_TARGET_MASK                                           0x000000ff
#define NV_DMA_TARGET_VM                                             0x00000000
#define NV_DMA_TARGET_VRAM                                           0x00000001
#define NV_DMA_TARGET_PCI                                            0x00000002
#define NV_DMA_TARGET_PCI_US                                         0x00000003
#define NV_DMA_TARGET_AGP                                            0x00000004
#define NV_DMA_ACCESS_MASK                                           0x00000f00
#define NV_DMA_ACCESS_VM                                             0x00000000
#define NV_DMA_ACCESS_RD                                             0x00000100
#define NV_DMA_ACCESS_WR                                             0x00000200
#define NV_DMA_ACCESS_RDWR                                           0x00000300

/* NV50:NVC0 */
#define NV50_DMA_CONF0_ENABLE                                        0x80000000
#define NV50_DMA_CONF0_PRIV                                          0x00300000
#define NV50_DMA_CONF0_PRIV_VM                                       0x00000000
#define NV50_DMA_CONF0_PRIV_US                                       0x00100000
#define NV50_DMA_CONF0_PRIV__S                                       0x00200000
#define NV50_DMA_CONF0_PART                                          0x00030000
#define NV50_DMA_CONF0_PART_VM                                       0x00000000
#define NV50_DMA_CONF0_PART_256                                      0x00010000
#define NV50_DMA_CONF0_PART_1KB                                      0x00020000
#define NV50_DMA_CONF0_COMP                                          0x00000180
#define NV50_DMA_CONF0_COMP_NONE                                     0x00000000
#define NV50_DMA_CONF0_COMP_VM                                       0x00000180
#define NV50_DMA_CONF0_TYPE                                          0x0000007f
#define NV50_DMA_CONF0_TYPE_LINEAR                                   0x00000000
#define NV50_DMA_CONF0_TYPE_VM                                       0x0000007f

/* NVC0:NVD9 */
#define NVC0_DMA_CONF0_ENABLE                                        0x80000000
#define NVC0_DMA_CONF0_PRIV                                          0x00300000
#define NVC0_DMA_CONF0_PRIV_VM                                       0x00000000
#define NVC0_DMA_CONF0_PRIV_US                                       0x00100000
#define NVC0_DMA_CONF0_PRIV__S                                       0x00200000
#define NVC0_DMA_CONF0_UNKN /* PART? */                              0x00030000
#define NVC0_DMA_CONF0_TYPE                                          0x000000ff
#define NVC0_DMA_CONF0_TYPE_LINEAR                                   0x00000000
#define NVC0_DMA_CONF0_TYPE_VM                                       0x000000ff

struct nv_dma_class {
	u32 flags;
	u32 pad0;
	u64 start;
	u64 limit;
	u32 conf0;
};

/* DMA FIFO channel classes
 *
 * 006b: NV03_CHANNEL_DMA
 * 006e: NV10_CHANNEL_DMA
 * 176e: NV17_CHANNEL_DMA
 * 406e: NV40_CHANNEL_DMA
 * 506e: NV50_CHANNEL_DMA
 * 826e: NV84_CHANNEL_DMA
 */
#define NV03_CHANNEL_DMA_CLASS                                       0x0000006b
#define NV10_CHANNEL_DMA_CLASS                                       0x0000006e
#define NV17_CHANNEL_DMA_CLASS                                       0x0000176e
#define NV40_CHANNEL_DMA_CLASS                                       0x0000406e
#define NV50_CHANNEL_DMA_CLASS                                       0x0000506e
#define NV84_CHANNEL_DMA_CLASS                                       0x0000826e

struct nv03_channel_dma_class {
	u32 pushbuf;
	u32 pad0;
	u64 offset;
};

/* Indirect FIFO channel classes
 *
 * 506f: NV50_CHANNEL_IND
 * 826f: NV84_CHANNEL_IND
 * 906f: NVC0_CHANNEL_IND
 * a06f: NVE0_CHANNEL_IND
 */

#define NV50_CHANNEL_IND_CLASS                                       0x0000506f
#define NV84_CHANNEL_IND_CLASS                                       0x0000826f
#define NVC0_CHANNEL_IND_CLASS                                       0x0000906f
#define NVE0_CHANNEL_IND_CLASS                                       0x0000a06f

struct nv50_channel_ind_class {
	u32 pushbuf;
	u32 ilength;
	u64 ioffset;
};

#define NVE0_CHANNEL_IND_ENGINE_GR                                   0x00000001
#define NVE0_CHANNEL_IND_ENGINE_VP                                   0x00000002
#define NVE0_CHANNEL_IND_ENGINE_PPP                                  0x00000004
#define NVE0_CHANNEL_IND_ENGINE_BSP                                  0x00000008
#define NVE0_CHANNEL_IND_ENGINE_CE0                                  0x00000010
#define NVE0_CHANNEL_IND_ENGINE_CE1                                  0x00000020
#define NVE0_CHANNEL_IND_ENGINE_ENC                                  0x00000040

struct nve0_channel_ind_class {
	u32 pushbuf;
	u32 ilength;
	u64 ioffset;
	u32 engine;
};

#endif
Commit	Line	Data
9274f4a9 BS	1	#ifndef __NOUVEAU_CLASS_H__
	2	#define __NOUVEAU_CLASS_H__
	3
9456f7d1 BS	4	/* Device class
	5	*
	6	* 0080: NV_DEVICE
9274f4a9	7	*/
9456f7d1	8	#define NV_DEVICE_CLASS 0x00000080
9274f4a9 BS	9
	10	#define NV_DEVICE_DISABLE_IDENTIFY 0x0000000000000001ULL
	11	#define NV_DEVICE_DISABLE_MMIO 0x0000000000000002ULL
	12	#define NV_DEVICE_DISABLE_VBIOS 0x0000000000000004ULL
	13	#define NV_DEVICE_DISABLE_CORE 0x0000000000000008ULL
	14	#define NV_DEVICE_DISABLE_DISP 0x0000000000010000ULL
	15	#define NV_DEVICE_DISABLE_FIFO 0x0000000000020000ULL
	16	#define NV_DEVICE_DISABLE_GRAPH 0x0000000100000000ULL
	17	#define NV_DEVICE_DISABLE_MPEG 0x0000000200000000ULL
	18	#define NV_DEVICE_DISABLE_ME 0x0000000400000000ULL
	19	#define NV_DEVICE_DISABLE_VP 0x0000000800000000ULL
	20	#define NV_DEVICE_DISABLE_CRYPT 0x0000001000000000ULL
	21	#define NV_DEVICE_DISABLE_BSP 0x0000002000000000ULL
	22	#define NV_DEVICE_DISABLE_PPP 0x0000004000000000ULL
	23	#define NV_DEVICE_DISABLE_COPY0 0x0000008000000000ULL
	24	#define NV_DEVICE_DISABLE_COPY1 0x0000010000000000ULL
	25	#define NV_DEVICE_DISABLE_UNK1C1 0x0000020000000000ULL
	26
	27	struct nv_device_class {
	28	u64 device; /* device identifier, ~0 for client default */
	29	u64 disable; /* disable particular subsystems */
	30	u64 debug0; /* as above, but internal ids, and NOT ABI */
	31	};
	32
9456f7d1 BS	33	/* DMA object classes
	34	*
	35	* 0002: NV_DMA_FROM_MEMORY
9274f4a9 BS	36	* 0003: NV_DMA_TO_MEMORY
	37	* 003d: NV_DMA_IN_MEMORY
	38	*/
9456f7d1 BS	39	#define NV_DMA_FROM_MEMORY_CLASS 0x00000002
	40	#define NV_DMA_TO_MEMORY_CLASS 0x00000003
	41	#define NV_DMA_IN_MEMORY_CLASS 0x0000003d
9274f4a9 BS	42
	43	#define NV_DMA_TARGET_MASK 0x000000ff
	44	#define NV_DMA_TARGET_VM 0x00000000
	45	#define NV_DMA_TARGET_VRAM 0x00000001
	46	#define NV_DMA_TARGET_PCI 0x00000002
	47	#define NV_DMA_TARGET_PCI_US 0x00000003
	48	#define NV_DMA_TARGET_AGP 0x00000004
	49	#define NV_DMA_ACCESS_MASK 0x00000f00
	50	#define NV_DMA_ACCESS_VM 0x00000000
	51	#define NV_DMA_ACCESS_RD 0x00000100
	52	#define NV_DMA_ACCESS_WR 0x00000200
	53	#define NV_DMA_ACCESS_RDWR 0x00000300
	54
f756944a BS	55	/* NV50:NVC0 */
	56	#define NV50_DMA_CONF0_ENABLE 0x80000000
	57	#define NV50_DMA_CONF0_PRIV 0x00300000
	58	#define NV50_DMA_CONF0_PRIV_VM 0x00000000
	59	#define NV50_DMA_CONF0_PRIV_US 0x00100000
	60	#define NV50_DMA_CONF0_PRIV__S 0x00200000
	61	#define NV50_DMA_CONF0_PART 0x00030000
	62	#define NV50_DMA_CONF0_PART_VM 0x00000000
	63	#define NV50_DMA_CONF0_PART_256 0x00010000
	64	#define NV50_DMA_CONF0_PART_1KB 0x00020000
	65	#define NV50_DMA_CONF0_COMP 0x00000180
	66	#define NV50_DMA_CONF0_COMP_NONE 0x00000000
	67	#define NV50_DMA_CONF0_COMP_VM 0x00000180
	68	#define NV50_DMA_CONF0_TYPE 0x0000007f
	69	#define NV50_DMA_CONF0_TYPE_LINEAR 0x00000000
	70	#define NV50_DMA_CONF0_TYPE_VM 0x0000007f
	71
80fe155b BS	72	/* NVC0:NVD9 */
	73	#define NVC0_DMA_CONF0_ENABLE 0x80000000
	74	#define NVC0_DMA_CONF0_PRIV 0x00300000
	75	#define NVC0_DMA_CONF0_PRIV_VM 0x00000000
	76	#define NVC0_DMA_CONF0_PRIV_US 0x00100000
	77	#define NVC0_DMA_CONF0_PRIV__S 0x00200000
	78	#define NVC0_DMA_CONF0_UNKN /* PART? */ 0x00030000
	79	#define NVC0_DMA_CONF0_TYPE 0x000000ff
	80	#define NVC0_DMA_CONF0_TYPE_LINEAR 0x00000000
	81	#define NVC0_DMA_CONF0_TYPE_VM 0x000000ff
	82
9274f4a9 BS	83	struct nv_dma_class {
	84	u32 flags;
	85	u32 pad0;
	86	u64 start;
	87	u64 limit;
f756944a	88	u32 conf0;
9274f4a9 BS	89	};
9274f4a9 BS	90
9456f7d1 BS	91	/* DMA FIFO channel classes
	92	*
	93	* 006b: NV03_CHANNEL_DMA
9274f4a9	94	* 006e: NV10_CHANNEL_DMA
503b0f1c	95	* 176e: NV17_CHANNEL_DMA
9274f4a9	96	* 406e: NV40_CHANNEL_DMA
368be5f1	97	* 506e: NV50_CHANNEL_DMA
ab285892	98	* 826e: NV84_CHANNEL_DMA
9274f4a9	99	*/
9456f7d1 BS	100	#define NV03_CHANNEL_DMA_CLASS 0x0000006b
	101	#define NV10_CHANNEL_DMA_CLASS 0x0000006e
	102	#define NV17_CHANNEL_DMA_CLASS 0x0000176e
	103	#define NV40_CHANNEL_DMA_CLASS 0x0000406e
	104	#define NV50_CHANNEL_DMA_CLASS 0x0000506e
	105	#define NV84_CHANNEL_DMA_CLASS 0x0000826e
9274f4a9	106
a7c6e75e	107	struct nv03_channel_dma_class {
9274f4a9 BS	108	u32 pushbuf;
	109	u32 pad0;
	110	u64 offset;
	111	};
	112
9456f7d1 BS	113	/* Indirect FIFO channel classes
	114	*
	115	* 506f: NV50_CHANNEL_IND
9274f4a9 BS	116	* 826f: NV84_CHANNEL_IND
9274f4a9 BS	117	* 906f: NVC0_CHANNEL_IND
9456f7d1	118	* a06f: NVE0_CHANNEL_IND
9274f4a9 BS	119	*/
9274f4a9 BS	120
9456f7d1 BS	121	#define NV50_CHANNEL_IND_CLASS 0x0000506f
	122	#define NV84_CHANNEL_IND_CLASS 0x0000826f
	123	#define NVC0_CHANNEL_IND_CLASS 0x0000906f
	124	#define NVE0_CHANNEL_IND_CLASS 0x0000a06f
	125
dbff2dee	126	struct nv50_channel_ind_class {
9274f4a9 BS	127	u32 pushbuf;
	128	u32 ilength;
	129	u64 ioffset;
	130	};
	131
9456f7d1 BS	132	#define NVE0_CHANNEL_IND_ENGINE_GR 0x00000001
	133	#define NVE0_CHANNEL_IND_ENGINE_VP 0x00000002
	134	#define NVE0_CHANNEL_IND_ENGINE_PPP 0x00000004
	135	#define NVE0_CHANNEL_IND_ENGINE_BSP 0x00000008
	136	#define NVE0_CHANNEL_IND_ENGINE_CE0 0x00000010
	137	#define NVE0_CHANNEL_IND_ENGINE_CE1 0x00000020
	138	#define NVE0_CHANNEL_IND_ENGINE_ENC 0x00000040
dbff2dee BS	139
	140	struct nve0_channel_ind_class {
	141	u32 pushbuf;
	142	u32 ilength;
	143	u64 ioffset;
	144	u32 engine;
	145	};
	146
9274f4a9	147	#endif