drm/nouveau/bus: add interfaces/helpers for sequencer
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / include / core / device.h
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1#ifndef __NOUVEAU_DEVICE_H__
2#define __NOUVEAU_DEVICE_H__
3
4#include <core/object.h>
5#include <core/subdev.h>
6#include <core/engine.h>
7
8enum nv_subdev_type {
dded35de 9 NVDEV_ENGINE_DEVICE,
9274f4a9 10 NVDEV_SUBDEV_VBIOS,
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11
12 /* All subdevs from DEVINIT to DEVINIT_LAST will be created before
13 * *any* of them are initialised. This subdev category is used
14 * for any subdevs that the VBIOS init table parsing may call out
15 * to during POST.
16 */
17 NVDEV_SUBDEV_DEVINIT,
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18 NVDEV_SUBDEV_GPIO,
19 NVDEV_SUBDEV_I2C,
54ecff3e 20 NVDEV_SUBDEV_DEVINIT_LAST = NVDEV_SUBDEV_I2C,
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21
22 /* This grouping of subdevs are initialised right after they've
23 * been created, and are allowed to assume any subdevs in the
24 * list above them exist and have been initialised.
25 */
9274f4a9 26 NVDEV_SUBDEV_MXM,
9274f4a9 27 NVDEV_SUBDEV_MC,
a10220bb 28 NVDEV_SUBDEV_BUS,
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29 NVDEV_SUBDEV_TIMER,
30 NVDEV_SUBDEV_FB,
31 NVDEV_SUBDEV_LTCG,
2c1a425e 32 NVDEV_SUBDEV_IBUS,
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33 NVDEV_SUBDEV_INSTMEM,
34 NVDEV_SUBDEV_VM,
35 NVDEV_SUBDEV_BAR,
547807b8 36 NVDEV_SUBDEV_PWR,
9274f4a9 37 NVDEV_SUBDEV_VOLT,
9274f4a9 38 NVDEV_SUBDEV_THERM,
6387e2cb 39 NVDEV_SUBDEV_CLOCK,
7234d023 40
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41 NVDEV_ENGINE_DMAOBJ,
42 NVDEV_ENGINE_FIFO,
43 NVDEV_ENGINE_SW,
44 NVDEV_ENGINE_GR,
45 NVDEV_ENGINE_MPEG,
46 NVDEV_ENGINE_ME,
47 NVDEV_ENGINE_VP,
48 NVDEV_ENGINE_CRYPT,
49 NVDEV_ENGINE_BSP,
50 NVDEV_ENGINE_PPP,
51 NVDEV_ENGINE_COPY0,
52 NVDEV_ENGINE_COPY1,
b0bc5304 53 NVDEV_ENGINE_COPY2,
c42a7aec 54 NVDEV_ENGINE_VIC,
dbff2dee 55 NVDEV_ENGINE_VENC,
9274f4a9 56 NVDEV_ENGINE_DISP,
7234d023 57
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58 NVDEV_SUBDEV_NR,
59};
60
61struct nouveau_device {
dded35de 62 struct nouveau_engine base;
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63 struct list_head head;
64
65 struct pci_dev *pdev;
66 u64 handle;
67
68 const char *cfgopt;
69 const char *dbgopt;
70 const char *name;
71 const char *cname;
72
73 enum {
74 NV_04 = 0x04,
75 NV_10 = 0x10,
4a0ff754 76 NV_11 = 0x11,
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77 NV_20 = 0x20,
78 NV_30 = 0x30,
79 NV_40 = 0x40,
80 NV_50 = 0x50,
81 NV_C0 = 0xc0,
82 NV_D0 = 0xd0,
83 NV_E0 = 0xe0,
84 } card_type;
85 u32 chipset;
86 u32 crystal;
87
88 struct nouveau_oclass *oclass[NVDEV_SUBDEV_NR];
89 struct nouveau_object *subdev[NVDEV_SUBDEV_NR];
90};
91
92static inline struct nouveau_device *
93nv_device(void *obj)
94{
95 struct nouveau_object *object = nv_object(obj);
96 struct nouveau_object *device = object;
97
98 if (device->engine)
99 device = device->engine;
100 if (device->parent)
101 device = device->parent;
102
103#if CONFIG_NOUVEAU_DEBUG >= NV_DBG_PARANOIA
104 if (unlikely(!nv_iclass(device, NV_SUBDEV_CLASS) ||
dded35de 105 (nv_hclass(device) & 0xff) != NVDEV_ENGINE_DEVICE)) {
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106 nv_assert("BAD CAST -> NvDevice, 0x%08x 0x%08x",
107 nv_hclass(object), nv_hclass(device));
108 }
109#endif
110
111 return (void *)device;
112}
113
114static inline struct nouveau_subdev *
115nouveau_subdev(void *obj, int sub)
116{
117 if (nv_device(obj)->subdev[sub])
118 return nv_subdev(nv_device(obj)->subdev[sub]);
119 return NULL;
120}
121
122static inline struct nouveau_engine *
123nouveau_engine(void *obj, int sub)
124{
125 struct nouveau_subdev *subdev = nouveau_subdev(obj, sub);
126 if (subdev && nv_iclass(subdev, NV_ENGINE_CLASS))
127 return nv_engine(subdev);
128 return NULL;
129}
130
131static inline bool
132nv_device_match(struct nouveau_object *object, u16 dev, u16 ven, u16 sub)
133{
134 struct nouveau_device *device = nv_device(object);
135 return device->pdev->device == dev &&
136 device->pdev->subsystem_vendor == ven &&
137 device->pdev->subsystem_device == sub;
138}
139
140#endif
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