[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / clock / nva3.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

#include "pll.h"

#include "nva3.h"

struct nva3_clock_priv {
	struct nouveau_clock base;
	struct nva3_clock_info eng[nv_clk_src_max];
};

static u32 read_clk(struct nva3_clock_priv *, int, bool);
static u32 read_pll(struct nva3_clock_priv *, int, u32);

static u32
read_vco(struct nva3_clock_priv *priv, int clk)
{
	u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	if ((sctl & 0x00000030) != 0x00000030)
		return read_pll(priv, 0x41, 0x00e820);
	return read_pll(priv, 0x42, 0x00e8a0);
}

static u32
read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
{
	u32 sctl, sdiv, sclk;

	/* refclk for the 0xe8xx plls is a fixed frequency */
	if (clk >= 0x40) {
		if (nv_device(priv)->chipset == 0xaf) {
			/* no joke.. seriously.. sigh.. */
			return nv_rd32(priv, 0x00471c) * 1000;
		}

		return nv_device(priv)->crystal;
	}

	sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	if (!ignore_en && !(sctl & 0x00000100))
		return 0;

	switch (sctl & 0x00003000) {
	case 0x00000000:
		return nv_device(priv)->crystal;
	case 0x00002000:
		if (sctl & 0x00000040)
			return 108000;
		return 100000;
	case 0x00003000:
		sclk = read_vco(priv, clk);
		sdiv = ((sctl & 0x003f0000) >> 16) + 2;
		return (sclk * 2) / sdiv;
	default:
		return 0;
	}
}

static u32
read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
{
	u32 ctrl = nv_rd32(priv, pll + 0);
	u32 sclk = 0, P = 1, N = 1, M = 1;

	if (!(ctrl & 0x00000008)) {
		if (ctrl & 0x00000001) {
			u32 coef = nv_rd32(priv, pll + 4);
			M = (coef & 0x000000ff) >> 0;
			N = (coef & 0x0000ff00) >> 8;
			P = (coef & 0x003f0000) >> 16;

			/* no post-divider on these.. */
			if ((pll & 0x00ff00) == 0x00e800)
				P = 1;

			sclk = read_clk(priv, 0x00 + clk, false);
		}
	} else {
		sclk = read_clk(priv, 0x10 + clk, false);
	}

	if (M * P)
		return sclk * N / (M * P);
	return 0;
}

static int
nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
	struct nva3_clock_priv *priv = (void *)clk;

	switch (src) {
	case nv_clk_src_crystal:
		return nv_device(priv)->crystal;
	case nv_clk_src_href:
		return 100000;
	case nv_clk_src_core:
		return read_pll(priv, 0x00, 0x4200);
	case nv_clk_src_shader:
		return read_pll(priv, 0x01, 0x4220);
	case nv_clk_src_mem:
		return read_pll(priv, 0x02, 0x4000);
	case nv_clk_src_disp:
		return read_clk(priv, 0x20, false);
	case nv_clk_src_vdec:
		return read_clk(priv, 0x21, false);
	case nv_clk_src_daemon:
		return read_clk(priv, 0x25, false);
	default:
		nv_error(clk, "invalid clock source %d\n", src);
		return -EINVAL;
	}
}

int
nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
		struct nva3_clock_info *info)
{
	struct nouveau_bios *bios = nouveau_bios(clock);
	struct nva3_clock_priv *priv = (void *)clock;
	struct nvbios_pll limits;
	u32 oclk, sclk, sdiv;
	int P, N, M, diff;
	int ret;

	info->pll = 0;
	info->clk = 0;

	switch (khz) {
	case 27000:
		info->clk = 0x00000100;
		return khz;
	case 100000:
		info->clk = 0x00002100;
		return khz;
	case 108000:
		info->clk = 0x00002140;
		return khz;
	default:
		sclk = read_vco(priv, clk);
		sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
		/* if the clock has a PLL attached, and we can get a within
		 * [-2, 3) MHz of a divider, we'll disable the PLL and use
		 * the divider instead.
		 *
		 * divider can go as low as 2, limited here because NVIDIA
		 * and the VBIOS on my NVA8 seem to prefer using the PLL
		 * for 810MHz - is there a good reason?
		 */
		if (sdiv > 4) {
			oclk = (sclk * 2) / sdiv;
			diff = khz - oclk;
			if (!pll || (diff >= -2000 && diff < 3000)) {
				info->clk = (((sdiv - 2) << 16) | 0x00003100);
				return oclk;
			}
		}

		if (!pll)
			return -ERANGE;
		break;
	}

	ret = nvbios_pll_parse(bios, pll, &limits);
	if (ret)
		return ret;

	limits.refclk = read_clk(priv, clk - 0x10, true);
	if (!limits.refclk)
		return -EINVAL;

	ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
	if (ret >= 0) {
		info->clk = nv_rd32(priv, 0x4120 + (clk * 4));
		info->pll = (P << 16) | (N << 8) | M;
	}

	return ret ? ret : -ERANGE;
}

static int
calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
	 int clk, u32 pll, int idx)
{
	int ret = nva3_clock_info(&priv->base, clk, pll, cstate->domain[idx],
				  &priv->eng[idx]);
	if (ret >= 0)
		return 0;
	return ret;
}

static void
prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
{
	struct nva3_clock_info *info = &priv->eng[idx];
	const u32 src0 = 0x004120 + (clk * 4);
	const u32 src1 = 0x004160 + (clk * 4);
	const u32 ctrl = pll + 0;
	const u32 coef = pll + 4;

	if (info->pll) {
		nv_mask(priv, src0, 0x00000101, 0x00000101);
		nv_wr32(priv, coef, info->pll);
		nv_mask(priv, ctrl, 0x00000015, 0x00000015);
		nv_mask(priv, ctrl, 0x00000010, 0x00000000);
		nv_wait(priv, ctrl, 0x00020000, 0x00020000);
		nv_mask(priv, ctrl, 0x00000010, 0x00000010);
		nv_mask(priv, ctrl, 0x00000008, 0x00000000);
		nv_mask(priv, src1, 0x00000100, 0x00000000);
		nv_mask(priv, src1, 0x00000001, 0x00000000);
	} else {
		nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
		nv_mask(priv, ctrl, 0x00000018, 0x00000018);
		udelay(20);
		nv_mask(priv, ctrl, 0x00000001, 0x00000000);
		nv_mask(priv, src0, 0x00000100, 0x00000000);
		nv_mask(priv, src0, 0x00000001, 0x00000000);
	}
}

static void
prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
{
	struct nva3_clock_info *info = &priv->eng[idx];
	nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
}

static int
nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
	struct nva3_clock_priv *priv = (void *)clk;
	int ret;

	if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
	    (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
	    (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
	    (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)))
		return ret;

	return 0;
}

static int
nva3_clock_prog(struct nouveau_clock *clk)
{
	struct nva3_clock_priv *priv = (void *)clk;
	prog_pll(priv, 0x00, 0x004200, nv_clk_src_core);
	prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
	prog_clk(priv, 0x20, nv_clk_src_disp);
	prog_clk(priv, 0x21, nv_clk_src_vdec);
	return 0;
}

static void
nva3_clock_tidy(struct nouveau_clock *clk)
{
}

static struct nouveau_clocks
nva3_domain[] = {
	{ nv_clk_src_crystal, 0xff },
	{ nv_clk_src_href   , 0xff },
	{ nv_clk_src_core   , 0x00, 0, "core", 1000 },
	{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
	{ nv_clk_src_mem    , 0x02, 0, "memory", 1000 },
	{ nv_clk_src_vdec   , 0x03 },
	{ nv_clk_src_disp   , 0x04 },
	{ nv_clk_src_max }
};

static int
nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		struct nouveau_oclass *oclass, void *data, u32 size,
		struct nouveau_object **pobject)
{
	struct nva3_clock_priv *priv;
	int ret;

	ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0,
				   false, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.read = nva3_clock_read;
	priv->base.calc = nva3_clock_calc;
	priv->base.prog = nva3_clock_prog;
	priv->base.tidy = nva3_clock_tidy;
	return 0;
}

struct nouveau_oclass
nva3_clock_oclass = {
	.handle = NV_SUBDEV(CLOCK, 0xa3),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nva3_clock_ctor,
		.dtor = _nouveau_clock_dtor,
		.init = _nouveau_clock_init,
		.fini = _nouveau_clock_fini,
	},
};
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
70790f4f BS	25	#include <subdev/bios.h>
70790f4f BS	26	#include <subdev/bios/pll.h>
7c856522	27	#include <subdev/timer.h>
70790f4f BS	28
70790f4f BS	29	#include "pll.h"
8aceb7de	30
7c856522 BS	31	#include "nva3.h"
7c856522 BS	32
8aceb7de BS	33	struct nva3_clock_priv {
8aceb7de BS	34	struct nouveau_clock base;
7c856522	35	struct nva3_clock_info eng[nv_clk_src_max];
8aceb7de BS	36	};
8aceb7de BS	37
7c856522 BS	38	static u32 read_clk(struct nva3_clock_priv *, int, bool);
	39	static u32 read_pll(struct nva3_clock_priv *, int, u32);
	40
	41	static u32
	42	read_vco(struct nva3_clock_priv *priv, int clk)
	43	{
	44	u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	45	if ((sctl & 0x00000030) != 0x00000030)
	46	return read_pll(priv, 0x41, 0x00e820);
	47	return read_pll(priv, 0x42, 0x00e8a0);
	48	}
	49
	50	static u32
	51	read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
	52	{
	53	u32 sctl, sdiv, sclk;
	54
	55	/* refclk for the 0xe8xx plls is a fixed frequency */
	56	if (clk >= 0x40) {
	57	if (nv_device(priv)->chipset == 0xaf) {
	58	/* no joke.. seriously.. sigh.. */
	59	return nv_rd32(priv, 0x00471c) * 1000;
	60	}
	61
	62	return nv_device(priv)->crystal;
	63	}
	64
	65	sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	66	if (!ignore_en && !(sctl & 0x00000100))
	67	return 0;
	68
	69	switch (sctl & 0x00003000) {
	70	case 0x00000000:
	71	return nv_device(priv)->crystal;
	72	case 0x00002000:
	73	if (sctl & 0x00000040)
	74	return 108000;
	75	return 100000;
	76	case 0x00003000:
	77	sclk = read_vco(priv, clk);
	78	sdiv = ((sctl & 0x003f0000) >> 16) + 2;
	79	return (sclk * 2) / sdiv;
	80	default:
	81	return 0;
	82	}
	83	}
	84
	85	static u32
	86	read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
	87	{
	88	u32 ctrl = nv_rd32(priv, pll + 0);
	89	u32 sclk = 0, P = 1, N = 1, M = 1;
	90
	91	if (!(ctrl & 0x00000008)) {
	92	if (ctrl & 0x00000001) {
	93	u32 coef = nv_rd32(priv, pll + 4);
	94	M = (coef & 0x000000ff) >> 0;
	95	N = (coef & 0x0000ff00) >> 8;
	96	P = (coef & 0x003f0000) >> 16;
	97
	98	/* no post-divider on these.. */
	99	if ((pll & 0x00ff00) == 0x00e800)
	100	P = 1;
	101
102	sclk = read_clk(priv, 0x00 + clk, false);
103	}
104	} else {
105	sclk = read_clk(priv, 0x10 + clk, false);
106	}
107
108	if (M * P)
109	return sclk * N / (M * P);
110	return 0;
111	}
112
113	static int
114	nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
115	{
116	struct nva3_clock_priv priv = (void )clk;
117
118	switch (src) {
119	case nv_clk_src_crystal:
120	return nv_device(priv)->crystal;
121	case nv_clk_src_href:
122	return 100000;
123	case nv_clk_src_core:
124	return read_pll(priv, 0x00, 0x4200);
125	case nv_clk_src_shader:
126	return read_pll(priv, 0x01, 0x4220);
127	case nv_clk_src_mem:
128	return read_pll(priv, 0x02, 0x4000);
129	case nv_clk_src_disp:
130	return read_clk(priv, 0x20, false);
131	case nv_clk_src_vdec:
132	return read_clk(priv, 0x21, false);
133	case nv_clk_src_daemon:
134	return read_clk(priv, 0x25, false);
135	default:
136	nv_error(clk, "invalid clock source %d\n", src);
137	return -EINVAL;
138	}
139	}
140
d9c39056	141	int
7c856522 BS	142	nva3_clock_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
7c856522 BS	143	struct nva3_clock_info *info)
d9c39056	144	{
7c856522 BS	145	struct nouveau_bios *bios = nouveau_bios(clock);
	146	struct nva3_clock_priv priv = (void )clock;
	147	struct nvbios_pll limits;
	148	u32 oclk, sclk, sdiv;
	149	int P, N, M, diff;
	150	int ret;
	151
	152	info->pll = 0;
	153	info->clk = 0;
	154
	155	switch (khz) {
	156	case 27000:
	157	info->clk = 0x00000100;
	158	return khz;
	159	case 100000:
	160	info->clk = 0x00002100;
	161	return khz;
	162	case 108000:
	163	info->clk = 0x00002140;
	164	return khz;
	165	default:
	166	sclk = read_vco(priv, clk);
	167	sdiv = min((sclk * 2) / (khz - 2999), (u32)65);
	168	/* if the clock has a PLL attached, and we can get a within
	169	* [-2, 3) MHz of a divider, we'll disable the PLL and use
	170	* the divider instead.
	171	*
	172	* divider can go as low as 2, limited here because NVIDIA
	173	* and the VBIOS on my NVA8 seem to prefer using the PLL
	174	* for 810MHz - is there a good reason?
	175	*/
	176	if (sdiv > 4) {
	177	oclk = (sclk * 2) / sdiv;
	178	diff = khz - oclk;
	179	if (!pll \|\| (diff >= -2000 && diff < 3000)) {
	180	info->clk = (((sdiv - 2) << 16) \| 0x00003100);
	181	return oclk;
	182	}
	183	}
	184
	185	if (!pll)
	186	return -ERANGE;
	187	break;
	188	}
d9c39056	189
7c856522 BS	190	ret = nvbios_pll_parse(bios, pll, &limits);
	191	if (ret)
	192	return ret;
	193
	194	limits.refclk = read_clk(priv, clk - 0x10, true);
	195	if (!limits.refclk)
	196	return -EINVAL;
d9c39056	197
7c856522 BS	198	ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
	199	if (ret >= 0) {
	200	info->clk = nv_rd32(priv, 0x4120 + (clk * 4));
	201	info->pll = (P << 16) \| (N << 8) \| M;
d9c39056	202	}
7c856522 BS	203
	204	return ret ? ret : -ERANGE;
	205	}
	206
	207	static int
	208	calc_clk(struct nva3_clock_priv priv, struct nouveau_cstate cstate,
	209	int clk, u32 pll, int idx)
	210	{
	211	int ret = nva3_clock_info(&priv->base, clk, pll, cstate->domain[idx],
	212	&priv->eng[idx]);
	213	if (ret >= 0)
	214	return 0;
d9c39056 ML	215	return ret;
	216	}
	217
7c856522 BS	218	static void
	219	prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
	220	{
	221	struct nva3_clock_info *info = &priv->eng[idx];
	222	const u32 src0 = 0x004120 + (clk * 4);
	223	const u32 src1 = 0x004160 + (clk * 4);
	224	const u32 ctrl = pll + 0;
	225	const u32 coef = pll + 4;
	226
	227	if (info->pll) {
	228	nv_mask(priv, src0, 0x00000101, 0x00000101);
	229	nv_wr32(priv, coef, info->pll);
	230	nv_mask(priv, ctrl, 0x00000015, 0x00000015);
	231	nv_mask(priv, ctrl, 0x00000010, 0x00000000);
	232	nv_wait(priv, ctrl, 0x00020000, 0x00020000);
	233	nv_mask(priv, ctrl, 0x00000010, 0x00000010);
	234	nv_mask(priv, ctrl, 0x00000008, 0x00000000);
	235	nv_mask(priv, src1, 0x00000100, 0x00000000);
	236	nv_mask(priv, src1, 0x00000001, 0x00000000);
	237	} else {
	238	nv_mask(priv, src1, 0x003f3141, 0x00000101 \| info->clk);
	239	nv_mask(priv, ctrl, 0x00000018, 0x00000018);
	240	udelay(20);
	241	nv_mask(priv, ctrl, 0x00000001, 0x00000000);
	242	nv_mask(priv, src0, 0x00000100, 0x00000000);
	243	nv_mask(priv, src0, 0x00000001, 0x00000000);
	244	}
	245	}
	246
	247	static void
	248	prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
	249	{
	250	struct nva3_clock_info *info = &priv->eng[idx];
	251	nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 \| info->clk);
	252	}
	253
	254	static int
	255	nva3_clock_calc(struct nouveau_clock clk, struct nouveau_cstate cstate)
	256	{
	257	struct nva3_clock_priv priv = (void )clk;
	258	int ret;
	259
	260	if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) \|\|
	261	(ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) \|\|
	262	(ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) \|\|
	263	(ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)))
	264	return ret;
	265
	266	return 0;
	267	}
	268
	269	static int
	270	nva3_clock_prog(struct nouveau_clock *clk)
	271	{
	272	struct nva3_clock_priv priv = (void )clk;
	273	prog_pll(priv, 0x00, 0x004200, nv_clk_src_core);
	274	prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
	275	prog_clk(priv, 0x20, nv_clk_src_disp);
	276	prog_clk(priv, 0x21, nv_clk_src_vdec);
	277	return 0;
	278	}
	279
	280	static void
	281	nva3_clock_tidy(struct nouveau_clock *clk)
282	{
283	}
284
285	static struct nouveau_clocks
286	nva3_domain[] = {
287	{ nv_clk_src_crystal, 0xff },
288	{ nv_clk_src_href , 0xff },
289	{ nv_clk_src_core , 0x00, 0, "core", 1000 },
290	{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
291	{ nv_clk_src_mem , 0x02, 0, "memory", 1000 },
292	{ nv_clk_src_vdec , 0x03 },
293	{ nv_clk_src_disp , 0x04 },
294	{ nv_clk_src_max }
295	};
d9c39056	296
8aceb7de BS	297	static int
	298	nva3_clock_ctor(struct nouveau_object parent, struct nouveau_object engine,
	299	struct nouveau_oclass oclass, void data, u32 size,
	300	struct nouveau_object **pobject)
	301	{
	302	struct nva3_clock_priv *priv;
	303	int ret;
	304
bb4d29df AC	305	ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0,
bb4d29df AC	306	false, &priv);
8aceb7de BS	307	*pobject = nv_object(priv);
	308	if (ret)
	309	return ret;
	310
7c856522 BS	311	priv->base.read = nva3_clock_read;
	312	priv->base.calc = nva3_clock_calc;
	313	priv->base.prog = nva3_clock_prog;
	314	priv->base.tidy = nva3_clock_tidy;
8aceb7de BS	315	return 0;
	316	}
	317
	318	struct nouveau_oclass
	319	nva3_clock_oclass = {
	320	.handle = NV_SUBDEV(CLOCK, 0xa3),
	321	.ofuncs = &(struct nouveau_ofuncs) {
	322	.ctor = nva3_clock_ctor,
	323	.dtor = _nouveau_clock_dtor,
	324	.init = _nouveau_clock_init,
	325	.fini = _nouveau_clock_fini,
	326	},
	327	};