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8aceb7de BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
3d896d34 | 23 | * Roy Spliet |
8aceb7de BS |
24 | */ |
25 | ||
70790f4f BS |
26 | #include <subdev/bios.h> |
27 | #include <subdev/bios/pll.h> | |
7c856522 | 28 | #include <subdev/timer.h> |
70790f4f BS |
29 | |
30 | #include "pll.h" | |
8aceb7de | 31 | |
7c856522 BS |
32 | #include "nva3.h" |
33 | ||
8aceb7de BS |
34 | struct nva3_clock_priv { |
35 | struct nouveau_clock base; | |
7c856522 | 36 | struct nva3_clock_info eng[nv_clk_src_max]; |
8aceb7de BS |
37 | }; |
38 | ||
7c856522 BS |
39 | static u32 read_clk(struct nva3_clock_priv *, int, bool); |
40 | static u32 read_pll(struct nva3_clock_priv *, int, u32); | |
41 | ||
42 | static u32 | |
43 | read_vco(struct nva3_clock_priv *priv, int clk) | |
44 | { | |
45 | u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4)); | |
3d896d34 RS |
46 | |
47 | switch (sctl & 0x00000030) { | |
48 | case 0x00000000: | |
49 | return nv_device(priv)->crystal; | |
50 | case 0x00000020: | |
7c856522 | 51 | return read_pll(priv, 0x41, 0x00e820); |
3d896d34 RS |
52 | case 0x00000030: |
53 | return read_pll(priv, 0x42, 0x00e8a0); | |
54 | default: | |
55 | return 0; | |
56 | } | |
7c856522 BS |
57 | } |
58 | ||
59 | static u32 | |
60 | read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en) | |
61 | { | |
62 | u32 sctl, sdiv, sclk; | |
63 | ||
64 | /* refclk for the 0xe8xx plls is a fixed frequency */ | |
65 | if (clk >= 0x40) { | |
66 | if (nv_device(priv)->chipset == 0xaf) { | |
67 | /* no joke.. seriously.. sigh.. */ | |
68 | return nv_rd32(priv, 0x00471c) * 1000; | |
69 | } | |
70 | ||
71 | return nv_device(priv)->crystal; | |
72 | } | |
73 | ||
74 | sctl = nv_rd32(priv, 0x4120 + (clk * 4)); | |
75 | if (!ignore_en && !(sctl & 0x00000100)) | |
76 | return 0; | |
77 | ||
3d896d34 RS |
78 | /* out_alt */ |
79 | if (sctl & 0x00000400) | |
80 | return 108000; | |
81 | ||
82 | /* vco_out */ | |
7c856522 BS |
83 | switch (sctl & 0x00003000) { |
84 | case 0x00000000: | |
3d896d34 RS |
85 | if (!(sctl & 0x00000200)) |
86 | return nv_device(priv)->crystal; | |
87 | return 0; | |
7c856522 BS |
88 | case 0x00002000: |
89 | if (sctl & 0x00000040) | |
90 | return 108000; | |
91 | return 100000; | |
92 | case 0x00003000: | |
3d896d34 RS |
93 | /* vco_enable */ |
94 | if (!(sctl & 0x00000001)) | |
95 | return 0; | |
96 | ||
7c856522 BS |
97 | sclk = read_vco(priv, clk); |
98 | sdiv = ((sctl & 0x003f0000) >> 16) + 2; | |
99 | return (sclk * 2) / sdiv; | |
100 | default: | |
101 | return 0; | |
102 | } | |
103 | } | |
104 | ||
105 | static u32 | |
106 | read_pll(struct nva3_clock_priv *priv, int clk, u32 pll) | |
107 | { | |
108 | u32 ctrl = nv_rd32(priv, pll + 0); | |
109 | u32 sclk = 0, P = 1, N = 1, M = 1; | |
110 | ||
111 | if (!(ctrl & 0x00000008)) { | |
112 | if (ctrl & 0x00000001) { | |
113 | u32 coef = nv_rd32(priv, pll + 4); | |
114 | M = (coef & 0x000000ff) >> 0; | |
115 | N = (coef & 0x0000ff00) >> 8; | |
116 | P = (coef & 0x003f0000) >> 16; | |
117 | ||
3d896d34 RS |
118 | /* no post-divider on these.. |
119 | * XXX: it looks more like two post-"dividers" that | |
120 | * cross each other out in the default RPLL config */ | |
7c856522 BS |
121 | if ((pll & 0x00ff00) == 0x00e800) |
122 | P = 1; | |
123 | ||
124 | sclk = read_clk(priv, 0x00 + clk, false); | |
125 | } | |
126 | } else { | |
127 | sclk = read_clk(priv, 0x10 + clk, false); | |
128 | } | |
129 | ||
130 | if (M * P) | |
131 | return sclk * N / (M * P); | |
132 | return 0; | |
133 | } | |
134 | ||
135 | static int | |
136 | nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) | |
137 | { | |
138 | struct nva3_clock_priv *priv = (void *)clk; | |
139 | ||
140 | switch (src) { | |
141 | case nv_clk_src_crystal: | |
142 | return nv_device(priv)->crystal; | |
143 | case nv_clk_src_href: | |
144 | return 100000; | |
145 | case nv_clk_src_core: | |
146 | return read_pll(priv, 0x00, 0x4200); | |
147 | case nv_clk_src_shader: | |
148 | return read_pll(priv, 0x01, 0x4220); | |
149 | case nv_clk_src_mem: | |
150 | return read_pll(priv, 0x02, 0x4000); | |
151 | case nv_clk_src_disp: | |
152 | return read_clk(priv, 0x20, false); | |
153 | case nv_clk_src_vdec: | |
154 | return read_clk(priv, 0x21, false); | |
155 | case nv_clk_src_daemon: | |
156 | return read_clk(priv, 0x25, false); | |
157 | default: | |
158 | nv_error(clk, "invalid clock source %d\n", src); | |
159 | return -EINVAL; | |
160 | } | |
3d896d34 RS |
161 | |
162 | return 0; | |
7c856522 BS |
163 | } |
164 | ||
d9c39056 | 165 | int |
6a4a47cf | 166 | nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz, |
7c856522 | 167 | struct nva3_clock_info *info) |
d9c39056 | 168 | { |
7c856522 | 169 | struct nva3_clock_priv *priv = (void *)clock; |
6a4a47cf | 170 | u32 oclk, sclk, sdiv, diff; |
7c856522 | 171 | |
7c856522 BS |
172 | info->clk = 0; |
173 | ||
174 | switch (khz) { | |
175 | case 27000: | |
176 | info->clk = 0x00000100; | |
177 | return khz; | |
178 | case 100000: | |
179 | info->clk = 0x00002100; | |
180 | return khz; | |
181 | case 108000: | |
182 | info->clk = 0x00002140; | |
183 | return khz; | |
184 | default: | |
185 | sclk = read_vco(priv, clk); | |
6a4a47cf RS |
186 | sdiv = min((sclk * 2) / khz, (u32)65); |
187 | oclk = (sclk * 2) / sdiv; | |
188 | diff = ((khz + 3000) - oclk); | |
189 | ||
190 | /* When imprecise, play it safe and aim for a clock lower than | |
191 | * desired rather than higher */ | |
192 | if (diff < 0) { | |
193 | sdiv++; | |
194 | oclk = (sclk * 2) / sdiv; | |
195 | } | |
196 | ||
197 | /* divider can go as low as 2, limited here because NVIDIA | |
7c856522 BS |
198 | * and the VBIOS on my NVA8 seem to prefer using the PLL |
199 | * for 810MHz - is there a good reason? | |
6a4a47cf | 200 | * XXX: PLLs with refclk 810MHz? */ |
7c856522 | 201 | if (sdiv > 4) { |
6a4a47cf RS |
202 | info->clk = (((sdiv - 2) << 16) | 0x00003100); |
203 | return oclk; | |
7c856522 BS |
204 | } |
205 | ||
7c856522 BS |
206 | break; |
207 | } | |
d9c39056 | 208 | |
6a4a47cf RS |
209 | return -ERANGE; |
210 | } | |
211 | ||
212 | int | |
213 | nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz, | |
214 | struct nva3_clock_info *info) | |
215 | { | |
216 | struct nouveau_bios *bios = nouveau_bios(clock); | |
217 | struct nva3_clock_priv *priv = (void *)clock; | |
218 | int clk_khz; | |
219 | struct nvbios_pll limits; | |
220 | int P, N, M, diff; | |
221 | int ret; | |
222 | ||
223 | info->pll = 0; | |
224 | ||
225 | /* If we can get a within [-2, 3) MHz of a divider, we'll disable the | |
226 | * PLL and use the divider instead. */ | |
227 | clk_khz = nva3_clk_info(clock, clk, khz, info); | |
228 | diff = khz - clk_khz; | |
229 | if (!pll || (diff >= -2000 && diff < 3000)) { | |
230 | return clk_khz; | |
231 | } | |
232 | ||
233 | /* Try with PLL */ | |
7c856522 BS |
234 | ret = nvbios_pll_parse(bios, pll, &limits); |
235 | if (ret) | |
236 | return ret; | |
237 | ||
6a4a47cf RS |
238 | clk_khz = nva3_clk_info(clock, clk - 0x10, limits.refclk, info); |
239 | if (clk_khz != limits.refclk) | |
7c856522 | 240 | return -EINVAL; |
d9c39056 | 241 | |
7c856522 BS |
242 | ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P); |
243 | if (ret >= 0) { | |
7c856522 | 244 | info->pll = (P << 16) | (N << 8) | M; |
d9c39056 | 245 | } |
7c856522 BS |
246 | |
247 | return ret ? ret : -ERANGE; | |
248 | } | |
249 | ||
250 | static int | |
251 | calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate, | |
252 | int clk, u32 pll, int idx) | |
253 | { | |
6a4a47cf | 254 | int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx], |
7c856522 BS |
255 | &priv->eng[idx]); |
256 | if (ret >= 0) | |
257 | return 0; | |
d9c39056 ML |
258 | return ret; |
259 | } | |
260 | ||
7c856522 BS |
261 | static void |
262 | prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx) | |
263 | { | |
264 | struct nva3_clock_info *info = &priv->eng[idx]; | |
265 | const u32 src0 = 0x004120 + (clk * 4); | |
266 | const u32 src1 = 0x004160 + (clk * 4); | |
267 | const u32 ctrl = pll + 0; | |
268 | const u32 coef = pll + 4; | |
269 | ||
270 | if (info->pll) { | |
6a4a47cf | 271 | nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk); |
7c856522 BS |
272 | nv_wr32(priv, coef, info->pll); |
273 | nv_mask(priv, ctrl, 0x00000015, 0x00000015); | |
274 | nv_mask(priv, ctrl, 0x00000010, 0x00000000); | |
275 | nv_wait(priv, ctrl, 0x00020000, 0x00020000); | |
276 | nv_mask(priv, ctrl, 0x00000010, 0x00000010); | |
277 | nv_mask(priv, ctrl, 0x00000008, 0x00000000); | |
278 | nv_mask(priv, src1, 0x00000100, 0x00000000); | |
279 | nv_mask(priv, src1, 0x00000001, 0x00000000); | |
280 | } else { | |
281 | nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk); | |
282 | nv_mask(priv, ctrl, 0x00000018, 0x00000018); | |
283 | udelay(20); | |
284 | nv_mask(priv, ctrl, 0x00000001, 0x00000000); | |
285 | nv_mask(priv, src0, 0x00000100, 0x00000000); | |
286 | nv_mask(priv, src0, 0x00000001, 0x00000000); | |
287 | } | |
288 | } | |
289 | ||
290 | static void | |
291 | prog_clk(struct nva3_clock_priv *priv, int clk, int idx) | |
292 | { | |
293 | struct nva3_clock_info *info = &priv->eng[idx]; | |
294 | nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk); | |
295 | } | |
296 | ||
297 | static int | |
298 | nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) | |
299 | { | |
300 | struct nva3_clock_priv *priv = (void *)clk; | |
301 | int ret; | |
302 | ||
303 | if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) || | |
304 | (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) || | |
305 | (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) || | |
306 | (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec))) | |
307 | return ret; | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
312 | static int | |
313 | nva3_clock_prog(struct nouveau_clock *clk) | |
314 | { | |
315 | struct nva3_clock_priv *priv = (void *)clk; | |
316 | prog_pll(priv, 0x00, 0x004200, nv_clk_src_core); | |
317 | prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader); | |
318 | prog_clk(priv, 0x20, nv_clk_src_disp); | |
319 | prog_clk(priv, 0x21, nv_clk_src_vdec); | |
320 | return 0; | |
321 | } | |
322 | ||
323 | static void | |
324 | nva3_clock_tidy(struct nouveau_clock *clk) | |
325 | { | |
326 | } | |
327 | ||
328 | static struct nouveau_clocks | |
329 | nva3_domain[] = { | |
330 | { nv_clk_src_crystal, 0xff }, | |
331 | { nv_clk_src_href , 0xff }, | |
332 | { nv_clk_src_core , 0x00, 0, "core", 1000 }, | |
333 | { nv_clk_src_shader , 0x01, 0, "shader", 1000 }, | |
334 | { nv_clk_src_mem , 0x02, 0, "memory", 1000 }, | |
335 | { nv_clk_src_vdec , 0x03 }, | |
336 | { nv_clk_src_disp , 0x04 }, | |
337 | { nv_clk_src_max } | |
338 | }; | |
d9c39056 | 339 | |
8aceb7de BS |
340 | static int |
341 | nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |
342 | struct nouveau_oclass *oclass, void *data, u32 size, | |
343 | struct nouveau_object **pobject) | |
344 | { | |
345 | struct nva3_clock_priv *priv; | |
346 | int ret; | |
347 | ||
bb4d29df AC |
348 | ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0, |
349 | false, &priv); | |
8aceb7de BS |
350 | *pobject = nv_object(priv); |
351 | if (ret) | |
352 | return ret; | |
353 | ||
7c856522 BS |
354 | priv->base.read = nva3_clock_read; |
355 | priv->base.calc = nva3_clock_calc; | |
356 | priv->base.prog = nva3_clock_prog; | |
357 | priv->base.tidy = nva3_clock_tidy; | |
8aceb7de BS |
358 | return 0; |
359 | } | |
360 | ||
361 | struct nouveau_oclass | |
362 | nva3_clock_oclass = { | |
363 | .handle = NV_SUBDEV(CLOCK, 0xa3), | |
364 | .ofuncs = &(struct nouveau_ofuncs) { | |
365 | .ctor = nva3_clock_ctor, | |
366 | .dtor = _nouveau_clock_dtor, | |
367 | .init = _nouveau_clock_init, | |
368 | .fini = _nouveau_clock_fini, | |
369 | }, | |
370 | }; |