[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / clock / nva3.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 *          Roy Spliet
 */

#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

#include "pll.h"

#include "nva3.h"

struct nva3_clock_priv {
	struct nouveau_clock base;
	struct nva3_clock_info eng[nv_clk_src_max];
};

static u32 read_clk(struct nva3_clock_priv *, int, bool);
static u32 read_pll(struct nva3_clock_priv *, int, u32);

static u32
read_vco(struct nva3_clock_priv *priv, int clk)
{
	u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));

	switch (sctl & 0x00000030) {
	case 0x00000000:
		return nv_device(priv)->crystal;
	case 0x00000020:
		return read_pll(priv, 0x41, 0x00e820);
	case 0x00000030:
		return read_pll(priv, 0x42, 0x00e8a0);
	default:
		return 0;
	}
}

static u32
read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
{
	u32 sctl, sdiv, sclk;

	/* refclk for the 0xe8xx plls is a fixed frequency */
	if (clk >= 0x40) {
		if (nv_device(priv)->chipset == 0xaf) {
			/* no joke.. seriously.. sigh.. */
			return nv_rd32(priv, 0x00471c) * 1000;
		}

		return nv_device(priv)->crystal;
	}

	sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	if (!ignore_en && !(sctl & 0x00000100))
		return 0;

	/* out_alt */
	if (sctl & 0x00000400)
		return 108000;

	/* vco_out */
	switch (sctl & 0x00003000) {
	case 0x00000000:
		if (!(sctl & 0x00000200))
			return nv_device(priv)->crystal;
		return 0;
	case 0x00002000:
		if (sctl & 0x00000040)
			return 108000;
		return 100000;
	case 0x00003000:
		/* vco_enable */
		if (!(sctl & 0x00000001))
			return 0;

		sclk = read_vco(priv, clk);
		sdiv = ((sctl & 0x003f0000) >> 16) + 2;
		return (sclk * 2) / sdiv;
	default:
		return 0;
	}
}

static u32
read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
{
	u32 ctrl = nv_rd32(priv, pll + 0);
	u32 sclk = 0, P = 1, N = 1, M = 1;

	if (!(ctrl & 0x00000008)) {
		if (ctrl & 0x00000001) {
			u32 coef = nv_rd32(priv, pll + 4);
			M = (coef & 0x000000ff) >> 0;
			N = (coef & 0x0000ff00) >> 8;
			P = (coef & 0x003f0000) >> 16;

			/* no post-divider on these..
			 * XXX: it looks more like two post-"dividers" that
			 * cross each other out in the default RPLL config */
			if ((pll & 0x00ff00) == 0x00e800)
				P = 1;

			sclk = read_clk(priv, 0x00 + clk, false);
		}
	} else {
		sclk = read_clk(priv, 0x10 + clk, false);
	}

	if (M * P)
		return sclk * N / (M * P);
	return 0;
}

static int
nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
	struct nva3_clock_priv *priv = (void *)clk;
	u32 hsrc;

	switch (src) {
	case nv_clk_src_crystal:
		return nv_device(priv)->crystal;
	case nv_clk_src_core:
		return read_pll(priv, 0x00, 0x4200);
	case nv_clk_src_shader:
		return read_pll(priv, 0x01, 0x4220);
	case nv_clk_src_mem:
		return read_pll(priv, 0x02, 0x4000);
	case nv_clk_src_disp:
		return read_clk(priv, 0x20, false);
	case nv_clk_src_vdec:
		return read_clk(priv, 0x21, false);
	case nv_clk_src_daemon:
		return read_clk(priv, 0x25, false);
	case nv_clk_src_host:
		hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28;
		switch (hsrc) {
		case 0:
			return read_clk(priv, 0x1d, false);
		case 2:
		case 3:
			return 277000;
		default:
			nv_error(clk, "unknown HOST clock source %d\n", hsrc);
			return -EINVAL;
		}
	default:
		nv_error(clk, "invalid clock source %d\n", src);
		return -EINVAL;
	}

	return 0;
}

int
nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
		struct nva3_clock_info *info)
{
	struct nva3_clock_priv *priv = (void *)clock;
	u32 oclk, sclk, sdiv, diff;

	info->clk = 0;

	switch (khz) {
	case 27000:
		info->clk = 0x00000100;
		return khz;
	case 100000:
		info->clk = 0x00002100;
		return khz;
	case 108000:
		info->clk = 0x00002140;
		return khz;
	default:
		sclk = read_vco(priv, clk);
		sdiv = min((sclk * 2) / khz, (u32)65);
		oclk = (sclk * 2) / sdiv;
		diff = ((khz + 3000) - oclk);

		/* When imprecise, play it safe and aim for a clock lower than
		 * desired rather than higher */
		if (diff < 0) {
			sdiv++;
			oclk = (sclk * 2) / sdiv;
		}

		/* divider can go as low as 2, limited here because NVIDIA
		 * and the VBIOS on my NVA8 seem to prefer using the PLL
		 * for 810MHz - is there a good reason?
		 * XXX: PLLs with refclk 810MHz?  */
		if (sdiv > 4) {
			info->clk = (((sdiv - 2) << 16) | 0x00003100);
			return oclk;
		}

		break;
	}

	return -ERANGE;
}

int
nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
		struct nva3_clock_info *info)
{
	struct nouveau_bios *bios = nouveau_bios(clock);
	struct nva3_clock_priv *priv = (void *)clock;
	int clk_khz;
	struct nvbios_pll limits;
	int P, N, M, diff;
	int ret;

	info->pll = 0;

	/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
	 * PLL and use the divider instead. */
	clk_khz = nva3_clk_info(clock, clk, khz, info);
	diff = khz - clk_khz;
	if (!pll || (diff >= -2000 && diff < 3000)) {
		return clk_khz;
	}

	/* Try with PLL */
	ret = nvbios_pll_parse(bios, pll, &limits);
	if (ret)
		return ret;

	clk_khz = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
	if (clk_khz != limits.refclk)
		return -EINVAL;

	ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
	if (ret >= 0) {
		info->pll = (P << 16) | (N << 8) | M;
	}

	return ret ? ret : -ERANGE;
}

static int
calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
	 int clk, u32 pll, int idx)
{
	int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
				  &priv->eng[idx]);
	if (ret >= 0)
		return 0;
	return ret;
}

static int
calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
{
	int ret = 0;
	u32 kHz = cstate->domain[nv_clk_src_host];
	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];

	if (kHz == 277000) {
		info->clk = 0;
		info->host_out = NVA3_HOST_277;
		return 0;
	}

	info->host_out = NVA3_HOST_CLK;

	ret = nva3_clk_info(&priv->base, 0x1d, kHz, info);
	if (ret >= 0)
		return 0;
	return ret;
}

static void
disable_clk_src(struct nva3_clock_priv *priv, u32 src)
{
	nv_mask(priv, src, 0x00000100, 0x00000000);
	nv_mask(priv, src, 0x00000001, 0x00000000);
}

static void
prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
{
	struct nva3_clock_info *info = &priv->eng[idx];
	const u32 src0 = 0x004120 + (clk * 4);
	const u32 src1 = 0x004160 + (clk * 4);
	const u32 ctrl = pll + 0;
	const u32 coef = pll + 4;

	if (info->pll) {
		nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk);
		nv_wr32(priv, coef, info->pll);
		nv_mask(priv, ctrl, 0x00000015, 0x00000015);
		nv_mask(priv, ctrl, 0x00000010, 0x00000000);
		nv_wait(priv, ctrl, 0x00020000, 0x00020000);
		nv_mask(priv, ctrl, 0x00000010, 0x00000010);
		nv_mask(priv, ctrl, 0x00000008, 0x00000000);
		disable_clk_src(priv, src1);
	} else {
		nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
		nv_mask(priv, ctrl, 0x00000018, 0x00000018);
		udelay(20);
		nv_mask(priv, ctrl, 0x00000001, 0x00000000);
		disable_clk_src(priv, src0);
	}
}

static void
prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
{
	struct nva3_clock_info *info = &priv->eng[idx];
	nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
}

static void
prog_host(struct nva3_clock_priv *priv)
{
	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
	u32 hsrc = (nv_rd32(priv, 0xc040));

	switch (info->host_out) {
	case NVA3_HOST_277:
		if ((hsrc & 0x30000000) == 0) {
			nv_wr32(priv, 0xc040, hsrc | 0x20000000);
			disable_clk_src(priv, 0x4194);
		}
		break;
	case NVA3_HOST_CLK:
		prog_clk(priv, 0x1d, nv_clk_src_host);
		if ((hsrc & 0x30000000) >= 0x20000000) {
			nv_wr32(priv, 0xc040, hsrc & ~0x30000000);
		}
		break;
	default:
		break;
	}

	/* This seems to be a clock gating factor on idle, always set to 64 */
	nv_wr32(priv, 0xc044, 0x3e);
}

static int
nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
	struct nva3_clock_priv *priv = (void *)clk;
	int ret;

	if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
	    (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
	    (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
	    (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) ||
	    (ret = calc_host(priv, cstate)))
		return ret;

	return 0;
}

static int
nva3_clock_prog(struct nouveau_clock *clk)
{
	struct nva3_clock_priv *priv = (void *)clk;
	prog_pll(priv, 0x00, 0x004200, nv_clk_src_core);
	prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
	prog_clk(priv, 0x20, nv_clk_src_disp);
	prog_clk(priv, 0x21, nv_clk_src_vdec);
	prog_host(priv);
	return 0;
}

static void
nva3_clock_tidy(struct nouveau_clock *clk)
{
}

static struct nouveau_clocks
nva3_domain[] = {
	{ nv_clk_src_crystal, 0xff },
	{ nv_clk_src_core   , 0x00, 0, "core", 1000 },
	{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
	{ nv_clk_src_mem    , 0x02, 0, "memory", 1000 },
	{ nv_clk_src_vdec   , 0x03 },
	{ nv_clk_src_disp   , 0x04 },
	{ nv_clk_src_host   , 0x05 },
	{ nv_clk_src_max }
};

static int
nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		struct nouveau_oclass *oclass, void *data, u32 size,
		struct nouveau_object **pobject)
{
	struct nva3_clock_priv *priv;
	int ret;

	ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0,
				   false, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.read = nva3_clock_read;
	priv->base.calc = nva3_clock_calc;
	priv->base.prog = nva3_clock_prog;
	priv->base.tidy = nva3_clock_tidy;
	return 0;
}

struct nouveau_oclass
nva3_clock_oclass = {
	.handle = NV_SUBDEV(CLOCK, 0xa3),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nva3_clock_ctor,
		.dtor = _nouveau_clock_dtor,
		.init = _nouveau_clock_init,
		.fini = _nouveau_clock_fini,
	},
};
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
3d896d34	23	* Roy Spliet
8aceb7de BS	24	*/
8aceb7de BS	25
70790f4f BS	26	#include <subdev/bios.h>
70790f4f BS	27	#include <subdev/bios/pll.h>
7c856522	28	#include <subdev/timer.h>
70790f4f BS	29
70790f4f BS	30	#include "pll.h"
8aceb7de	31
7c856522 BS	32	#include "nva3.h"
7c856522 BS	33
8aceb7de BS	34	struct nva3_clock_priv {
8aceb7de BS	35	struct nouveau_clock base;
7c856522	36	struct nva3_clock_info eng[nv_clk_src_max];
8aceb7de BS	37	};
8aceb7de BS	38
7c856522 BS	39	static u32 read_clk(struct nva3_clock_priv *, int, bool);
	40	static u32 read_pll(struct nva3_clock_priv *, int, u32);
	41
	42	static u32
	43	read_vco(struct nva3_clock_priv *priv, int clk)
	44	{
	45	u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
3d896d34 RS	46
	47	switch (sctl & 0x00000030) {
	48	case 0x00000000:
	49	return nv_device(priv)->crystal;
	50	case 0x00000020:
7c856522	51	return read_pll(priv, 0x41, 0x00e820);
3d896d34 RS	52	case 0x00000030:
	53	return read_pll(priv, 0x42, 0x00e8a0);
	54	default:
	55	return 0;
	56	}
7c856522 BS	57	}
	58
	59	static u32
	60	read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
	61	{
	62	u32 sctl, sdiv, sclk;
	63
	64	/* refclk for the 0xe8xx plls is a fixed frequency */
	65	if (clk >= 0x40) {
	66	if (nv_device(priv)->chipset == 0xaf) {
	67	/* no joke.. seriously.. sigh.. */
	68	return nv_rd32(priv, 0x00471c) * 1000;
	69	}
	70
	71	return nv_device(priv)->crystal;
	72	}
	73
	74	sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	75	if (!ignore_en && !(sctl & 0x00000100))
	76	return 0;
	77
3d896d34 RS	78	/* out_alt */
	79	if (sctl & 0x00000400)
	80	return 108000;
	81
	82	/* vco_out */
7c856522 BS	83	switch (sctl & 0x00003000) {
7c856522 BS	84	case 0x00000000:
3d896d34 RS	85	if (!(sctl & 0x00000200))
	86	return nv_device(priv)->crystal;
	87	return 0;
7c856522 BS	88	case 0x00002000:
	89	if (sctl & 0x00000040)
	90	return 108000;
	91	return 100000;
	92	case 0x00003000:
3d896d34 RS	93	/* vco_enable */
	94	if (!(sctl & 0x00000001))
	95	return 0;
	96
7c856522 BS	97	sclk = read_vco(priv, clk);
	98	sdiv = ((sctl & 0x003f0000) >> 16) + 2;
	99	return (sclk * 2) / sdiv;
	100	default:
	101	return 0;
	102	}
	103	}
	104
	105	static u32
	106	read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
	107	{
	108	u32 ctrl = nv_rd32(priv, pll + 0);
	109	u32 sclk = 0, P = 1, N = 1, M = 1;
	110
	111	if (!(ctrl & 0x00000008)) {
	112	if (ctrl & 0x00000001) {
	113	u32 coef = nv_rd32(priv, pll + 4);
	114	M = (coef & 0x000000ff) >> 0;
	115	N = (coef & 0x0000ff00) >> 8;
	116	P = (coef & 0x003f0000) >> 16;
	117
3d896d34 RS	118	/* no post-divider on these..
	119	* XXX: it looks more like two post-"dividers" that
	120	* cross each other out in the default RPLL config */
7c856522 BS	121	if ((pll & 0x00ff00) == 0x00e800)
	122	P = 1;
	123
	124	sclk = read_clk(priv, 0x00 + clk, false);
	125	}
	126	} else {
	127	sclk = read_clk(priv, 0x10 + clk, false);
	128	}
	129
	130	if (M * P)
	131	return sclk * N / (M * P);
	132	return 0;
	133	}
	134
	135	static int
	136	nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
	137	{
	138	struct nva3_clock_priv priv = (void )clk;
70c7995d	139	u32 hsrc;
7c856522 BS	140
	141	switch (src) {
	142	case nv_clk_src_crystal:
	143	return nv_device(priv)->crystal;
7c856522 BS	144	case nv_clk_src_core:
	145	return read_pll(priv, 0x00, 0x4200);
	146	case nv_clk_src_shader:
	147	return read_pll(priv, 0x01, 0x4220);
	148	case nv_clk_src_mem:
	149	return read_pll(priv, 0x02, 0x4000);
	150	case nv_clk_src_disp:
	151	return read_clk(priv, 0x20, false);
	152	case nv_clk_src_vdec:
	153	return read_clk(priv, 0x21, false);
	154	case nv_clk_src_daemon:
	155	return read_clk(priv, 0x25, false);
70c7995d RS	156	case nv_clk_src_host:
	157	hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28;
	158	switch (hsrc) {
	159	case 0:
	160	return read_clk(priv, 0x1d, false);
	161	case 2:
	162	case 3:
	163	return 277000;
	164	default:
	165	nv_error(clk, "unknown HOST clock source %d\n", hsrc);
	166	return -EINVAL;
	167	}
7c856522 BS	168	default:
	169	nv_error(clk, "invalid clock source %d\n", src);
	170	return -EINVAL;
	171	}
3d896d34 RS	172
3d896d34 RS	173	return 0;
7c856522 BS	174	}
7c856522 BS	175
d9c39056	176	int
6a4a47cf	177	nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
7c856522	178	struct nva3_clock_info *info)
d9c39056	179	{
7c856522	180	struct nva3_clock_priv priv = (void )clock;
6a4a47cf	181	u32 oclk, sclk, sdiv, diff;
7c856522	182
7c856522 BS	183	info->clk = 0;
	184
	185	switch (khz) {
	186	case 27000:
	187	info->clk = 0x00000100;
	188	return khz;
	189	case 100000:
	190	info->clk = 0x00002100;
	191	return khz;
	192	case 108000:
	193	info->clk = 0x00002140;
	194	return khz;
	195	default:
	196	sclk = read_vco(priv, clk);
6a4a47cf RS	197	sdiv = min((sclk * 2) / khz, (u32)65);
	198	oclk = (sclk * 2) / sdiv;
	199	diff = ((khz + 3000) - oclk);
	200
	201	/* When imprecise, play it safe and aim for a clock lower than
	202	* desired rather than higher */
	203	if (diff < 0) {
	204	sdiv++;
	205	oclk = (sclk * 2) / sdiv;
	206	}
	207
	208	/* divider can go as low as 2, limited here because NVIDIA
7c856522 BS	209	* and the VBIOS on my NVA8 seem to prefer using the PLL
7c856522 BS	210	* for 810MHz - is there a good reason?
6a4a47cf	211	* XXX: PLLs with refclk 810MHz? */
7c856522	212	if (sdiv > 4) {
6a4a47cf RS	213	info->clk = (((sdiv - 2) << 16) \| 0x00003100);
6a4a47cf RS	214	return oclk;
7c856522 BS	215	}
7c856522 BS	216
7c856522 BS	217	break;
7c856522 BS	218	}
d9c39056	219
6a4a47cf RS	220	return -ERANGE;
	221	}
	222
	223	int
	224	nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
	225	struct nva3_clock_info *info)
	226	{
	227	struct nouveau_bios *bios = nouveau_bios(clock);
	228	struct nva3_clock_priv priv = (void )clock;
	229	int clk_khz;
	230	struct nvbios_pll limits;
	231	int P, N, M, diff;
	232	int ret;
	233
	234	info->pll = 0;
	235
	236	/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
	237	* PLL and use the divider instead. */
	238	clk_khz = nva3_clk_info(clock, clk, khz, info);
	239	diff = khz - clk_khz;
	240	if (!pll \|\| (diff >= -2000 && diff < 3000)) {
	241	return clk_khz;
	242	}
	243
	244	/* Try with PLL */
7c856522 BS	245	ret = nvbios_pll_parse(bios, pll, &limits);
	246	if (ret)
	247	return ret;
	248
6a4a47cf RS	249	clk_khz = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
6a4a47cf RS	250	if (clk_khz != limits.refclk)
7c856522	251	return -EINVAL;
d9c39056	252
7c856522 BS	253	ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
7c856522 BS	254	if (ret >= 0) {
7c856522	255	info->pll = (P << 16) \| (N << 8) \| M;
d9c39056	256	}
7c856522 BS	257
	258	return ret ? ret : -ERANGE;
	259	}
	260
	261	static int
	262	calc_clk(struct nva3_clock_priv priv, struct nouveau_cstate cstate,
	263	int clk, u32 pll, int idx)
	264	{
6a4a47cf	265	int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
7c856522 BS	266	&priv->eng[idx]);
	267	if (ret >= 0)
	268	return 0;
d9c39056 ML	269	return ret;
	270	}
	271
70c7995d RS	272	static int
	273	calc_host(struct nva3_clock_priv priv, struct nouveau_cstate cstate)
	274	{
	275	int ret = 0;
	276	u32 kHz = cstate->domain[nv_clk_src_host];
	277	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
	278
	279	if (kHz == 277000) {
	280	info->clk = 0;
	281	info->host_out = NVA3_HOST_277;
	282	return 0;
	283	}
	284
	285	info->host_out = NVA3_HOST_CLK;
	286
	287	ret = nva3_clk_info(&priv->base, 0x1d, kHz, info);
	288	if (ret >= 0)
	289	return 0;
	290	return ret;
	291	}
	292
	293	static void
	294	disable_clk_src(struct nva3_clock_priv *priv, u32 src)
	295	{
	296	nv_mask(priv, src, 0x00000100, 0x00000000);
	297	nv_mask(priv, src, 0x00000001, 0x00000000);
	298	}
	299
7c856522 BS	300	static void
	301	prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
	302	{
	303	struct nva3_clock_info *info = &priv->eng[idx];
	304	const u32 src0 = 0x004120 + (clk * 4);
	305	const u32 src1 = 0x004160 + (clk * 4);
	306	const u32 ctrl = pll + 0;
	307	const u32 coef = pll + 4;
	308
	309	if (info->pll) {
6a4a47cf	310	nv_mask(priv, src0, 0x003f3141, 0x00000101 \| info->clk);
7c856522 BS	311	nv_wr32(priv, coef, info->pll);
	312	nv_mask(priv, ctrl, 0x00000015, 0x00000015);
	313	nv_mask(priv, ctrl, 0x00000010, 0x00000000);
	314	nv_wait(priv, ctrl, 0x00020000, 0x00020000);
	315	nv_mask(priv, ctrl, 0x00000010, 0x00000010);
	316	nv_mask(priv, ctrl, 0x00000008, 0x00000000);
70c7995d	317	disable_clk_src(priv, src1);
7c856522 BS	318	} else {
	319	nv_mask(priv, src1, 0x003f3141, 0x00000101 \| info->clk);
	320	nv_mask(priv, ctrl, 0x00000018, 0x00000018);
	321	udelay(20);
	322	nv_mask(priv, ctrl, 0x00000001, 0x00000000);
70c7995d	323	disable_clk_src(priv, src0);
7c856522 BS	324	}
	325	}
	326
	327	static void
	328	prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
	329	{
	330	struct nva3_clock_info *info = &priv->eng[idx];
	331	nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 \| info->clk);
	332	}
	333
70c7995d RS	334	static void
	335	prog_host(struct nva3_clock_priv *priv)
	336	{
	337	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
	338	u32 hsrc = (nv_rd32(priv, 0xc040));
	339
	340	switch (info->host_out) {
	341	case NVA3_HOST_277:
	342	if ((hsrc & 0x30000000) == 0) {
	343	nv_wr32(priv, 0xc040, hsrc \| 0x20000000);
	344	disable_clk_src(priv, 0x4194);
	345	}
	346	break;
	347	case NVA3_HOST_CLK:
	348	prog_clk(priv, 0x1d, nv_clk_src_host);
	349	if ((hsrc & 0x30000000) >= 0x20000000) {
	350	nv_wr32(priv, 0xc040, hsrc & ~0x30000000);
	351	}
	352	break;
	353	default:
	354	break;
	355	}
	356
	357	/* This seems to be a clock gating factor on idle, always set to 64 */
	358	nv_wr32(priv, 0xc044, 0x3e);
	359	}
	360
7c856522 BS	361	static int
	362	nva3_clock_calc(struct nouveau_clock clk, struct nouveau_cstate cstate)
	363	{
	364	struct nva3_clock_priv priv = (void )clk;
	365	int ret;
	366
	367	if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) \|\|
	368	(ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) \|\|
	369	(ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) \|\|
70c7995d RS	370	(ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) \|\|
70c7995d RS	371	(ret = calc_host(priv, cstate)))
7c856522 BS	372	return ret;
	373
	374	return 0;
	375	}
	376
	377	static int
	378	nva3_clock_prog(struct nouveau_clock *clk)
	379	{
	380	struct nva3_clock_priv priv = (void )clk;
	381	prog_pll(priv, 0x00, 0x004200, nv_clk_src_core);
	382	prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
	383	prog_clk(priv, 0x20, nv_clk_src_disp);
	384	prog_clk(priv, 0x21, nv_clk_src_vdec);
70c7995d	385	prog_host(priv);
7c856522 BS	386	return 0;
	387	}
	388
	389	static void
	390	nva3_clock_tidy(struct nouveau_clock *clk)
	391	{
	392	}
	393
	394	static struct nouveau_clocks
	395	nva3_domain[] = {
	396	{ nv_clk_src_crystal, 0xff },
7c856522 BS	397	{ nv_clk_src_core , 0x00, 0, "core", 1000 },
	398	{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
	399	{ nv_clk_src_mem , 0x02, 0, "memory", 1000 },
	400	{ nv_clk_src_vdec , 0x03 },
	401	{ nv_clk_src_disp , 0x04 },
70c7995d	402	{ nv_clk_src_host , 0x05 },
7c856522 BS	403	{ nv_clk_src_max }
7c856522 BS	404	};
d9c39056	405
8aceb7de BS	406	static int
	407	nva3_clock_ctor(struct nouveau_object parent, struct nouveau_object engine,
	408	struct nouveau_oclass oclass, void data, u32 size,
	409	struct nouveau_object **pobject)
	410	{
	411	struct nva3_clock_priv *priv;
	412	int ret;
	413
bb4d29df AC	414	ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0,
bb4d29df AC	415	false, &priv);
8aceb7de BS	416	*pobject = nv_object(priv);
	417	if (ret)
	418	return ret;
	419
7c856522 BS	420	priv->base.read = nva3_clock_read;
	421	priv->base.calc = nva3_clock_calc;
	422	priv->base.prog = nva3_clock_prog;
	423	priv->base.tidy = nva3_clock_tidy;
8aceb7de BS	424	return 0;
	425	}
	426
	427	struct nouveau_oclass
	428	nva3_clock_oclass = {
	429	.handle = NV_SUBDEV(CLOCK, 0xa3),
	430	.ofuncs = &(struct nouveau_ofuncs) {
	431	.ctor = nva3_clock_ctor,
	432	.dtor = _nouveau_clock_dtor,
	433	.init = _nouveau_clock_init,
	434	.fini = _nouveau_clock_fini,
	435	},
	436	};