[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / clock / nva3.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 *          Roy Spliet
 */

#include <subdev/bios.h>
#include <subdev/bios/pll.h>
#include <subdev/timer.h>

#include "pll.h"

#include "nva3.h"

struct nva3_clock_priv {
	struct nouveau_clock base;
	struct nva3_clock_info eng[nv_clk_src_max];
};

static u32 read_clk(struct nva3_clock_priv *, int, bool);
static u32 read_pll(struct nva3_clock_priv *, int, u32);

static u32
read_vco(struct nva3_clock_priv *priv, int clk)
{
	u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));

	switch (sctl & 0x00000030) {
	case 0x00000000:
		return nv_device(priv)->crystal;
	case 0x00000020:
		return read_pll(priv, 0x41, 0x00e820);
	case 0x00000030:
		return read_pll(priv, 0x42, 0x00e8a0);
	default:
		return 0;
	}
}

static u32
read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
{
	u32 sctl, sdiv, sclk;

	/* refclk for the 0xe8xx plls is a fixed frequency */
	if (clk >= 0x40) {
		if (nv_device(priv)->chipset == 0xaf) {
			/* no joke.. seriously.. sigh.. */
			return nv_rd32(priv, 0x00471c) * 1000;
		}

		return nv_device(priv)->crystal;
	}

	sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	if (!ignore_en && !(sctl & 0x00000100))
		return 0;

	/* out_alt */
	if (sctl & 0x00000400)
		return 108000;

	/* vco_out */
	switch (sctl & 0x00003000) {
	case 0x00000000:
		if (!(sctl & 0x00000200))
			return nv_device(priv)->crystal;
		return 0;
	case 0x00002000:
		if (sctl & 0x00000040)
			return 108000;
		return 100000;
	case 0x00003000:
		/* vco_enable */
		if (!(sctl & 0x00000001))
			return 0;

		sclk = read_vco(priv, clk);
		sdiv = ((sctl & 0x003f0000) >> 16) + 2;
		return (sclk * 2) / sdiv;
	default:
		return 0;
	}
}

static u32
read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
{
	u32 ctrl = nv_rd32(priv, pll + 0);
	u32 sclk = 0, P = 1, N = 1, M = 1;

	if (!(ctrl & 0x00000008)) {
		if (ctrl & 0x00000001) {
			u32 coef = nv_rd32(priv, pll + 4);
			M = (coef & 0x000000ff) >> 0;
			N = (coef & 0x0000ff00) >> 8;
			P = (coef & 0x003f0000) >> 16;

			/* no post-divider on these..
			 * XXX: it looks more like two post-"dividers" that
			 * cross each other out in the default RPLL config */
			if ((pll & 0x00ff00) == 0x00e800)
				P = 1;

			sclk = read_clk(priv, 0x00 + clk, false);
		}
	} else {
		sclk = read_clk(priv, 0x10 + clk, false);
	}

	if (M * P)
		return sclk * N / (M * P);
	return 0;
}

static int
nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
{
	struct nva3_clock_priv *priv = (void *)clk;
	u32 hsrc;

	switch (src) {
	case nv_clk_src_crystal:
		return nv_device(priv)->crystal;
	case nv_clk_src_core:
	case nv_clk_src_core_intm:
		return read_pll(priv, 0x00, 0x4200);
	case nv_clk_src_shader:
		return read_pll(priv, 0x01, 0x4220);
	case nv_clk_src_mem:
		return read_pll(priv, 0x02, 0x4000);
	case nv_clk_src_disp:
		return read_clk(priv, 0x20, false);
	case nv_clk_src_vdec:
		return read_clk(priv, 0x21, false);
	case nv_clk_src_daemon:
		return read_clk(priv, 0x25, false);
	case nv_clk_src_host:
		hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28;
		switch (hsrc) {
		case 0:
			return read_clk(priv, 0x1d, false);
		case 2:
		case 3:
			return 277000;
		default:
			nv_error(clk, "unknown HOST clock source %d\n", hsrc);
			return -EINVAL;
		}
	default:
		nv_error(clk, "invalid clock source %d\n", src);
		return -EINVAL;
	}

	return 0;
}

int
nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
		struct nva3_clock_info *info)
{
	struct nva3_clock_priv *priv = (void *)clock;
	u32 oclk, sclk, sdiv, diff;

	info->clk = 0;

	switch (khz) {
	case 27000:
		info->clk = 0x00000100;
		return khz;
	case 100000:
		info->clk = 0x00002100;
		return khz;
	case 108000:
		info->clk = 0x00002140;
		return khz;
	default:
		sclk = read_vco(priv, clk);
		sdiv = min((sclk * 2) / khz, (u32)65);
		oclk = (sclk * 2) / sdiv;
		diff = ((khz + 3000) - oclk);

		/* When imprecise, play it safe and aim for a clock lower than
		 * desired rather than higher */
		if (diff < 0) {
			sdiv++;
			oclk = (sclk * 2) / sdiv;
		}

		/* divider can go as low as 2, limited here because NVIDIA
		 * and the VBIOS on my NVA8 seem to prefer using the PLL
		 * for 810MHz - is there a good reason?
		 * XXX: PLLs with refclk 810MHz?  */
		if (sdiv > 4) {
			info->clk = (((sdiv - 2) << 16) | 0x00003100);
			return oclk;
		}

		break;
	}

	return -ERANGE;
}

int
nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
		struct nva3_clock_info *info)
{
	struct nouveau_bios *bios = nouveau_bios(clock);
	struct nva3_clock_priv *priv = (void *)clock;
	struct nvbios_pll limits;
	int P, N, M, diff;
	int ret;

	info->pll = 0;

	/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
	 * PLL and use the divider instead. */
	ret = nva3_clk_info(clock, clk, khz, info);
	diff = khz - ret;
	if (!pll || (diff >= -2000 && diff < 3000)) {
		goto out;
	}

	/* Try with PLL */
	ret = nvbios_pll_parse(bios, pll, &limits);
	if (ret)
		return ret;

	ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
	if (ret != limits.refclk)
		return -EINVAL;

	ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
	if (ret >= 0) {
		info->pll = (P << 16) | (N << 8) | M;
	}

out:
	info->fb_delay = max(((khz + 7566) / 15133), (u32) 18);

	return ret ? ret : -ERANGE;
}

static int
calc_clk(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate,
	 int clk, u32 pll, int idx)
{
	int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
				  &priv->eng[idx]);
	if (ret >= 0)
		return 0;
	return ret;
}

static int
calc_host(struct nva3_clock_priv *priv, struct nouveau_cstate *cstate)
{
	int ret = 0;
	u32 kHz = cstate->domain[nv_clk_src_host];
	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];

	if (kHz == 277000) {
		info->clk = 0;
		info->host_out = NVA3_HOST_277;
		return 0;
	}

	info->host_out = NVA3_HOST_CLK;

	ret = nva3_clk_info(&priv->base, 0x1d, kHz, info);
	if (ret >= 0)
		return 0;
	return ret;
}

static void
disable_clk_src(struct nva3_clock_priv *priv, u32 src)
{
	nv_mask(priv, src, 0x00000100, 0x00000000);
	nv_mask(priv, src, 0x00000001, 0x00000000);
}

static void
prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
{
	struct nva3_clock_info *info = &priv->eng[idx];
	const u32 src0 = 0x004120 + (clk * 4);
	const u32 src1 = 0x004160 + (clk * 4);
	const u32 ctrl = pll + 0;
	const u32 coef = pll + 4;
	u32 bypass;

	if (info->pll) {
		/* Always start from a non-PLL clock */
		bypass = nv_rd32(priv, ctrl)  & 0x00000008;
		if (!bypass) {
			nv_mask(priv, src1, 0x00000101, 0x00000101);
			nv_mask(priv, ctrl, 0x00000008, 0x00000008);
			udelay(20);
		}

		nv_mask(priv, src0, 0x003f3141, 0x00000101 | info->clk);
		nv_wr32(priv, coef, info->pll);
		nv_mask(priv, ctrl, 0x00000015, 0x00000015);
		nv_mask(priv, ctrl, 0x00000010, 0x00000000);
		if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) {
			nv_mask(priv, ctrl, 0x00000010, 0x00000010);
			nv_mask(priv, src0, 0x00000101, 0x00000000);
			return;
		}
		nv_mask(priv, ctrl, 0x00000010, 0x00000010);
		nv_mask(priv, ctrl, 0x00000008, 0x00000000);
		disable_clk_src(priv, src1);
	} else {
		nv_mask(priv, src1, 0x003f3141, 0x00000101 | info->clk);
		nv_mask(priv, ctrl, 0x00000018, 0x00000018);
		udelay(20);
		nv_mask(priv, ctrl, 0x00000001, 0x00000000);
		disable_clk_src(priv, src0);
	}
}

static void
prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
{
	struct nva3_clock_info *info = &priv->eng[idx];
	nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 | info->clk);
}

static void
prog_host(struct nva3_clock_priv *priv)
{
	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
	u32 hsrc = (nv_rd32(priv, 0xc040));

	switch (info->host_out) {
	case NVA3_HOST_277:
		if ((hsrc & 0x30000000) == 0) {
			nv_wr32(priv, 0xc040, hsrc | 0x20000000);
			disable_clk_src(priv, 0x4194);
		}
		break;
	case NVA3_HOST_CLK:
		prog_clk(priv, 0x1d, nv_clk_src_host);
		if ((hsrc & 0x30000000) >= 0x20000000) {
			nv_wr32(priv, 0xc040, hsrc & ~0x30000000);
		}
		break;
	default:
		break;
	}

	/* This seems to be a clock gating factor on idle, always set to 64 */
	nv_wr32(priv, 0xc044, 0x3e);
}

static void
prog_core(struct nva3_clock_priv *priv, int idx)
{
	struct nva3_clock_info *info = &priv->eng[idx];
	u32 fb_delay = nv_rd32(priv, 0x10002c);

	if (fb_delay < info->fb_delay)
		nv_wr32(priv, 0x10002c, info->fb_delay);

	prog_pll(priv, 0x00, 0x004200, idx);

	if (fb_delay > info->fb_delay)
		nv_wr32(priv, 0x10002c, info->fb_delay);
}

static int
nva3_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate)
{
	struct nva3_clock_priv *priv = (void *)clk;
	struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
	int ret;

	if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) ||
	    (ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) ||
	    (ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) ||
	    (ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) ||
	    (ret = calc_host(priv, cstate)))
		return ret;

	/* XXX: Should be reading the highest bit in the VBIOS clock to decide
	 * whether to use a PLL or not... but using a PLL defeats the purpose */
	if (core->pll) {
		ret = nva3_clk_info(clk, 0x10,
				cstate->domain[nv_clk_src_core_intm],
				&priv->eng[nv_clk_src_core_intm]);
		if (ret < 0)
			return ret;
	}

	return 0;
}

static int
nva3_clock_prog(struct nouveau_clock *clk)
{
	struct nva3_clock_priv *priv = (void *)clk;
	struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];

	if (core->pll)
		prog_core(priv, nv_clk_src_core_intm);

	prog_core(priv,  nv_clk_src_core);
	prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
	prog_clk(priv, 0x20, nv_clk_src_disp);
	prog_clk(priv, 0x21, nv_clk_src_vdec);
	prog_host(priv);
	return 0;
}

static void
nva3_clock_tidy(struct nouveau_clock *clk)
{
}

static struct nouveau_clocks
nva3_domain[] = {
	{ nv_clk_src_crystal  , 0xff },
	{ nv_clk_src_core     , 0x00, 0, "core", 1000 },
	{ nv_clk_src_shader   , 0x01, 0, "shader", 1000 },
	{ nv_clk_src_mem      , 0x02, 0, "memory", 1000 },
	{ nv_clk_src_vdec     , 0x03 },
	{ nv_clk_src_disp     , 0x04 },
	{ nv_clk_src_host     , 0x05 },
	{ nv_clk_src_core_intm, 0x06 },
	{ nv_clk_src_max }
};

static int
nva3_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		struct nouveau_oclass *oclass, void *data, u32 size,
		struct nouveau_object **pobject)
{
	struct nva3_clock_priv *priv;
	int ret;

	ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0,
				   false, &priv);
	*pobject = nv_object(priv);
	if (ret)
		return ret;

	priv->base.read = nva3_clock_read;
	priv->base.calc = nva3_clock_calc;
	priv->base.prog = nva3_clock_prog;
	priv->base.tidy = nva3_clock_tidy;
	return 0;
}

struct nouveau_oclass
nva3_clock_oclass = {
	.handle = NV_SUBDEV(CLOCK, 0xa3),
	.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = nva3_clock_ctor,
		.dtor = _nouveau_clock_dtor,
		.init = _nouveau_clock_init,
		.fini = _nouveau_clock_fini,
	},
};
Commit	Line	Data
8aceb7de BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
3d896d34	23	* Roy Spliet
8aceb7de BS	24	*/
8aceb7de BS	25
70790f4f BS	26	#include <subdev/bios.h>
70790f4f BS	27	#include <subdev/bios/pll.h>
7c856522	28	#include <subdev/timer.h>
70790f4f BS	29
70790f4f BS	30	#include "pll.h"
8aceb7de	31
7c856522 BS	32	#include "nva3.h"
7c856522 BS	33
8aceb7de BS	34	struct nva3_clock_priv {
8aceb7de BS	35	struct nouveau_clock base;
7c856522	36	struct nva3_clock_info eng[nv_clk_src_max];
8aceb7de BS	37	};
8aceb7de BS	38
7c856522 BS	39	static u32 read_clk(struct nva3_clock_priv *, int, bool);
	40	static u32 read_pll(struct nva3_clock_priv *, int, u32);
	41
	42	static u32
	43	read_vco(struct nva3_clock_priv *priv, int clk)
	44	{
	45	u32 sctl = nv_rd32(priv, 0x4120 + (clk * 4));
3d896d34 RS	46
	47	switch (sctl & 0x00000030) {
	48	case 0x00000000:
	49	return nv_device(priv)->crystal;
	50	case 0x00000020:
7c856522	51	return read_pll(priv, 0x41, 0x00e820);
3d896d34 RS	52	case 0x00000030:
	53	return read_pll(priv, 0x42, 0x00e8a0);
	54	default:
	55	return 0;
	56	}
7c856522 BS	57	}
	58
	59	static u32
	60	read_clk(struct nva3_clock_priv *priv, int clk, bool ignore_en)
	61	{
	62	u32 sctl, sdiv, sclk;
	63
	64	/* refclk for the 0xe8xx plls is a fixed frequency */
	65	if (clk >= 0x40) {
	66	if (nv_device(priv)->chipset == 0xaf) {
	67	/* no joke.. seriously.. sigh.. */
	68	return nv_rd32(priv, 0x00471c) * 1000;
	69	}
	70
	71	return nv_device(priv)->crystal;
	72	}
	73
	74	sctl = nv_rd32(priv, 0x4120 + (clk * 4));
	75	if (!ignore_en && !(sctl & 0x00000100))
	76	return 0;
	77
3d896d34 RS	78	/* out_alt */
	79	if (sctl & 0x00000400)
	80	return 108000;
	81
	82	/* vco_out */
7c856522 BS	83	switch (sctl & 0x00003000) {
7c856522 BS	84	case 0x00000000:
3d896d34 RS	85	if (!(sctl & 0x00000200))
	86	return nv_device(priv)->crystal;
	87	return 0;
7c856522 BS	88	case 0x00002000:
	89	if (sctl & 0x00000040)
	90	return 108000;
	91	return 100000;
	92	case 0x00003000:
3d896d34 RS	93	/* vco_enable */
	94	if (!(sctl & 0x00000001))
	95	return 0;
	96
7c856522 BS	97	sclk = read_vco(priv, clk);
	98	sdiv = ((sctl & 0x003f0000) >> 16) + 2;
	99	return (sclk * 2) / sdiv;
	100	default:
	101	return 0;
	102	}
	103	}
	104
	105	static u32
	106	read_pll(struct nva3_clock_priv *priv, int clk, u32 pll)
	107	{
	108	u32 ctrl = nv_rd32(priv, pll + 0);
	109	u32 sclk = 0, P = 1, N = 1, M = 1;
	110
	111	if (!(ctrl & 0x00000008)) {
	112	if (ctrl & 0x00000001) {
	113	u32 coef = nv_rd32(priv, pll + 4);
	114	M = (coef & 0x000000ff) >> 0;
	115	N = (coef & 0x0000ff00) >> 8;
	116	P = (coef & 0x003f0000) >> 16;
	117
3d896d34 RS	118	/* no post-divider on these..
	119	* XXX: it looks more like two post-"dividers" that
	120	* cross each other out in the default RPLL config */
7c856522 BS	121	if ((pll & 0x00ff00) == 0x00e800)
	122	P = 1;
	123
	124	sclk = read_clk(priv, 0x00 + clk, false);
	125	}
	126	} else {
	127	sclk = read_clk(priv, 0x10 + clk, false);
	128	}
	129
	130	if (M * P)
	131	return sclk * N / (M * P);
	132	return 0;
	133	}
	134
	135	static int
	136	nva3_clock_read(struct nouveau_clock *clk, enum nv_clk_src src)
	137	{
	138	struct nva3_clock_priv priv = (void )clk;
70c7995d	139	u32 hsrc;
7c856522 BS	140
	141	switch (src) {
	142	case nv_clk_src_crystal:
	143	return nv_device(priv)->crystal;
7c856522	144	case nv_clk_src_core:
3d40a717	145	case nv_clk_src_core_intm:
7c856522 BS	146	return read_pll(priv, 0x00, 0x4200);
	147	case nv_clk_src_shader:
	148	return read_pll(priv, 0x01, 0x4220);
	149	case nv_clk_src_mem:
	150	return read_pll(priv, 0x02, 0x4000);
	151	case nv_clk_src_disp:
	152	return read_clk(priv, 0x20, false);
	153	case nv_clk_src_vdec:
	154	return read_clk(priv, 0x21, false);
	155	case nv_clk_src_daemon:
	156	return read_clk(priv, 0x25, false);
70c7995d RS	157	case nv_clk_src_host:
	158	hsrc = (nv_rd32(priv, 0xc040) & 0x30000000) >> 28;
	159	switch (hsrc) {
	160	case 0:
	161	return read_clk(priv, 0x1d, false);
	162	case 2:
	163	case 3:
	164	return 277000;
	165	default:
	166	nv_error(clk, "unknown HOST clock source %d\n", hsrc);
	167	return -EINVAL;
	168	}
7c856522 BS	169	default:
	170	nv_error(clk, "invalid clock source %d\n", src);
	171	return -EINVAL;
	172	}
3d896d34 RS	173
3d896d34 RS	174	return 0;
7c856522 BS	175	}
7c856522 BS	176
d9c39056	177	int
6a4a47cf	178	nva3_clk_info(struct nouveau_clock *clock, int clk, u32 khz,
7c856522	179	struct nva3_clock_info *info)
d9c39056	180	{
7c856522	181	struct nva3_clock_priv priv = (void )clock;
6a4a47cf	182	u32 oclk, sclk, sdiv, diff;
7c856522	183
7c856522 BS	184	info->clk = 0;
	185
	186	switch (khz) {
	187	case 27000:
	188	info->clk = 0x00000100;
	189	return khz;
	190	case 100000:
	191	info->clk = 0x00002100;
	192	return khz;
	193	case 108000:
	194	info->clk = 0x00002140;
	195	return khz;
	196	default:
	197	sclk = read_vco(priv, clk);
6a4a47cf RS	198	sdiv = min((sclk * 2) / khz, (u32)65);
	199	oclk = (sclk * 2) / sdiv;
	200	diff = ((khz + 3000) - oclk);
	201
	202	/* When imprecise, play it safe and aim for a clock lower than
	203	* desired rather than higher */
	204	if (diff < 0) {
	205	sdiv++;
	206	oclk = (sclk * 2) / sdiv;
	207	}
	208
	209	/* divider can go as low as 2, limited here because NVIDIA
7c856522 BS	210	* and the VBIOS on my NVA8 seem to prefer using the PLL
7c856522 BS	211	* for 810MHz - is there a good reason?
6a4a47cf	212	* XXX: PLLs with refclk 810MHz? */
7c856522	213	if (sdiv > 4) {
6a4a47cf RS	214	info->clk = (((sdiv - 2) << 16) \| 0x00003100);
6a4a47cf RS	215	return oclk;
7c856522 BS	216	}
7c856522 BS	217
7c856522 BS	218	break;
7c856522 BS	219	}
d9c39056	220
6a4a47cf RS	221	return -ERANGE;
	222	}
	223
	224	int
	225	nva3_pll_info(struct nouveau_clock *clock, int clk, u32 pll, u32 khz,
	226	struct nva3_clock_info *info)
	227	{
	228	struct nouveau_bios *bios = nouveau_bios(clock);
	229	struct nva3_clock_priv priv = (void )clock;
6a4a47cf RS	230	struct nvbios_pll limits;
	231	int P, N, M, diff;
	232	int ret;
	233
	234	info->pll = 0;
	235
	236	/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
	237	* PLL and use the divider instead. */
3d40a717 RS	238	ret = nva3_clk_info(clock, clk, khz, info);
3d40a717 RS	239	diff = khz - ret;
6a4a47cf	240	if (!pll \|\| (diff >= -2000 && diff < 3000)) {
3d40a717	241	goto out;
6a4a47cf RS	242	}
	243
	244	/* Try with PLL */
7c856522 BS	245	ret = nvbios_pll_parse(bios, pll, &limits);
	246	if (ret)
	247	return ret;
	248
3d40a717 RS	249	ret = nva3_clk_info(clock, clk - 0x10, limits.refclk, info);
3d40a717 RS	250	if (ret != limits.refclk)
7c856522	251	return -EINVAL;
d9c39056	252
7c856522 BS	253	ret = nva3_pll_calc(nv_subdev(priv), &limits, khz, &N, NULL, &M, &P);
7c856522 BS	254	if (ret >= 0) {
7c856522	255	info->pll = (P << 16) \| (N << 8) \| M;
d9c39056	256	}
7c856522	257
3d40a717 RS	258	out:
	259	info->fb_delay = max(((khz + 7566) / 15133), (u32) 18);
	260
7c856522 BS	261	return ret ? ret : -ERANGE;
	262	}
	263
	264	static int
	265	calc_clk(struct nva3_clock_priv priv, struct nouveau_cstate cstate,
	266	int clk, u32 pll, int idx)
	267	{
6a4a47cf	268	int ret = nva3_pll_info(&priv->base, clk, pll, cstate->domain[idx],
7c856522 BS	269	&priv->eng[idx]);
	270	if (ret >= 0)
	271	return 0;
d9c39056 ML	272	return ret;
	273	}
	274
70c7995d RS	275	static int
	276	calc_host(struct nva3_clock_priv priv, struct nouveau_cstate cstate)
	277	{
	278	int ret = 0;
	279	u32 kHz = cstate->domain[nv_clk_src_host];
	280	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
	281
	282	if (kHz == 277000) {
	283	info->clk = 0;
	284	info->host_out = NVA3_HOST_277;
	285	return 0;
	286	}
	287
	288	info->host_out = NVA3_HOST_CLK;
	289
	290	ret = nva3_clk_info(&priv->base, 0x1d, kHz, info);
	291	if (ret >= 0)
	292	return 0;
	293	return ret;
	294	}
	295
	296	static void
	297	disable_clk_src(struct nva3_clock_priv *priv, u32 src)
	298	{
	299	nv_mask(priv, src, 0x00000100, 0x00000000);
	300	nv_mask(priv, src, 0x00000001, 0x00000000);
	301	}
	302
7c856522 BS	303	static void
	304	prog_pll(struct nva3_clock_priv *priv, int clk, u32 pll, int idx)
	305	{
	306	struct nva3_clock_info *info = &priv->eng[idx];
	307	const u32 src0 = 0x004120 + (clk * 4);
	308	const u32 src1 = 0x004160 + (clk * 4);
	309	const u32 ctrl = pll + 0;
	310	const u32 coef = pll + 4;
a749a1fb	311	u32 bypass;
7c856522 BS	312
7c856522 BS	313	if (info->pll) {
a749a1fb RS	314	/* Always start from a non-PLL clock */
	315	bypass = nv_rd32(priv, ctrl) & 0x00000008;
	316	if (!bypass) {
	317	nv_mask(priv, src1, 0x00000101, 0x00000101);
	318	nv_mask(priv, ctrl, 0x00000008, 0x00000008);
	319	udelay(20);
	320	}
	321
6a4a47cf	322	nv_mask(priv, src0, 0x003f3141, 0x00000101 \| info->clk);
7c856522 BS	323	nv_wr32(priv, coef, info->pll);
	324	nv_mask(priv, ctrl, 0x00000015, 0x00000015);
	325	nv_mask(priv, ctrl, 0x00000010, 0x00000000);
275dd6f4 RS	326	if (!nv_wait(priv, ctrl, 0x00020000, 0x00020000)) {
	327	nv_mask(priv, ctrl, 0x00000010, 0x00000010);
	328	nv_mask(priv, src0, 0x00000101, 0x00000000);
	329	return;
	330	}
7c856522 BS	331	nv_mask(priv, ctrl, 0x00000010, 0x00000010);
7c856522 BS	332	nv_mask(priv, ctrl, 0x00000008, 0x00000000);
70c7995d	333	disable_clk_src(priv, src1);
7c856522 BS	334	} else {
	335	nv_mask(priv, src1, 0x003f3141, 0x00000101 \| info->clk);
	336	nv_mask(priv, ctrl, 0x00000018, 0x00000018);
	337	udelay(20);
	338	nv_mask(priv, ctrl, 0x00000001, 0x00000000);
70c7995d	339	disable_clk_src(priv, src0);
7c856522 BS	340	}
	341	}
	342
	343	static void
	344	prog_clk(struct nva3_clock_priv *priv, int clk, int idx)
	345	{
	346	struct nva3_clock_info *info = &priv->eng[idx];
	347	nv_mask(priv, 0x004120 + (clk * 4), 0x003f3141, 0x00000101 \| info->clk);
	348	}
	349
70c7995d RS	350	static void
	351	prog_host(struct nva3_clock_priv *priv)
	352	{
	353	struct nva3_clock_info *info = &priv->eng[nv_clk_src_host];
	354	u32 hsrc = (nv_rd32(priv, 0xc040));
	355
	356	switch (info->host_out) {
	357	case NVA3_HOST_277:
	358	if ((hsrc & 0x30000000) == 0) {
	359	nv_wr32(priv, 0xc040, hsrc \| 0x20000000);
	360	disable_clk_src(priv, 0x4194);
	361	}
	362	break;
	363	case NVA3_HOST_CLK:
	364	prog_clk(priv, 0x1d, nv_clk_src_host);
	365	if ((hsrc & 0x30000000) >= 0x20000000) {
	366	nv_wr32(priv, 0xc040, hsrc & ~0x30000000);
	367	}
	368	break;
	369	default:
	370	break;
	371	}
	372
	373	/* This seems to be a clock gating factor on idle, always set to 64 */
	374	nv_wr32(priv, 0xc044, 0x3e);
	375	}
	376
3d40a717 RS	377	static void
	378	prog_core(struct nva3_clock_priv *priv, int idx)
	379	{
	380	struct nva3_clock_info *info = &priv->eng[idx];
	381	u32 fb_delay = nv_rd32(priv, 0x10002c);
	382
	383	if (fb_delay < info->fb_delay)
	384	nv_wr32(priv, 0x10002c, info->fb_delay);
	385
	386	prog_pll(priv, 0x00, 0x004200, idx);
	387
	388	if (fb_delay > info->fb_delay)
	389	nv_wr32(priv, 0x10002c, info->fb_delay);
	390	}
	391
7c856522 BS	392	static int
	393	nva3_clock_calc(struct nouveau_clock clk, struct nouveau_cstate cstate)
	394	{
	395	struct nva3_clock_priv priv = (void )clk;
3d40a717	396	struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
7c856522 BS	397	int ret;
	398
	399	if ((ret = calc_clk(priv, cstate, 0x10, 0x4200, nv_clk_src_core)) \|\|
	400	(ret = calc_clk(priv, cstate, 0x11, 0x4220, nv_clk_src_shader)) \|\|
	401	(ret = calc_clk(priv, cstate, 0x20, 0x0000, nv_clk_src_disp)) \|\|
70c7995d RS	402	(ret = calc_clk(priv, cstate, 0x21, 0x0000, nv_clk_src_vdec)) \|\|
70c7995d RS	403	(ret = calc_host(priv, cstate)))
7c856522 BS	404	return ret;
7c856522 BS	405
3d40a717 RS	406	/* XXX: Should be reading the highest bit in the VBIOS clock to decide
	407	* whether to use a PLL or not... but using a PLL defeats the purpose */
	408	if (core->pll) {
	409	ret = nva3_clk_info(clk, 0x10,
	410	cstate->domain[nv_clk_src_core_intm],
	411	&priv->eng[nv_clk_src_core_intm]);
	412	if (ret < 0)
	413	return ret;
	414	}
	415
7c856522 BS	416	return 0;
	417	}
	418
	419	static int
	420	nva3_clock_prog(struct nouveau_clock *clk)
	421	{
	422	struct nva3_clock_priv priv = (void )clk;
3d40a717 RS	423	struct nva3_clock_info *core = &priv->eng[nv_clk_src_core];
	424
	425	if (core->pll)
	426	prog_core(priv, nv_clk_src_core_intm);
	427
	428	prog_core(priv, nv_clk_src_core);
7c856522 BS	429	prog_pll(priv, 0x01, 0x004220, nv_clk_src_shader);
	430	prog_clk(priv, 0x20, nv_clk_src_disp);
	431	prog_clk(priv, 0x21, nv_clk_src_vdec);
70c7995d	432	prog_host(priv);
7c856522 BS	433	return 0;
	434	}
	435
	436	static void
	437	nva3_clock_tidy(struct nouveau_clock *clk)
	438	{
	439	}
	440
	441	static struct nouveau_clocks
	442	nva3_domain[] = {
3d40a717 RS	443	{ nv_clk_src_crystal , 0xff },
	444	{ nv_clk_src_core , 0x00, 0, "core", 1000 },
	445	{ nv_clk_src_shader , 0x01, 0, "shader", 1000 },
	446	{ nv_clk_src_mem , 0x02, 0, "memory", 1000 },
	447	{ nv_clk_src_vdec , 0x03 },
	448	{ nv_clk_src_disp , 0x04 },
	449	{ nv_clk_src_host , 0x05 },
	450	{ nv_clk_src_core_intm, 0x06 },
7c856522 BS	451	{ nv_clk_src_max }
7c856522 BS	452	};
d9c39056	453
8aceb7de BS	454	static int
	455	nva3_clock_ctor(struct nouveau_object parent, struct nouveau_object engine,
	456	struct nouveau_oclass oclass, void data, u32 size,
	457	struct nouveau_object **pobject)
	458	{
	459	struct nva3_clock_priv *priv;
	460	int ret;
	461
bb4d29df AC	462	ret = nouveau_clock_create(parent, engine, oclass, nva3_domain, NULL, 0,
bb4d29df AC	463	false, &priv);
8aceb7de BS	464	*pobject = nv_object(priv);
	465	if (ret)
	466	return ret;
	467
7c856522 BS	468	priv->base.read = nva3_clock_read;
	469	priv->base.calc = nva3_clock_calc;
	470	priv->base.prog = nva3_clock_prog;
	471	priv->base.tidy = nva3_clock_tidy;
8aceb7de BS	472	return 0;
	473	}
	474
	475	struct nouveau_oclass
	476	nva3_clock_oclass = {
	477	.handle = NV_SUBDEV(CLOCK, 0xa3),
	478	.ofuncs = &(struct nouveau_ofuncs) {
	479	.ctor = nva3_clock_ctor,
	480	.dtor = _nouveau_clock_dtor,
	481	.init = _nouveau_clock_init,
	482	.fini = _nouveau_clock_fini,
	483	},
	484	};