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drm/nouveau: port all engines to new engine module format
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / device / nv50.c
CommitLineData
9274f4a9
BS		 1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/device.h>
70c0f263 26#include <subdev/bios.h>
e0996aea 27#include <subdev/gpio.h>
4196faa8 28#include <subdev/i2c.h>
8aceb7de 29#include <subdev/clock.h>
cb75d97e 30#include <subdev/devinit.h>
7d9115de 31#include <subdev/mc.h>
5a5c7432 32#include <subdev/timer.h>
861d2107 33#include <subdev/fb.h>
3863c9bc
BS		 34#include <subdev/instmem.h>
35#include <subdev/vm.h>
36#include <subdev/bar.h>
9274f4a9 37
ebb945a9
BS		 38#include <engine/dmaobj.h>
39#include <engine/fifo.h>
40#include <engine/software.h>
41#include <engine/graph.h>
42#include <engine/mpeg.h>
43#include <engine/vp.h>
44#include <engine/crypt.h>
45#include <engine/bsp.h>
46#include <engine/ppp.h>
47#include <engine/copy.h>
48#include <engine/disp.h>
49
9274f4a9
BS		 50int
51nv50_identify(struct nouveau_device *device)
52{
53 switch (device->chipset) {
54 case 0x50:
70c0f263 55 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 56 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 57 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 58 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 59 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 60 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
5a5c7432 61 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 62 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 63 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
64 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
65 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 66 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
67 device->oclass[NVDEV_ENGINE_FIFO ] = &nv50_fifo_oclass;
68 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
69 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
70 device->oclass[NVDEV_ENGINE_MPEG ] = &nv50_mpeg_oclass;
71 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 72 break;
73 case 0x84:
70c0f263 74 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 75 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 76 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 77 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 78 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 79 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
5a5c7432 80 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 81 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 82 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
83 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
84 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 85 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
86 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
87 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
88 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
89 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
90 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
91 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
92 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
93 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 94 break;
95 case 0x86:
70c0f263 96 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 97 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 98 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 99 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 100 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 101 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
5a5c7432 102 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 103 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 104 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
105 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
106 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 107 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
108 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
109 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
110 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
111 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
112 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
113 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
114 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
115 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 116 break;
117 case 0x92:
70c0f263 118 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 119 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 120 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 121 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 122 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 123 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
5a5c7432 124 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 125 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 126 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
127 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
128 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 129 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
130 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
131 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
132 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
133 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
134 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
135 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
136 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
137 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 138 break;
139 case 0x94:
70c0f263 140 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 141 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 142 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 143 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 144 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 145 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
5a5c7432 146 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 147 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 148 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
149 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
150 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 151 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
152 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
153 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
154 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
155 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
156 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
157 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
158 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
159 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 160 break;
161 case 0x96:
70c0f263 162 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 163 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 164 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 165 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 166 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 167 device->oclass[NVDEV_SUBDEV_MC ] = &nv50_mc_oclass;
5a5c7432 168 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 169 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 170 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
171 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
172 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 173 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
174 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
175 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
176 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
177 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
178 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
179 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
180 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
181 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 182 break;
183 case 0x98:
70c0f263 184 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 185 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 186 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 187 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 188 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 189 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
5a5c7432 190 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 191 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 192 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
193 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
194 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 195 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
196 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
197 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
198 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
199 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
200 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
201 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
202 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
203 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 204 break;
205 case 0xa0:
70c0f263 206 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 207 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 208 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 209 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 210 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 211 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
5a5c7432 212 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 213 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 214 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
215 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
216 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 217 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
218 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
219 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
220 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
221 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
222 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
223 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv84_crypt_oclass;
224 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
225 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 226 break;
227 case 0xaa:
70c0f263 228 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 229 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 230 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 231 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 232 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 233 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
5a5c7432 234 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 235 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 236 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
237 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
238 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 239 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
240 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
241 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
242 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
243 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
244 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
245 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
246 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
247 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 248 break;
249 case 0xac:
70c0f263 250 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 251 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 252 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 253 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv50_clock_oclass;
cb75d97e 254 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 255 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
5a5c7432 256 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 257 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 258 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
259 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
260 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 261 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
262 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
263 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
264 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
265 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
266 device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
267 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
268 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
269 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 270 break;
271 case 0xa3:
70c0f263 272 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 273 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 274 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 275 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
cb75d97e 276 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 277 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
5a5c7432 278 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 279 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 280 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
281 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
282 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 283 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
284 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
285 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
286 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
287 device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
288 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
289 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
290 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
291 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
292 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 293 break;
294 case 0xa5:
70c0f263 295 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 296 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 297 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 298 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
cb75d97e 299 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 300 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
5a5c7432 301 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 302 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 303 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
304 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
305 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 306 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
307 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
308 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
309 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
310 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
311 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
312 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
313 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
314 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 315 break;
316 case 0xa8:
70c0f263 317 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 318 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 319 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 320 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
cb75d97e 321 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 322 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
5a5c7432 323 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 324 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 325 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
326 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
327 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 328 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
329 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
330 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
331 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
332 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
333 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
334 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
335 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
336 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 337 break;
338 case 0xaf:
70c0f263 339 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea 340 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8 341 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de 342 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nva3_clock_oclass;
cb75d97e 343 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de 344 device->oclass[NVDEV_SUBDEV_MC ] = &nv98_mc_oclass;
5a5c7432 345 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 346 device->oclass[NVDEV_SUBDEV_FB ] = &nv50_fb_oclass;
3863c9bc
BS		 347 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
348 device->oclass[NVDEV_SUBDEV_VM ] = &nv50_vmmgr_oclass;
349 device->oclass[NVDEV_SUBDEV_BAR ] = &nv50_bar_oclass;
ebb945a9
BS		 350 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv50_dmaeng_oclass;
351 device->oclass[NVDEV_ENGINE_FIFO ] = &nv84_fifo_oclass;
352 device->oclass[NVDEV_ENGINE_SW ] = &nv50_software_oclass;
353 device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
354 device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
355 device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
356 device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
357 device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
358 device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9
BS		 359 break;
360 default:
361 nv_fatal(device, "unknown Tesla chipset\n");
362 return -EINVAL;
363 }
364
365 return 0;
366}
Linux kernel - Deliverables
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