[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / device / nvc0.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <subdev/device.h>
#include <subdev/bios.h>
#include <subdev/gpio.h>
#include <subdev/i2c.h>
#include <subdev/clock.h>
#include <subdev/devinit.h>
#include <subdev/mc.h>
#include <subdev/timer.h>
#include <subdev/fb.h>
#include <subdev/ltcg.h>
#include <subdev/instmem.h>
#include <subdev/vm.h>
#include <subdev/bar.h>

#include <engine/dmaobj.h>
#include <engine/fifo.h>
#include <engine/software.h>
#include <engine/graph.h>
#include <engine/vp.h>
#include <engine/bsp.h>
#include <engine/ppp.h>
#include <engine/copy.h>
#include <engine/disp.h>

int
nvc0_identify(struct nouveau_device *device)
{
	switch (device->chipset) {
	case 0xc0:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xc4:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xc3:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xce:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xcf:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xc1:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xc8:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nv50_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_COPY1  ] = &nvc0_copy1_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nv50_disp_oclass;
		break;
	case 0xd9:
		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nouveau_bios_oclass;
		device->oclass[NVDEV_SUBDEV_GPIO   ] = &nvd0_gpio_oclass;
		device->oclass[NVDEV_SUBDEV_I2C    ] = &nouveau_i2c_oclass;
		device->oclass[NVDEV_SUBDEV_CLOCK  ] = &nvc0_clock_oclass;
		device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
		device->oclass[NVDEV_SUBDEV_MC     ] = &nvc0_mc_oclass;
		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;
		device->oclass[NVDEV_SUBDEV_FB     ] = &nvc0_fb_oclass;
		device->oclass[NVDEV_SUBDEV_LTCG   ] = &nvc0_ltcg_oclass;
		device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
		device->oclass[NVDEV_SUBDEV_VM     ] = &nvc0_vmmgr_oclass;
		device->oclass[NVDEV_SUBDEV_BAR    ] = &nvc0_bar_oclass;
		device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
		device->oclass[NVDEV_ENGINE_FIFO   ] = &nvc0_fifo_oclass;
		device->oclass[NVDEV_ENGINE_SW     ] = &nvc0_software_oclass;
		device->oclass[NVDEV_ENGINE_GR     ] = &nvc0_graph_oclass;
		device->oclass[NVDEV_ENGINE_VP     ] = &nv84_vp_oclass;
		device->oclass[NVDEV_ENGINE_BSP    ] = &nv84_bsp_oclass;
		device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
		device->oclass[NVDEV_ENGINE_COPY0  ] = &nvc0_copy0_oclass;
		device->oclass[NVDEV_ENGINE_DISP   ] = &nvd0_disp_oclass;
		break;
	default:
		nv_fatal(device, "unknown Fermi chipset\n");
		return -EINVAL;
	}

	return 0;
}
Commit	Line	Data
9274f4a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include <subdev/device.h>
70c0f263	26	#include <subdev/bios.h>
e0996aea	27	#include <subdev/gpio.h>
4196faa8	28	#include <subdev/i2c.h>
8aceb7de	29	#include <subdev/clock.h>
cb75d97e	30	#include <subdev/devinit.h>
7d9115de	31	#include <subdev/mc.h>
5a5c7432	32	#include <subdev/timer.h>
861d2107 BS	33	#include <subdev/fb.h>
861d2107 BS	34	#include <subdev/ltcg.h>
3863c9bc BS	35	#include <subdev/instmem.h>
	36	#include <subdev/vm.h>
	37	#include <subdev/bar.h>
9274f4a9	38
ebb945a9 BS	39	#include <engine/dmaobj.h>
	40	#include <engine/fifo.h>
	41	#include <engine/software.h>
	42	#include <engine/graph.h>
	43	#include <engine/vp.h>
	44	#include <engine/bsp.h>
	45	#include <engine/ppp.h>
	46	#include <engine/copy.h>
	47	#include <engine/disp.h>
	48
9274f4a9 BS	49	int
	50	nvc0_identify(struct nouveau_device *device)
	51	{
	52	switch (device->chipset) {
	53	case 0xc0:
70c0f263	54	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	55	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	56	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	57	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
cb75d97e	58	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	59	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	60	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	61	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	62	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	63	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	64	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	65	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	66	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	67	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	68	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	69	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	70	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	71	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	72	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	73	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	74	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	75	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	76	break;
9274f4a9 BS	77	case 0xc4:
70c0f263	78	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	79	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	80	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	81	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
cb75d97e	82	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	83	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	84	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	85	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	86	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	87	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	88	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	89	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	90	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	91	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	92	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	93	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	94	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	95	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	96	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	97	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	98	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	99	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	100	break;
9274f4a9 BS	101	case 0xc3:
70c0f263	102	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	103	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	104	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	105	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
cb75d97e	106	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	107	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	108	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	109	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	110	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	111	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	112	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	113	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	114	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	115	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	116	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	117	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	118	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	119	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	120	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	121	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	122	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	123	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	124	break;
9274f4a9 BS	125	case 0xce:
70c0f263	126	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	127	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	128	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	129	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
cb75d97e	130	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	131	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	132	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	133	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	134	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	135	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	136	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	137	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	138	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	139	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	140	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	141	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	142	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	143	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	144	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	145	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	146	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	147	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	148	break;
9274f4a9 BS	149	case 0xcf:
70c0f263	150	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	151	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	152	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	153	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
cb75d97e	154	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	155	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	156	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	157	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	158	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	159	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	160	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	161	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	162	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	163	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	164	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	165	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	166	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	167	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	168	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	169	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	170	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	171	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	172	break;
9274f4a9 BS	173	case 0xc1:
70c0f263	174	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	175	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	176	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	177	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
cb75d97e	178	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	179	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	180	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	181	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	182	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	183	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	184	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	185	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	186	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	187	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	188	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	189	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	190	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	191	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	192	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	193	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	194	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	195	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	196	break;
9274f4a9 BS	197	case 0xc8:
70c0f263	198	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	199	device->oclass[NVDEV_SUBDEV_GPIO ] = &nv50_gpio_oclass;
4196faa8	200	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	201	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
cb75d97e	202	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	203	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	204	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	205	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	206	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	207	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	208	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	209	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	210	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	211	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	212	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	213	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	214	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	215	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	216	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	217	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	218	device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
	219	device->oclass[NVDEV_ENGINE_DISP ] = &nv50_disp_oclass;
9274f4a9 BS	220	break;
9274f4a9 BS	221	case 0xd9:
70c0f263	222	device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
e0996aea	223	device->oclass[NVDEV_SUBDEV_GPIO ] = &nvd0_gpio_oclass;
4196faa8	224	device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
8aceb7de	225	device->oclass[NVDEV_SUBDEV_CLOCK ] = &nvc0_clock_oclass;
cb75d97e	226	device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv50_devinit_oclass;
7d9115de	227	device->oclass[NVDEV_SUBDEV_MC ] = &nvc0_mc_oclass;
5a5c7432	228	device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
861d2107 BS	229	device->oclass[NVDEV_SUBDEV_FB ] = &nvc0_fb_oclass;
861d2107 BS	230	device->oclass[NVDEV_SUBDEV_LTCG ] = &nvc0_ltcg_oclass;
3863c9bc BS	231	device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv50_instmem_oclass;
	232	device->oclass[NVDEV_SUBDEV_VM ] = &nvc0_vmmgr_oclass;
	233	device->oclass[NVDEV_SUBDEV_BAR ] = &nvc0_bar_oclass;
ebb945a9 BS	234	device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nvc0_dmaeng_oclass;
	235	device->oclass[NVDEV_ENGINE_FIFO ] = &nvc0_fifo_oclass;
	236	device->oclass[NVDEV_ENGINE_SW ] = &nvc0_software_oclass;
	237	device->oclass[NVDEV_ENGINE_GR ] = &nvc0_graph_oclass;
	238	device->oclass[NVDEV_ENGINE_VP ] = &nv84_vp_oclass;
	239	device->oclass[NVDEV_ENGINE_BSP ] = &nv84_bsp_oclass;
	240	device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
	241	device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
	242	device->oclass[NVDEV_ENGINE_DISP ] = &nvd0_disp_oclass;
9274f4a9 BS	243	break;
	244	default:
	245	nv_fatal(device, "unknown Fermi chipset\n");
	246	return -EINVAL;
	247	}
	248
	249	return 0;
	250	}