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1 | /* |
2 | * Copyright (C) 2009 Francisco Jerez. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
02a841d4 | 27 | #include <subdev/gpio.h> |
6ee73861 | 28 | |
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29 | struct nv10_gpio_priv { |
30 | struct nouveau_gpio base; | |
31 | }; | |
32 | ||
33 | static int | |
34 | nv10_gpio_sense(struct nouveau_gpio *gpio, int line) | |
6ee73861 | 35 | { |
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36 | if (line < 2) { |
37 | line = line * 16; | |
e0996aea | 38 | line = nv_rd32(gpio, 0x600818) >> line; |
a0b25635 BS |
39 | return !!(line & 0x0100); |
40 | } else | |
41 | if (line < 10) { | |
42 | line = (line - 2) * 4; | |
e0996aea | 43 | line = nv_rd32(gpio, 0x60081c) >> line; |
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44 | return !!(line & 0x04); |
45 | } else | |
46 | if (line < 14) { | |
47 | line = (line - 10) * 4; | |
e0996aea | 48 | line = nv_rd32(gpio, 0x600850) >> line; |
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49 | return !!(line & 0x04); |
50 | } | |
6ee73861 | 51 | |
a0b25635 | 52 | return -EINVAL; |
6ee73861 BS |
53 | } |
54 | ||
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55 | static int |
56 | nv10_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out) | |
6ee73861 | 57 | { |
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58 | u32 reg, mask, data; |
59 | ||
60 | if (line < 2) { | |
61 | line = line * 16; | |
e0996aea | 62 | reg = 0x600818; |
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63 | mask = 0x00000011; |
64 | data = (dir << 4) | out; | |
65 | } else | |
66 | if (line < 10) { | |
67 | line = (line - 2) * 4; | |
e0996aea | 68 | reg = 0x60081c; |
b99da31e | 69 | mask = 0x00000003; |
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70 | data = (dir << 1) | out; |
71 | } else | |
72 | if (line < 14) { | |
73 | line = (line - 10) * 4; | |
e0996aea | 74 | reg = 0x600850; |
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75 | mask = 0x00000003; |
76 | data = (dir << 1) | out; | |
77 | } else { | |
78 | return -EINVAL; | |
79 | } | |
6ee73861 | 80 | |
e0996aea | 81 | nv_mask(gpio, reg, mask << line, data << line); |
6ee73861 BS |
82 | return 0; |
83 | } | |
47e5d5cb | 84 | |
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85 | static void |
86 | nv10_gpio_irq_enable(struct nouveau_gpio *gpio, int line, bool on) | |
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87 | { |
88 | u32 mask = 0x00010001 << line; | |
89 | ||
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90 | nv_wr32(gpio, 0x001104, mask); |
91 | nv_mask(gpio, 0x001144, mask, on ? mask : 0); | |
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92 | } |
93 | ||
94 | static void | |
e0996aea | 95 | nv10_gpio_intr(struct nouveau_subdev *subdev) |
47e5d5cb | 96 | { |
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97 | struct nv10_gpio_priv *priv = (void *)subdev; |
98 | u32 intr = nv_rd32(priv, 0x001104); | |
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99 | u32 hi = (intr & 0x0000ffff) >> 0; |
100 | u32 lo = (intr & 0xffff0000) >> 16; | |
101 | ||
e0996aea | 102 | priv->base.isr_run(&priv->base, 0, hi | lo); |
47e5d5cb | 103 | |
e0996aea | 104 | nv_wr32(priv, 0x001104, intr); |
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105 | } |
106 | ||
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107 | static int |
108 | nv10_gpio_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |
109 | struct nouveau_oclass *oclass, void *data, u32 size, | |
110 | struct nouveau_object **pobject) | |
47e5d5cb | 111 | { |
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112 | struct nv10_gpio_priv *priv; |
113 | int ret; | |
114 | ||
115 | ret = nouveau_gpio_create(parent, engine, oclass, &priv); | |
116 | *pobject = nv_object(priv); | |
117 | if (ret) | |
118 | return ret; | |
119 | ||
120 | priv->base.drive = nv10_gpio_drive; | |
121 | priv->base.sense = nv10_gpio_sense; | |
122 | priv->base.irq_enable = nv10_gpio_irq_enable; | |
123 | nv_subdev(priv)->intr = nv10_gpio_intr; | |
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124 | return 0; |
125 | } | |
126 | ||
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127 | static void |
128 | nv10_gpio_dtor(struct nouveau_object *object) | |
47e5d5cb | 129 | { |
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130 | struct nv10_gpio_priv *priv = (void *)object; |
131 | nouveau_gpio_destroy(&priv->base); | |
47e5d5cb | 132 | } |
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133 | |
134 | static int | |
135 | nv10_gpio_init(struct nouveau_object *object) | |
136 | { | |
137 | struct nv10_gpio_priv *priv = (void *)object; | |
138 | int ret; | |
139 | ||
140 | ret = nouveau_gpio_init(&priv->base); | |
141 | if (ret) | |
142 | return ret; | |
143 | ||
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144 | nv_wr32(priv, 0x001144, 0x00000000); |
145 | nv_wr32(priv, 0x001104, 0xffffffff); | |
146 | return 0; | |
147 | } | |
148 | ||
149 | static int | |
150 | nv10_gpio_fini(struct nouveau_object *object, bool suspend) | |
151 | { | |
152 | struct nv10_gpio_priv *priv = (void *)object; | |
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153 | nv_wr32(priv, 0x001144, 0x00000000); |
154 | return nouveau_gpio_fini(&priv->base, suspend); | |
155 | } | |
156 | ||
157 | struct nouveau_oclass | |
158 | nv10_gpio_oclass = { | |
159 | .handle = NV_SUBDEV(GPIO, 0x10), | |
160 | .ofuncs = &(struct nouveau_ofuncs) { | |
161 | .ctor = nv10_gpio_ctor, | |
162 | .dtor = nv10_gpio_dtor, | |
163 | .init = nv10_gpio_init, | |
164 | .fini = nv10_gpio_fini, | |
165 | }, | |
166 | }; |