drm/nouveau/gpio: use base constructor for all implementations
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / gpio / nvd0.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
fa531bc8 25#include "priv.h"
e0996aea 26
fa531bc8 27void
1ed73166 28nvd0_gpio_reset(struct nouveau_gpio *gpio, u8 match)
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29{
30 struct nouveau_bios *bios = nouveau_bios(gpio);
d2bcea68 31 u8 ver, len;
e0996aea 32 u16 entry;
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33 int ent = -1;
34
d2bcea68 35 while ((entry = dcb_gpio_entry(bios, 0, ++ent, &ver, &len))) {
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36 u32 data = nv_ro32(bios, entry);
37 u8 line = (data & 0x0000003f);
38 u8 defs = !!(data & 0x00000080);
39 u8 func = (data & 0x0000ff00) >> 8;
40 u8 unk0 = (data & 0x00ff0000) >> 16;
41 u8 unk1 = (data & 0x1f000000) >> 24;
42
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43 if ( func == DCB_GPIO_UNUSED ||
44 (match != DCB_GPIO_UNUSED && match != func))
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45 continue;
46
47 gpio->set(gpio, 0, func, line, defs);
48
bc3b0c41 49 nv_mask(gpio, 0x00d610 + (line * 4), 0xff, unk0);
e0996aea 50 if (unk1--)
bc3b0c41 51 nv_mask(gpio, 0x00d740 + (unk1 * 4), 0xff, line);
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52 }
53}
54
fa531bc8 55int
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56nvd0_gpio_drive(struct nouveau_gpio *gpio, int line, int dir, int out)
57{
58 u32 data = ((dir ^ 1) << 13) | (out << 12);
59 nv_mask(gpio, 0x00d610 + (line * 4), 0x00003000, data);
60 nv_mask(gpio, 0x00d604, 0x00000001, 0x00000001); /* update? */
61 return 0;
62}
63
fa531bc8 64int
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65nvd0_gpio_sense(struct nouveau_gpio *gpio, int line)
66{
67 return !!(nv_rd32(gpio, 0x00d610 + (line * 4)) & 0x00004000);
68}
69
d93174ec 70struct nouveau_oclass *
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71nvd0_gpio_oclass = &(struct nouveau_gpio_impl) {
72 .base.handle = NV_SUBDEV(GPIO, 0xd0),
73 .base.ofuncs = &(struct nouveau_ofuncs) {
bc3b0c41 74 .ctor = _nouveau_gpio_ctor,
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75 .dtor = _nouveau_gpio_dtor,
76 .init = _nouveau_gpio_init,
77 .fini = _nouveau_gpio_fini,
e0996aea 78 },
7356859a 79 .lines = 32,
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80 .intr_stat = nv92_gpio_intr_stat,
81 .intr_mask = nv92_gpio_intr_mask,
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82 .drive = nvd0_gpio_drive,
83 .sense = nvd0_gpio_sense,
84 .reset = nvd0_gpio_reset,
7356859a 85}.base;
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