[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / i2c / nv94.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "nv50.h"

#define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args)
#define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)

static void
auxch_fini(struct nouveau_i2c *aux, int ch)
{
	nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
}

static int
auxch_init(struct nouveau_i2c *aux, int ch)
{
	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
	const u32 urep = unksel ? 0x01000000 : 0x02000000;
	u32 ctrl, timeout;

	/* wait up to 1ms for any previous transaction to be done... */
	timeout = 1000;
	do {
		ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
		udelay(1);
		if (!timeout--) {
			AUX_ERR("begin idle timeout 0x%08x\n", ctrl);
			return -EBUSY;
		}
	} while (ctrl & 0x03010000);

	/* set some magic, and wait up to 1ms for it to appear */
	nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
	timeout = 1000;
	do {
		ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
		udelay(1);
		if (!timeout--) {
			AUX_ERR("magic wait 0x%08x\n", ctrl);
			auxch_fini(aux, ch);
			return -EBUSY;
		}
	} while ((ctrl & 0x03000000) != urep);

	return 0;
}

int
nv94_aux(struct nouveau_i2c_port *base, bool retry,
	 u8 type, u32 addr, u8 *data, u8 size)
{
	struct nouveau_i2c *aux = nouveau_i2c(base);
	struct nv50_i2c_port *port = (void *)base;
	u32 ctrl, stat, timeout, retries;
	u32 xbuf[4] = {};
	int ch = port->addr;
	int ret, i;

	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);

	ret = auxch_init(aux, ch);
	if (ret)
		goto out;

	stat = nv_rd32(aux, 0x00e4e8 + (ch * 0x50));
	if (!(stat & 0x10000000)) {
		AUX_DBG("sink not detected\n");
		ret = -ENXIO;
		goto out;
	}

	if (!(type & 1)) {
		memcpy(xbuf, data, size);
		for (i = 0; i < 16; i += 4) {
			AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
			nv_wr32(aux, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
		}
	}

	ctrl  = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
	ctrl &= ~0x0001f0ff;
	ctrl |= type << 12;
	ctrl |= size - 1;
	nv_wr32(aux, 0x00e4e0 + (ch * 0x50), addr);

	/* (maybe) retry transaction a number of times on failure... */
	for (retries = 0; !ret && retries < 32; retries++) {
		/* reset, and delay a while if this is a retry */
		nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
		nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
		if (retries)
			udelay(400);

		/* transaction request, wait up to 1ms for it to complete */
		nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);

		timeout = 1000;
		do {
			ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
			udelay(1);
			if (!timeout--) {
				AUX_ERR("tx req timeout 0x%08x\n", ctrl);
				ret = -EIO;
				goto out;
			}
		} while (ctrl & 0x00010000);
		ret = 1;

		/* read status, and check if transaction completed ok */
		stat = nv_mask(aux, 0x00e4e8 + (ch * 0x50), 0, 0);
		if ((stat & 0x000f0000) == 0x00080000 ||
		    (stat & 0x000f0000) == 0x00020000)
			ret = retry ? 0 : 1;
		if ((stat & 0x00000100))
			ret = -ETIMEDOUT;
		if ((stat & 0x00000e00))
			ret = -EIO;

		AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
	}

	if (type & 1) {
		for (i = 0; i < 16; i += 4) {
			xbuf[i / 4] = nv_rd32(aux, 0x00e4d0 + (ch * 0x50) + i);
			AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
		}
		memcpy(data, xbuf, size);
	}

out:
	auxch_fini(aux, ch);
	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;
}

void
nv94_i2c_acquire(struct nouveau_i2c_port *base)
{
	struct nv50_i2c_priv *priv = (void *)nv_object(base)->engine;
	struct nv50_i2c_port *port = (void *)base;
	if (port->ctrl) {
		nv_mask(priv, port->ctrl + 0x0c, 0x00000001, 0x00000000);
		nv_mask(priv, port->ctrl + 0x00, 0x0000f003, port->data);
	}
}

void
nv94_i2c_release(struct nouveau_i2c_port *base)
{
}

static const struct nouveau_i2c_func
nv94_i2c_func = {
	.acquire   = nv94_i2c_acquire,
	.release   = nv94_i2c_release,
	.drive_scl = nv50_i2c_drive_scl,
	.drive_sda = nv50_i2c_drive_sda,
	.sense_scl = nv50_i2c_sense_scl,
	.sense_sda = nv50_i2c_sense_sda,
};

static int
nv94_i2c_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		   struct nouveau_oclass *oclass, void *data, u32 index,
		   struct nouveau_object **pobject)
{
	struct dcb_i2c_entry *info = data;
	struct nv50_i2c_port *port;
	int ret;

	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
				      &nouveau_i2c_bit_algo, &nv94_i2c_func,
				      &port);
	*pobject = nv_object(port);
	if (ret)
		return ret;

	if (info->drive >= nv50_i2c_addr_nr)
		return -EINVAL;

	port->state = 7;
	port->addr = nv50_i2c_addr[info->drive];
	if (info->share != DCB_I2C_UNUSED) {
		port->ctrl = 0x00e500 + (info->share * 0x50);
		port->data = 0x0000e001;
	}
	return 0;
}

static const struct nouveau_i2c_func
nv94_aux_func = {
	.acquire   = nv94_i2c_acquire,
	.release   = nv94_i2c_release,
	.aux       = nv94_aux,
};

int
nv94_aux_port_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
		   struct nouveau_oclass *oclass, void *data, u32 index,
		   struct nouveau_object **pobject)
{
	struct dcb_i2c_entry *info = data;
	struct nv50_i2c_port *port;
	int ret;

	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
				      &nouveau_i2c_aux_algo, &nv94_aux_func,
				      &port);
	*pobject = nv_object(port);
	if (ret)
		return ret;

	port->base.aux = info->drive;
	port->addr = info->drive;
	if (info->share != DCB_I2C_UNUSED) {
		port->ctrl = 0x00e500 + (info->drive * 0x50);
		port->data = 0x00002002;
	}

	return 0;
}

static struct nouveau_oclass
nv94_i2c_sclass[] = {
	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
	  .ofuncs = &(struct nouveau_ofuncs) {
		  .ctor = nv94_i2c_port_ctor,
		  .dtor = _nouveau_i2c_port_dtor,
		  .init = nv50_i2c_port_init,
		  .fini = _nouveau_i2c_port_fini,
	  },
	},
	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
	  .ofuncs = &(struct nouveau_ofuncs) {
		  .ctor = nv94_aux_port_ctor,
		  .dtor = _nouveau_i2c_port_dtor,
		  .init = _nouveau_i2c_port_init,
		  .fini = _nouveau_i2c_port_fini,
	  },
	},
	{}
};

struct nouveau_oclass *
nv94_i2c_oclass = &(struct nouveau_i2c_impl) {
	.base.handle = NV_SUBDEV(I2C, 0x94),
	.base.ofuncs = &(struct nouveau_ofuncs) {
		.ctor = _nouveau_i2c_ctor,
		.dtor = _nouveau_i2c_dtor,
		.init = _nouveau_i2c_init,
		.fini = _nouveau_i2c_fini,
	},
	.sclass = nv94_i2c_sclass,
}.base;
Commit	Line	Data
31a34aa4	1	/*
7dcd060c	2	* Copyright 2012 Red Hat Inc.
31a34aa4 BS	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
7dcd060c	25	#include "nv50.h"
31a34aa4	26
31a34aa4 BS	27	#define AUX_DBG(fmt, args...) nv_debug(aux, "AUXCH(%d): " fmt, ch, ##args)
	28	#define AUX_ERR(fmt, args...) nv_error(aux, "AUXCH(%d): " fmt, ch, ##args)
	29
	30	static void
	31	auxch_fini(struct nouveau_i2c *aux, int ch)
	32	{
	33	nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
	34	}
	35
	36	static int
	37	auxch_init(struct nouveau_i2c *aux, int ch)
	38	{
	39	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
	40	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
	41	const u32 urep = unksel ? 0x01000000 : 0x02000000;
	42	u32 ctrl, timeout;
	43
	44	/* wait up to 1ms for any previous transaction to be done... */
	45	timeout = 1000;
	46	do {
	47	ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
	48	udelay(1);
	49	if (!timeout--) {
	50	AUX_ERR("begin idle timeout 0x%08x\n", ctrl);
	51	return -EBUSY;
	52	}
	53	} while (ctrl & 0x03010000);
	54
	55	/* set some magic, and wait up to 1ms for it to appear */
	56	nv_mask(aux, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
	57	timeout = 1000;
	58	do {
	59	ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
	60	udelay(1);
	61	if (!timeout--) {
	62	AUX_ERR("magic wait 0x%08x\n", ctrl);
	63	auxch_fini(aux, ch);
	64	return -EBUSY;
	65	}
	66	} while ((ctrl & 0x03000000) != urep);
	67
	68	return 0;
	69	}
	70
	71	int
842c2953 BS	72	nv94_aux(struct nouveau_i2c_port *base, bool retry,
842c2953 BS	73	u8 type, u32 addr, u8 *data, u8 size)
31a34aa4	74	{
7dcd060c BS	75	struct nouveau_i2c *aux = nouveau_i2c(base);
7dcd060c BS	76	struct nv50_i2c_port port = (void )base;
31a34aa4 BS	77	u32 ctrl, stat, timeout, retries;
31a34aa4 BS	78	u32 xbuf[4] = {};
7dcd060c	79	int ch = port->addr;
31a34aa4 BS	80	int ret, i;
	81
	82	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
	83
	84	ret = auxch_init(aux, ch);
	85	if (ret)
	86	goto out;
	87
	88	stat = nv_rd32(aux, 0x00e4e8 + (ch * 0x50));
	89	if (!(stat & 0x10000000)) {
	90	AUX_DBG("sink not detected\n");
	91	ret = -ENXIO;
	92	goto out;
	93	}
	94
	95	if (!(type & 1)) {
	96	memcpy(xbuf, data, size);
	97	for (i = 0; i < 16; i += 4) {
	98	AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
	99	nv_wr32(aux, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
	100	}
	101	}
	102
	103	ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
	104	ctrl &= ~0x0001f0ff;
	105	ctrl \|= type << 12;
	106	ctrl \|= size - 1;
	107	nv_wr32(aux, 0x00e4e0 + (ch * 0x50), addr);
	108
842c2953 BS	109	/* (maybe) retry transaction a number of times on failure... */
842c2953 BS	110	for (retries = 0; !ret && retries < 32; retries++) {
31a34aa4 BS	111	/* reset, and delay a while if this is a retry */
	112	nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x80000000 \| ctrl);
	113	nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00000000 \| ctrl);
	114	if (retries)
	115	udelay(400);
	116
	117	/* transaction request, wait up to 1ms for it to complete */
	118	nv_wr32(aux, 0x00e4e4 + (ch * 0x50), 0x00010000 \| ctrl);
	119
	120	timeout = 1000;
	121	do {
	122	ctrl = nv_rd32(aux, 0x00e4e4 + (ch * 0x50));
	123	udelay(1);
	124	if (!timeout--) {
	125	AUX_ERR("tx req timeout 0x%08x\n", ctrl);
842c2953	126	ret = -EIO;
31a34aa4 BS	127	goto out;
	128	}
	129	} while (ctrl & 0x00010000);
842c2953	130	ret = 1;
31a34aa4 BS	131
	132	/* read status, and check if transaction completed ok */
	133	stat = nv_mask(aux, 0x00e4e8 + (ch * 0x50), 0, 0);
842c2953 BS	134	if ((stat & 0x000f0000) == 0x00080000 \|\|
	135	(stat & 0x000f0000) == 0x00020000)
	136	ret = retry ? 0 : 1;
	137	if ((stat & 0x00000100))
	138	ret = -ETIMEDOUT;
	139	if ((stat & 0x00000e00))
	140	ret = -EIO;
31a34aa4 BS	141
	142	AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
	143	}
	144
	145	if (type & 1) {
	146	for (i = 0; i < 16; i += 4) {
	147	xbuf[i / 4] = nv_rd32(aux, 0x00e4d0 + (ch * 0x50) + i);
	148	AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
	149	}
	150	memcpy(data, xbuf, size);
	151	}
	152
	153	out:
	154	auxch_fini(aux, ch);
842c2953	155	return ret < 0 ? ret : (stat & 0x000f0000) >> 16;
31a34aa4 BS	156	}
	157
	158	void
7dcd060c	159	nv94_i2c_acquire(struct nouveau_i2c_port *base)
31a34aa4	160	{
7dcd060c BS	161	struct nv50_i2c_priv priv = (void )nv_object(base)->engine;
	162	struct nv50_i2c_port port = (void )base;
	163	if (port->ctrl) {
	164	nv_mask(priv, port->ctrl + 0x0c, 0x00000001, 0x00000000);
	165	nv_mask(priv, port->ctrl + 0x00, 0x0000f003, port->data);
31a34aa4 BS	166	}
31a34aa4 BS	167	}
7dcd060c BS	168
	169	void
	170	nv94_i2c_release(struct nouveau_i2c_port *base)
	171	{
	172	}
	173
	174	static const struct nouveau_i2c_func
	175	nv94_i2c_func = {
	176	.acquire = nv94_i2c_acquire,
	177	.release = nv94_i2c_release,
	178	.drive_scl = nv50_i2c_drive_scl,
	179	.drive_sda = nv50_i2c_drive_sda,
	180	.sense_scl = nv50_i2c_sense_scl,
	181	.sense_sda = nv50_i2c_sense_sda,
	182	};
	183
	184	static int
	185	nv94_i2c_port_ctor(struct nouveau_object parent, struct nouveau_object engine,
	186	struct nouveau_oclass oclass, void data, u32 index,
	187	struct nouveau_object **pobject)
	188	{
	189	struct dcb_i2c_entry *info = data;
	190	struct nv50_i2c_port *port;
	191	int ret;
	192
	193	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
c865534f IM	194	&nouveau_i2c_bit_algo, &nv94_i2c_func,
c865534f IM	195	&port);
7dcd060c BS	196	*pobject = nv_object(port);
	197	if (ret)
	198	return ret;
	199
	200	if (info->drive >= nv50_i2c_addr_nr)
	201	return -EINVAL;
	202
7dcd060c BS	203	port->state = 7;
	204	port->addr = nv50_i2c_addr[info->drive];
	205	if (info->share != DCB_I2C_UNUSED) {
	206	port->ctrl = 0x00e500 + (info->share * 0x50);
	207	port->data = 0x0000e001;
	208	}
	209	return 0;
	210	}
	211
	212	static const struct nouveau_i2c_func
	213	nv94_aux_func = {
	214	.acquire = nv94_i2c_acquire,
	215	.release = nv94_i2c_release,
	216	.aux = nv94_aux,
	217	};
	218
	219	int
	220	nv94_aux_port_ctor(struct nouveau_object parent, struct nouveau_object engine,
	221	struct nouveau_oclass oclass, void data, u32 index,
	222	struct nouveau_object **pobject)
	223	{
	224	struct dcb_i2c_entry *info = data;
	225	struct nv50_i2c_port *port;
	226	int ret;
	227
	228	ret = nouveau_i2c_port_create(parent, engine, oclass, index,
c865534f IM	229	&nouveau_i2c_aux_algo, &nv94_aux_func,
c865534f IM	230	&port);
7dcd060c BS	231	*pobject = nv_object(port);
	232	if (ret)
	233	return ret;
	234
3668a339	235	port->base.aux = info->drive;
7dcd060c BS	236	port->addr = info->drive;
	237	if (info->share != DCB_I2C_UNUSED) {
	238	port->ctrl = 0x00e500 + (info->drive * 0x50);
	239	port->data = 0x00002002;
	240	}
	241
	242	return 0;
	243	}
	244
	245	static struct nouveau_oclass
	246	nv94_i2c_sclass[] = {
	247	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_BIT),
	248	.ofuncs = &(struct nouveau_ofuncs) {
	249	.ctor = nv94_i2c_port_ctor,
	250	.dtor = _nouveau_i2c_port_dtor,
	251	.init = nv50_i2c_port_init,
	252	.fini = _nouveau_i2c_port_fini,
	253	},
	254	},
	255	{ .handle = NV_I2C_TYPE_DCBI2C(DCB_I2C_NVIO_AUX),
	256	.ofuncs = &(struct nouveau_ofuncs) {
	257	.ctor = nv94_aux_port_ctor,
	258	.dtor = _nouveau_i2c_port_dtor,
	259	.init = _nouveau_i2c_port_init,
	260	.fini = _nouveau_i2c_port_fini,
	261	},
	262	},
	263	{}
	264	};
	265
c26fe843 BS	266	struct nouveau_oclass *
	267	nv94_i2c_oclass = &(struct nouveau_i2c_impl) {
	268	.base.handle = NV_SUBDEV(I2C, 0x94),
	269	.base.ofuncs = &(struct nouveau_ofuncs) {
	270	.ctor = _nouveau_i2c_ctor,
7dcd060c BS	271	.dtor = _nouveau_i2c_dtor,
	272	.init = _nouveau_i2c_init,
	273	.fini = _nouveau_i2c_fini,
	274	},
c26fe843 BS	275	.sclass = nv94_i2c_sclass,
c26fe843 BS	276	}.base;