drm/nouveau/pbus: add a PBUS subdev that hands IRQs to the right subdevs
[deliverable/linux.git] / drivers / gpu / drm / nouveau / core / subdev / mc / nvc0.c
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1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/mc.h>
26
27struct nvc0_mc_priv {
28 struct nouveau_mc base;
29};
30
31static const struct nouveau_mc_intr
32nvc0_mc_intr[] = {
33 { 0x00000001, NVDEV_ENGINE_PPP },
34 { 0x00000020, NVDEV_ENGINE_COPY0 },
35 { 0x00000040, NVDEV_ENGINE_COPY1 },
36 { 0x00000100, NVDEV_ENGINE_FIFO },
37 { 0x00001000, NVDEV_ENGINE_GR },
38 { 0x00008000, NVDEV_ENGINE_BSP },
a10220bb 39 { 0x00040000, NVDEV_SUBDEV_THERM },
a7416d0d 40 { 0x00020000, NVDEV_ENGINE_VP },
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41 { 0x00100000, NVDEV_SUBDEV_TIMER },
42 { 0x00200000, NVDEV_SUBDEV_GPIO },
861d2107 43 { 0x02000000, NVDEV_SUBDEV_LTCG },
7d9115de 44 { 0x04000000, NVDEV_ENGINE_DISP },
a10220bb 45 { 0x10000000, NVDEV_SUBDEV_BUS },
2c1a425e 46 { 0x40000000, NVDEV_SUBDEV_IBUS },
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47 { 0x80000000, NVDEV_ENGINE_SW },
48 {},
49};
50
51static int
52nvc0_mc_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
53 struct nouveau_oclass *oclass, void *data, u32 size,
54 struct nouveau_object **pobject)
55{
56 struct nvc0_mc_priv *priv;
57 int ret;
58
59 ret = nouveau_mc_create(parent, engine, oclass, &priv);
60 *pobject = nv_object(priv);
61 if (ret)
62 return ret;
63
64 nv_subdev(priv)->intr = nouveau_mc_intr;
65 priv->base.intr_map = nvc0_mc_intr;
66 return 0;
67}
68
69struct nouveau_oclass
70nvc0_mc_oclass = {
71 .handle = NV_SUBDEV(MC, 0xc0),
72 .ofuncs = &(struct nouveau_ofuncs) {
73 .ctor = nvc0_mc_ctor,
74 .dtor = _nouveau_mc_dtor,
75 .init = nv50_mc_init,
76 .fini = _nouveau_mc_fini,
77 },
78};
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