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a11c3198 BS |
1 | /* |
2 | * Copyright 2010 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
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25 | #include <core/device.h> |
26 | #include <core/gpuobj.h> | |
a11c3198 | 27 | |
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28 | #include <subdev/timer.h> |
29 | #include <subdev/fb.h> | |
02a841d4 | 30 | #include <subdev/vm.h> |
a11c3198 | 31 | |
3863c9bc BS |
32 | struct nv50_vmmgr_priv { |
33 | struct nouveau_vmmgr base; | |
34 | spinlock_t lock; | |
35 | }; | |
36 | ||
a11c3198 | 37 | void |
3ee01281 BS |
38 | nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde, |
39 | struct nouveau_gpuobj *pgt[2]) | |
a11c3198 | 40 | { |
3ee01281 BS |
41 | u64 phys = 0xdeadcafe00000000ULL; |
42 | u32 coverage = 0; | |
a11c3198 | 43 | |
3ee01281 | 44 | if (pgt[0]) { |
3863c9bc | 45 | phys = 0x00000003 | pgt[0]->addr; /* present, 4KiB pages */ |
3ee01281 BS |
46 | coverage = (pgt[0]->size >> 3) << 12; |
47 | } else | |
48 | if (pgt[1]) { | |
3863c9bc | 49 | phys = 0x00000001 | pgt[1]->addr; /* present */ |
3ee01281 | 50 | coverage = (pgt[1]->size >> 3) << 16; |
a11c3198 BS |
51 | } |
52 | ||
3ee01281 | 53 | if (phys & 1) { |
3ee01281 BS |
54 | if (coverage <= 32 * 1024 * 1024) |
55 | phys |= 0x60; | |
56 | else if (coverage <= 64 * 1024 * 1024) | |
57 | phys |= 0x40; | |
9e7f96aa | 58 | else if (coverage <= 128 * 1024 * 1024) |
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59 | phys |= 0x20; |
60 | } | |
a11c3198 BS |
61 | |
62 | nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys)); | |
63 | nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys)); | |
64 | } | |
65 | ||
a11c3198 | 66 | static inline u64 |
990449c7 | 67 | vm_addr(struct nouveau_vma *vma, u64 phys, u32 memtype, u32 target) |
a11c3198 | 68 | { |
a11c3198 BS |
69 | phys |= 1; /* present */ |
70 | phys |= (u64)memtype << 40; | |
a11c3198 | 71 | phys |= target << 4; |
a11c3198 BS |
72 | if (vma->access & NV_MEM_ACCESS_SYS) |
73 | phys |= (1 << 6); | |
a11c3198 BS |
74 | if (!(vma->access & NV_MEM_ACCESS_WO)) |
75 | phys |= (1 << 3); | |
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76 | return phys; |
77 | } | |
78 | ||
79 | void | |
80 | nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, | |
8f7286f8 | 81 | struct nouveau_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta) |
a11c3198 | 82 | { |
8f7286f8 | 83 | u32 comp = (mem->memtype & 0x180) >> 7; |
990449c7 | 84 | u32 block, target; |
910d1b3a | 85 | int i; |
a11c3198 | 86 | |
990449c7 BS |
87 | /* IGPs don't have real VRAM, re-target to stolen system memory */ |
88 | target = 0; | |
3863c9bc BS |
89 | if (nouveau_fb(vma->vm->vmm)->ram.stolen) { |
90 | phys += nouveau_fb(vma->vm->vmm)->ram.stolen; | |
990449c7 BS |
91 | target = 3; |
92 | } | |
93 | ||
94 | phys = vm_addr(vma, phys, mem->memtype, target); | |
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95 | pte <<= 3; |
96 | cnt <<= 3; | |
97 | ||
98 | while (cnt) { | |
99 | u32 offset_h = upper_32_bits(phys); | |
100 | u32 offset_l = lower_32_bits(phys); | |
101 | ||
102 | for (i = 7; i >= 0; i--) { | |
103 | block = 1 << (i + 3); | |
104 | if (cnt >= block && !(pte & (block - 1))) | |
105 | break; | |
106 | } | |
107 | offset_l |= (i << 7); | |
108 | ||
109 | phys += block << (vma->node->type - 3); | |
110 | cnt -= block; | |
8f7286f8 | 111 | if (comp) { |
861d2107 | 112 | u32 tag = mem->tag->offset + ((delta >> 16) * comp); |
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113 | offset_h |= (tag << 17); |
114 | delta += block << (vma->node->type - 3); | |
115 | } | |
a11c3198 BS |
116 | |
117 | while (block) { | |
118 | nv_wo32(pgt, pte + 0, offset_l); | |
119 | nv_wo32(pgt, pte + 4, offset_h); | |
120 | pte += 8; | |
121 | block -= 8; | |
122 | } | |
123 | } | |
124 | } | |
125 | ||
126 | void | |
127 | nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt, | |
26c0c9e3 | 128 | struct nouveau_mem *mem, u32 pte, u32 cnt, dma_addr_t *list) |
a11c3198 | 129 | { |
990449c7 | 130 | u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 3 : 2; |
a11c3198 BS |
131 | pte <<= 3; |
132 | while (cnt--) { | |
990449c7 | 133 | u64 phys = vm_addr(vma, (u64)*list++, mem->memtype, target); |
a11c3198 BS |
134 | nv_wo32(pgt, pte + 0, lower_32_bits(phys)); |
135 | nv_wo32(pgt, pte + 4, upper_32_bits(phys)); | |
136 | pte += 8; | |
137 | } | |
138 | } | |
139 | ||
140 | void | |
141 | nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt) | |
142 | { | |
143 | pte <<= 3; | |
144 | while (cnt--) { | |
145 | nv_wo32(pgt, pte + 0, 0x00000000); | |
146 | nv_wo32(pgt, pte + 4, 0x00000000); | |
147 | pte += 8; | |
148 | } | |
149 | } | |
150 | ||
151 | void | |
152 | nv50_vm_flush(struct nouveau_vm *vm) | |
153 | { | |
3863c9bc | 154 | struct nouveau_engine *engine; |
6dfdd7a6 | 155 | int i; |
a11c3198 | 156 | |
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157 | for (i = 0; i < NVDEV_SUBDEV_NR; i++) { |
158 | if (atomic_read(&vm->engref[i])) { | |
159 | engine = nouveau_engine(vm->vmm, i); | |
160 | if (engine && engine->tlb_flush) | |
161 | engine->tlb_flush(engine); | |
162 | } | |
6dfdd7a6 | 163 | } |
a11c3198 BS |
164 | } |
165 | ||
166 | void | |
3863c9bc | 167 | nv50_vm_flush_engine(struct nouveau_subdev *subdev, int engine) |
a11c3198 | 168 | { |
3863c9bc | 169 | struct nv50_vmmgr_priv *priv = (void *)nouveau_vmmgr(subdev); |
04eb34a4 | 170 | unsigned long flags; |
6f70a4c3 | 171 | |
3863c9bc BS |
172 | spin_lock_irqsave(&priv->lock, flags); |
173 | nv_wr32(subdev, 0x100c80, (engine << 16) | 1); | |
174 | if (!nv_wait(subdev, 0x100c80, 0x00000001, 0x00000000)) | |
175 | nv_error(subdev, "vm flush timeout: engine %d\n", engine); | |
176 | spin_unlock_irqrestore(&priv->lock, flags); | |
a11c3198 | 177 | } |
3863c9bc BS |
178 | |
179 | static int | |
180 | nv50_vm_create(struct nouveau_vmmgr *vmm, u64 offset, u64 length, | |
181 | u64 mm_offset, struct nouveau_vm **pvm) | |
182 | { | |
183 | u32 block = (1 << (vmm->pgt_bits + 12)); | |
184 | if (block > length) | |
185 | block = length; | |
186 | ||
187 | return nouveau_vm_create(vmm, offset, length, mm_offset, block, pvm); | |
188 | } | |
189 | ||
190 | static int | |
191 | nv50_vmmgr_ctor(struct nouveau_object *parent, struct nouveau_object *engine, | |
192 | struct nouveau_oclass *oclass, void *data, u32 size, | |
193 | struct nouveau_object **pobject) | |
194 | { | |
195 | struct nv50_vmmgr_priv *priv; | |
196 | int ret; | |
197 | ||
198 | ret = nouveau_vmmgr_create(parent, engine, oclass, "VM", "vm", &priv); | |
199 | *pobject = nv_object(priv); | |
200 | if (ret) | |
201 | return ret; | |
202 | ||
ebb945a9 | 203 | priv->base.limit = 1ULL << 40; |
3863c9bc BS |
204 | priv->base.pgt_bits = 29 - 12; |
205 | priv->base.spg_shift = 12; | |
206 | priv->base.lpg_shift = 16; | |
207 | priv->base.create = nv50_vm_create; | |
208 | priv->base.map_pgt = nv50_vm_map_pgt; | |
209 | priv->base.map = nv50_vm_map; | |
210 | priv->base.map_sg = nv50_vm_map_sg; | |
211 | priv->base.unmap = nv50_vm_unmap; | |
212 | priv->base.flush = nv50_vm_flush; | |
213 | spin_lock_init(&priv->lock); | |
214 | return 0; | |
215 | } | |
216 | ||
217 | struct nouveau_oclass | |
218 | nv50_vmmgr_oclass = { | |
219 | .handle = NV_SUBDEV(VM, 0x50), | |
220 | .ofuncs = &(struct nouveau_ofuncs) { | |
221 | .ctor = nv50_vmmgr_ctor, | |
222 | .dtor = _nouveau_vmmgr_dtor, | |
223 | .init = _nouveau_vmmgr_init, | |
224 | .fini = _nouveau_vmmgr_fini, | |
225 | }, | |
226 | }; |