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drm/nouveau/falcon: convert user classes to new-style nvkm_object
[deliverable/linux.git] / drivers / gpu / drm / nouveau / include / nvif / class.h
CommitLineData
d01c3092
BS		 1#ifndef __NVIF_CLASS_H__
2#define __NVIF_CLASS_H__
3
4/*******************************************************************************
5 * class identifiers
6 ******************************************************************************/
7
8/* the below match nvidia-assigned (either in hw, or sw) class numbers */
9#define NV_DEVICE 0x00000080
10
4acfd707
BS		 11#define NV_DMA_FROM_MEMORY 0x00000002
12#define NV_DMA_TO_MEMORY 0x00000003
13#define NV_DMA_IN_MEMORY 0x0000003d
14
3740c825
BS		 15#define FERMI_TWOD_A 0x0000902d
16
9ee971a0 17#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
3740c825
BS		 18
19#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
20#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
21
648d4dfd
BS		 22#define NV04_DISP 0x00000046
23
bbf8906b
BS		 24#define NV03_CHANNEL_DMA 0x0000006b
25#define NV10_CHANNEL_DMA 0x0000006e
26#define NV17_CHANNEL_DMA 0x0000176e
27#define NV40_CHANNEL_DMA 0x0000406e
28#define NV50_CHANNEL_DMA 0x0000506e
29#define G82_CHANNEL_DMA 0x0000826e
30
31#define NV50_CHANNEL_GPFIFO 0x0000506f
32#define G82_CHANNEL_GPFIFO 0x0000826f
33#define FERMI_CHANNEL_GPFIFO 0x0000906f
34#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
89025bd4 35#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f
bbf8906b 36
648d4dfd
BS		 37#define NV50_DISP 0x00005070
38#define G82_DISP 0x00008270
39#define GT200_DISP 0x00008370
40#define GT214_DISP 0x00008570
41#define GT206_DISP 0x00008870
42#define GF110_DISP 0x00009070
43#define GK104_DISP 0x00009170
44#define GK110_DISP 0x00009270
45#define GM107_DISP 0x00009470
1f89b475 46#define GM204_DISP 0x00009570
648d4dfd
BS		 47
48#define NV50_DISP_CURSOR 0x0000507a
49#define G82_DISP_CURSOR 0x0000827a
50#define GT214_DISP_CURSOR 0x0000857a
51#define GF110_DISP_CURSOR 0x0000907a
52#define GK104_DISP_CURSOR 0x0000917a
53
54#define NV50_DISP_OVERLAY 0x0000507b
55#define G82_DISP_OVERLAY 0x0000827b
56#define GT214_DISP_OVERLAY 0x0000857b
57#define GF110_DISP_OVERLAY 0x0000907b
58#define GK104_DISP_OVERLAY 0x0000917b
59
60#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
61#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
62#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
63#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
64#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
65#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
66#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
67
68#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
69#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
70#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
71#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
72#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
73#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
74#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
75#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
76#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
1f89b475 77#define GM204_DISP_CORE_CHANNEL_DMA 0x0000957d
648d4dfd
BS		 78
79#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
80#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
81#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
82#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
83#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
84#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
85
ac9738bb
BS		 86#define FERMI_A 0x00009097
87#define FERMI_B 0x00009197
88#define FERMI_C 0x00009297
89
90#define KEPLER_A 0x0000a097
91#define KEPLER_B 0x0000a197
92#define KEPLER_C 0x0000a297
93
94#define MAXWELL_A 0x0000b097
3fed3ea9 95#define MAXWELL_B 0x0000b197
ac9738bb 96
9d498e0f
BS		 97#define GT212_MSVLD 0x000085b1
98#define IGT21A_MSVLD 0x000086b1
99#define G98_MSVLD 0x000088b1
100#define GF100_MSVLD 0x000090b1
101#define GK104_MSVLD 0x000095b1
102
103#define GT212_MSPDEC 0x000085b2
104#define G98_MSPDEC 0x000088b2
105#define GF100_MSPDEC 0x000090b2
106#define GK104_MSPDEC 0x000095b2
107
108#define GT212_MSPPP 0x000085b3
109#define G98_MSPPP 0x000088b3
110#define GF100_MSPPP 0x000090b3
111
112#define G98_SEC 0x000088b4
113
114#define GT212_DMA 0x000085b5
115#define FERMI_DMA 0x000090b5
116
117#define FERMI_DECOMPRESS 0x000090b8
118
d6bd3803
BS		 119#define FERMI_COMPUTE_A 0x000090c0
120#define FERMI_COMPUTE_B 0x000091c0
121
122#define KEPLER_COMPUTE_A 0x0000a0c0
123#define KEPLER_COMPUTE_B 0x0000a1c0
124
125#define MAXWELL_COMPUTE_A 0x0000b0c0
3fed3ea9 126#define MAXWELL_COMPUTE_B 0x0000b1c0
d6bd3803 127
d01c3092 128
803c1787
BS		 129/*******************************************************************************
130 * client
131 ******************************************************************************/
132
133#define NV_CLIENT_DEVLIST 0x00
134
135struct nv_client_devlist_v0 {
136 __u8 version;
137 __u8 count;
138 __u8 pad02[6];
139 __u64 device[];
140};
141
142
d01c3092
BS		 143/*******************************************************************************
144 * device
145 ******************************************************************************/
146
586491e6
BS		 147struct nv_device_v0 {
148 __u8 version;
149 __u8 pad01[7];
150 __u64 device; /* device identifier, ~0 for client default */
586491e6
BS		 151};
152
d01c3092 153#define NV_DEVICE_V0_INFO 0x00
d61f4c17 154#define NV_DEVICE_V0_TIME 0x01
d01c3092
BS		 155
156struct nv_device_info_v0 {
157 __u8 version;
158#define NV_DEVICE_INFO_V0_IGP 0x00
159#define NV_DEVICE_INFO_V0_PCI 0x01
160#define NV_DEVICE_INFO_V0_AGP 0x02
161#define NV_DEVICE_INFO_V0_PCIE 0x03
162#define NV_DEVICE_INFO_V0_SOC 0x04
163 __u8 platform;
164 __u16 chipset; /* from NV_PMC_BOOT_0 */
165 __u8 revision; /* from NV_PMC_BOOT_0 */
166#define NV_DEVICE_INFO_V0_TNT 0x01
167#define NV_DEVICE_INFO_V0_CELSIUS 0x02
168#define NV_DEVICE_INFO_V0_KELVIN 0x03
169#define NV_DEVICE_INFO_V0_RANKINE 0x04
170#define NV_DEVICE_INFO_V0_CURIE 0x05
171#define NV_DEVICE_INFO_V0_TESLA 0x06
172#define NV_DEVICE_INFO_V0_FERMI 0x07
173#define NV_DEVICE_INFO_V0_KEPLER 0x08
174#define NV_DEVICE_INFO_V0_MAXWELL 0x09
175 __u8 family;
176 __u8 pad06[2];
177 __u64 ram_size;
178 __u64 ram_user;
22827fa4
BS		 179 char chip[16];
180 char name[64];
d01c3092
BS		 181};
182
d61f4c17
BS		 183struct nv_device_time_v0 {
184 __u8 version;
185 __u8 pad01[7];
186 __u64 time;
187};
188
4acfd707
BS		 189
190/*******************************************************************************
191 * context dma
192 ******************************************************************************/
193
194struct nv_dma_v0 {
195 __u8 version;
196#define NV_DMA_V0_TARGET_VM 0x00
197#define NV_DMA_V0_TARGET_VRAM 0x01
198#define NV_DMA_V0_TARGET_PCI 0x02
199#define NV_DMA_V0_TARGET_PCI_US 0x03
200#define NV_DMA_V0_TARGET_AGP 0x04
201 __u8 target;
202#define NV_DMA_V0_ACCESS_VM 0x00
203#define NV_DMA_V0_ACCESS_RD 0x01
204#define NV_DMA_V0_ACCESS_WR 0x02
205#define NV_DMA_V0_ACCESS_RDWR (NV_DMA_V0_ACCESS_RD | NV_DMA_V0_ACCESS_WR)
206 __u8 access;
207 __u8 pad03[5];
208 __u64 start;
209 __u64 limit;
210 /* ... chipset-specific class data */
211};
212
213struct nv50_dma_v0 {
214 __u8 version;
215#define NV50_DMA_V0_PRIV_VM 0x00
216#define NV50_DMA_V0_PRIV_US 0x01
217#define NV50_DMA_V0_PRIV__S 0x02
218 __u8 priv;
219#define NV50_DMA_V0_PART_VM 0x00
220#define NV50_DMA_V0_PART_256 0x01
221#define NV50_DMA_V0_PART_1KB 0x02
222 __u8 part;
223#define NV50_DMA_V0_COMP_NONE 0x00
224#define NV50_DMA_V0_COMP_1 0x01
225#define NV50_DMA_V0_COMP_2 0x02
226#define NV50_DMA_V0_COMP_VM 0x03
227 __u8 comp;
228#define NV50_DMA_V0_KIND_PITCH 0x00
229#define NV50_DMA_V0_KIND_VM 0x7f
230 __u8 kind;
231 __u8 pad05[3];
232};
233
234struct gf100_dma_v0 {
235 __u8 version;
236#define GF100_DMA_V0_PRIV_VM 0x00
237#define GF100_DMA_V0_PRIV_US 0x01
238#define GF100_DMA_V0_PRIV__S 0x02
239 __u8 priv;
240#define GF100_DMA_V0_KIND_PITCH 0x00
241#define GF100_DMA_V0_KIND_VM 0xff
242 __u8 kind;
243 __u8 pad03[5];
244};
245
246struct gf110_dma_v0 {
247 __u8 version;
248#define GF110_DMA_V0_PAGE_LP 0x00
249#define GF110_DMA_V0_PAGE_SP 0x01
250 __u8 page;
251#define GF110_DMA_V0_KIND_PITCH 0x00
252#define GF110_DMA_V0_KIND_VM 0xff
253 __u8 kind;
254 __u8 pad03[5];
255};
256
96af8222
BS		 257
258/*******************************************************************************
259 * perfmon
260 ******************************************************************************/
261
45f0f94d
SP		 262#define NVIF_PERFMON_V0_QUERY_DOMAIN 0x00
263#define NVIF_PERFMON_V0_QUERY_SIGNAL 0x01
6f99c848 264#define NVIF_PERFMON_V0_QUERY_SOURCE 0x02
45f0f94d
SP		 265
266struct nvif_perfmon_query_domain_v0 {
267 __u8 version;
268 __u8 id;
269 __u8 counter_nr;
270 __u8 iter;
e4047599
SP		 271 __u16 signal_nr;
272 __u8 pad05[2];
df0b37ee 273 char name[64];
45f0f94d 274};
5a0bc4b5
SP		 275
276struct nvif_perfmon_query_signal_v0 {
277 __u8 version;
3e1b3357 278 __u8 domain;
e4047599 279 __u16 iter;
10a4d2b2 280 __u8 signal;
50d138d7
SP		 281 __u8 source_nr;
282 __u8 pad05[2];
5a0bc4b5
SP		 283 char name[64];
284};
285
6f99c848
SP		 286struct nvif_perfmon_query_source_v0 {
287 __u8 version;
288 __u8 domain;
289 __u8 signal;
290 __u8 iter;
291 __u8 pad04[4];
292 __u32 source;
293 __u32 mask;
294 char name[64];
295};
296
5a0bc4b5
SP		 297
298/*******************************************************************************
0f380436 299 * perfdom
5a0bc4b5
SP		 300 ******************************************************************************/
301
0f380436 302struct nvif_perfdom_v0 {
96af8222 303 __u8 version;
10a4d2b2 304 __u8 domain;
0f380436
SP		 305 __u8 mode;
306 __u8 pad03[1];
307 struct {
308 __u8 signal[4];
6137b5a7 309 __u64 source[4][8];
0f380436
SP		 310 __u16 logic_op;
311 } ctr[4];
96af8222
BS		 312};
313
0f380436
SP		 314#define NVIF_PERFDOM_V0_INIT 0x00
315#define NVIF_PERFDOM_V0_SAMPLE 0x01
316#define NVIF_PERFDOM_V0_READ 0x02
3bfdde17 317
0f380436 318struct nvif_perfdom_init {
3bfdde17 319};
96af8222 320
0f380436 321struct nvif_perfdom_sample {
96af8222
BS		 322};
323
0f380436 324struct nvif_perfdom_read_v0 {
96af8222
BS		 325 __u8 version;
326 __u8 pad01[7];
0f380436 327 __u32 ctr[4];
96af8222 328 __u32 clk;
0f380436 329 __u8 pad04[4];
96af8222
BS		 330};
331
a532da97
BS		 332
333/*******************************************************************************
334 * device control
335 ******************************************************************************/
336
337#define NVIF_CONTROL_PSTATE_INFO 0x00
338#define NVIF_CONTROL_PSTATE_ATTR 0x01
339#define NVIF_CONTROL_PSTATE_USER 0x02
340
341struct nvif_control_pstate_info_v0 {
342 __u8 version;
343 __u8 count; /* out: number of power states */
344#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_DISABLE (-1)
345#define NVIF_CONTROL_PSTATE_INFO_V0_USTATE_PERFMON (-2)
346 __s8 ustate_ac; /* out: target pstate index */
347 __s8 ustate_dc; /* out: target pstate index */
348 __s8 pwrsrc; /* out: current power source */
349#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN (-1)
350#define NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_PERFMON (-2)
351 __s8 pstate; /* out: current pstate index */
352 __u8 pad06[2];
353};
354
355struct nvif_control_pstate_attr_v0 {
356 __u8 version;
357#define NVIF_CONTROL_PSTATE_ATTR_V0_STATE_CURRENT (-1)
358 __s8 state; /* in: index of pstate to query
359 * out: pstate identifier
360 */
361 __u8 index; /* in: index of attribute to query
362 * out: index of next attribute, or 0 if no more
363 */
364 __u8 pad03[5];
365 __u32 min;
366 __u32 max;
367 char name[32];
368 char unit[16];
369};
370
371struct nvif_control_pstate_user_v0 {
372 __u8 version;
373#define NVIF_CONTROL_PSTATE_USER_V0_STATE_UNKNOWN (-1)
374#define NVIF_CONTROL_PSTATE_USER_V0_STATE_PERFMON (-2)
375 __s8 ustate; /* in: pstate identifier */
376 __s8 pwrsrc; /* in: target power source */
377 __u8 pad03[5];
378};
379
bbf8906b
BS		 380
381/*******************************************************************************
382 * DMA FIFO channels
383 ******************************************************************************/
384
385struct nv03_channel_dma_v0 {
159045cd
BS		 386 __u8 version;
387 __u8 chid;
388 __u8 pad02[2];
389 __u32 offset;
390 __u64 pushbuf;
391};
392
393struct nv50_channel_dma_v0 {
bbf8906b
BS		 394 __u8 version;
395 __u8 chid;
bf81df9b 396 __u8 pad02[6];
159045cd 397 __u64 vm;
bf81df9b 398 __u64 pushbuf;
bbf8906b
BS		 399 __u64 offset;
400};
401
867920f8 402#define G82_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
bbf8906b
BS		 403
404/*******************************************************************************
405 * GPFIFO channels
406 ******************************************************************************/
407
408struct nv50_channel_gpfifo_v0 {
409 __u8 version;
410 __u8 chid;
bf81df9b 411 __u8 pad02[2];
bbf8906b
BS		 412 __u32 ilength;
413 __u64 ioffset;
bf81df9b 414 __u64 pushbuf;
159045cd
BS		 415 __u64 vm;
416};
417
418struct fermi_channel_gpfifo_v0 {
419 __u8 version;
420 __u8 chid;
421 __u8 pad02[2];
422 __u32 ilength;
423 __u64 ioffset;
424 __u64 vm;
bbf8906b
BS		 425};
426
427struct kepler_channel_gpfifo_a_v0 {
428 __u8 version;
429#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
37a5d028 430#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPDEC 0x02
fd8666f7 431#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP 0x04
eccf7e8a 432#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
bbf8906b
BS		 433#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
434#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
435#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
436 __u8 engine;
437 __u16 chid;
bbf8906b
BS		 438 __u32 ilength;
439 __u64 ioffset;
159045cd 440 __u64 vm;
bbf8906b
BS		 441};
442
bf0eb898
BS		 443/*******************************************************************************
444 * legacy display
445 ******************************************************************************/
446
80bc340b
BS		 447#define NV04_DISP_NTFY_VBLANK 0x00
448#define NV04_DISP_NTFY_CONN 0x01
449
4952b4d3
BS		 450struct nv04_disp_mthd_v0 {
451 __u8 version;
452#define NV04_DISP_SCANOUTPOS 0x00
453 __u8 method;
454 __u8 head;
455 __u8 pad03[5];
456};
457
458struct nv04_disp_scanoutpos_v0 {
459 __u8 version;
460 __u8 pad01[7];
461 __s64 time[2];
462 __u16 vblanks;
463 __u16 vblanke;
464 __u16 vtotal;
465 __u16 vline;
466 __u16 hblanks;
467 __u16 hblanke;
468 __u16 htotal;
469 __u16 hline;
470};
471
bf0eb898
BS		 472/*******************************************************************************
473 * display
474 ******************************************************************************/
475
476#define NV50_DISP_MTHD 0x00
477
478struct nv50_disp_mthd_v0 {
479 __u8 version;
4952b4d3 480#define NV50_DISP_SCANOUTPOS 0x00
bf0eb898
BS		 481 __u8 method;
482 __u8 head;
483 __u8 pad03[5];
484};
485
486struct nv50_disp_mthd_v1 {
487 __u8 version;
488#define NV50_DISP_MTHD_V1_DAC_PWR 0x10
489#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11
490#define NV50_DISP_MTHD_V1_SOR_PWR 0x20
491#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21
492#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22
493#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23
494#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24
495#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30
496 __u8 method;
497 __u16 hasht;
498 __u16 hashm;
499 __u8 pad06[2];
500};
501
502struct nv50_disp_dac_pwr_v0 {
503 __u8 version;
504 __u8 state;
505 __u8 data;
506 __u8 vsync;
507 __u8 hsync;
508 __u8 pad05[3];
509};
510
c4abd317
BS		 511struct nv50_disp_dac_load_v0 {
512 __u8 version;
513 __u8 load;
8bd62a83
BS		 514 __u8 pad02[2];
515 __u32 data;
c4abd317
BS		 516};
517
d55b4af9
BS		 518struct nv50_disp_sor_pwr_v0 {
519 __u8 version;
520 __u8 state;
521 __u8 pad02[6];
522};
523
120b0c39
BS		 524struct nv50_disp_sor_hda_eld_v0 {
525 __u8 version;
526 __u8 pad01[7];
527 __u8 data[];
528};
529
e00f2235
BS		 530struct nv50_disp_sor_hdmi_pwr_v0 {
531 __u8 version;
532 __u8 state;
533 __u8 max_ac_packet;
534 __u8 rekey;
535 __u8 pad04[4];
536};
537
a3761fa2
BS		 538struct nv50_disp_sor_lvds_script_v0 {
539 __u8 version;
540 __u8 pad01[1];
541 __u16 script;
542 __u8 pad04[4];
543};
544
c02ed2bf
BS		 545struct nv50_disp_sor_dp_pwr_v0 {
546 __u8 version;
547 __u8 state;
548 __u8 pad02[6];
549};
550
67cb49c4
BS		 551struct nv50_disp_pior_pwr_v0 {
552 __u8 version;
553 __u8 state;
554 __u8 type;
555 __u8 pad03[5];
556};
557
648d4dfd
BS		 558/* core */
559struct nv50_disp_core_channel_dma_v0 {
560 __u8 version;
bf81df9b
BS		 561 __u8 pad01[7];
562 __u64 pushbuf;
648d4dfd
BS		 563};
564
b38a2322
BS		 565#define NV50_DISP_CORE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
566
648d4dfd
BS		 567/* cursor immediate */
568struct nv50_disp_cursor_v0 {
569 __u8 version;
570 __u8 head;
571 __u8 pad02[6];
572};
573
b38a2322
BS		 574#define NV50_DISP_CURSOR_V0_NTFY_UEVENT 0x00
575
648d4dfd
BS		 576/* base */
577struct nv50_disp_base_channel_dma_v0 {
578 __u8 version;
648d4dfd 579 __u8 head;
bf81df9b
BS		 580 __u8 pad02[6];
581 __u64 pushbuf;
648d4dfd
BS		 582};
583
b38a2322
BS		 584#define NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
585
648d4dfd
BS		 586/* overlay */
587struct nv50_disp_overlay_channel_dma_v0 {
588 __u8 version;
648d4dfd 589 __u8 head;
bf81df9b
BS		 590 __u8 pad02[6];
591 __u64 pushbuf;
648d4dfd
BS		 592};
593
b38a2322
BS		 594#define NV50_DISP_OVERLAY_CHANNEL_DMA_V0_NTFY_UEVENT 0x00
595
648d4dfd
BS		 596/* overlay immediate */
597struct nv50_disp_overlay_v0 {
598 __u8 version;
599 __u8 head;
600 __u8 pad02[6];
601};
602
b38a2322 603#define NV50_DISP_OVERLAY_V0_NTFY_UEVENT 0x00
ac9738bb 604
cd459e77
BS		 605/*******************************************************************************
606 * software
607 ******************************************************************************/
608
898a2b32
BS		 609#define NVSW_NTFY_UEVENT 0x00
610
cd459e77
BS		 611#define NV04_NVSW_GET_REF 0x00
612
613struct nv04_nvsw_get_ref_v0 {
614 __u8 version;
615 __u8 pad01[3];
616 __u32 ref;
617};
618
ac9738bb
BS		 619/*******************************************************************************
620 * fermi
621 ******************************************************************************/
622
623#define FERMI_A_ZBC_COLOR 0x00
624#define FERMI_A_ZBC_DEPTH 0x01
625
626struct fermi_a_zbc_color_v0 {
627 __u8 version;
628#define FERMI_A_ZBC_COLOR_V0_FMT_ZERO 0x01
629#define FERMI_A_ZBC_COLOR_V0_FMT_UNORM_ONE 0x02
630#define FERMI_A_ZBC_COLOR_V0_FMT_RF32_GF32_BF32_AF32 0x04
631#define FERMI_A_ZBC_COLOR_V0_FMT_R16_G16_B16_A16 0x08
632#define FERMI_A_ZBC_COLOR_V0_FMT_RN16_GN16_BN16_AN16 0x0c
633#define FERMI_A_ZBC_COLOR_V0_FMT_RS16_GS16_BS16_AS16 0x10
634#define FERMI_A_ZBC_COLOR_V0_FMT_RU16_GU16_BU16_AU16 0x14
635#define FERMI_A_ZBC_COLOR_V0_FMT_RF16_GF16_BF16_AF16 0x16
636#define FERMI_A_ZBC_COLOR_V0_FMT_A8R8G8B8 0x18
637#define FERMI_A_ZBC_COLOR_V0_FMT_A8RL8GL8BL8 0x1c
638#define FERMI_A_ZBC_COLOR_V0_FMT_A2B10G10R10 0x20
639#define FERMI_A_ZBC_COLOR_V0_FMT_AU2BU10GU10RU10 0x24
640#define FERMI_A_ZBC_COLOR_V0_FMT_A8B8G8R8 0x28
641#define FERMI_A_ZBC_COLOR_V0_FMT_A8BL8GL8RL8 0x2c
642#define FERMI_A_ZBC_COLOR_V0_FMT_AN8BN8GN8RN8 0x30
643#define FERMI_A_ZBC_COLOR_V0_FMT_AS8BS8GS8RS8 0x34
644#define FERMI_A_ZBC_COLOR_V0_FMT_AU8BU8GU8RU8 0x38
645#define FERMI_A_ZBC_COLOR_V0_FMT_A2R10G10B10 0x3c
646#define FERMI_A_ZBC_COLOR_V0_FMT_BF10GF11RF11 0x40
647 __u8 format;
648 __u8 index;
649 __u8 pad03[5];
650 __u32 ds[4];
651 __u32 l2[4];
652};
653
654struct fermi_a_zbc_depth_v0 {
655 __u8 version;
656#define FERMI_A_ZBC_DEPTH_V0_FMT_FP32 0x01
657 __u8 format;
658 __u8 index;
659 __u8 pad03[5];
660 __u32 ds;
661 __u32 l2;
662};
663
d01c3092 664#endif
Linux kernel - Deliverables
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