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drm/nouveau/clock: pull in the implementation from all over the place
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861 30
67eda20e 31#include <linux/io-mapping.h>
78339fb7 32#include <linux/firmware.h>
67eda20e 33
6ee73861
BS		 34/* these defines are made up */
35#define NV_CIO_CRE_44_HEADA 0x0
36#define NV_CIO_CRE_44_HEADB 0x3
37#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
6ee73861
BS		 38
39#define EDID1_LEN 128
40
41#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
42#define LOG_OLD_VALUE(x)
43
6ee73861
BS		 44struct init_exec {
45 bool execute;
46 bool repeat;
47};
48
49static bool nv_cksum(const uint8_t *data, unsigned int length)
50{
51 /*
52 * There's a few checksums in the BIOS, so here's a generic checking
53 * function.
54 */
55 int i;
56 uint8_t sum = 0;
57
58 for (i = 0; i < length; i++)
59 sum += data[i];
60
61 if (sum)
62 return true;
63
64 return false;
65}
66
6ee73861
BS		 67struct init_tbl_entry {
68 char *name;
69 uint8_t id;
9170a824
BS		 70 /* Return:
71 * > 0: success, length of opcode
72 * 0: success, but abort further parsing of table (INIT_DONE etc)
73 * < 0: failure, table parsing will be aborted
74 */
37383650 75 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 76};
77
ec64a408 78static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 79
80#define MACRO_INDEX_SIZE 2
81#define MACRO_SIZE 8
82#define CONDITION_SIZE 12
83#define IO_FLAG_CONDITION_SIZE 9
84#define IO_CONDITION_SIZE 5
85#define MEM_INIT_SIZE 66
86
87static void still_alive(void)
88{
89#if 0
90 sync();
c7ca4d1b 91 mdelay(2);
6ee73861
BS		 92#endif
93}
94
95static uint32_t
96munge_reg(struct nvbios *bios, uint32_t reg)
97{
98 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
99 struct dcb_entry *dcbent = bios->display.output;
100
101 if (dev_priv->card_type < NV_50)
102 return reg;
103
02e4f587
BS		 104 if (reg & 0x80000000) {
105 BUG_ON(bios->display.crtc < 0);
106 reg += bios->display.crtc * 0x800;
107 }
108
6ee73861
BS		 109 if (reg & 0x40000000) {
110 BUG_ON(!dcbent);
111
112 reg += (ffs(dcbent->or) - 1) * 0x800;
113 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
114 reg += 0x00000080;
115 }
116
02e4f587 117 reg &= ~0xe0000000;
6ee73861
BS		 118 return reg;
119}
120
121static int
122valid_reg(struct nvbios *bios, uint32_t reg)
123{
124 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
125 struct drm_device *dev = bios->dev;
126
127 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 128 if (reg & 0x2 ||
04a39c57 129 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 130 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
131
132 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 133 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 134 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
135 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
136 reg);
137
9855e584
BS		 138 if (reg >= (8*1024*1024)) {
139 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
140 return 0;
6ee73861 141 }
9855e584
BS		 142
143 return 1;
6ee73861
BS		 144}
145
146static bool
147valid_idx_port(struct nvbios *bios, uint16_t port)
148{
149 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
150 struct drm_device *dev = bios->dev;
151
152 /*
153 * If adding more ports here, the read/write functions below will need
154 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
155 * used for the port in question
156 */
157 if (dev_priv->card_type < NV_50) {
158 if (port == NV_CIO_CRX__COLOR)
159 return true;
160 if (port == NV_VIO_SRX)
161 return true;
162 } else {
163 if (port == NV_CIO_CRX__COLOR)
164 return true;
165 }
166
167 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
168 port);
169
170 return false;
171}
172
173static bool
174valid_port(struct nvbios *bios, uint16_t port)
175{
176 struct drm_device *dev = bios->dev;
177
178 /*
179 * If adding more ports here, the read/write functions below will need
180 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
181 * used for the port in question
182 */
183 if (port == NV_VIO_VSE2)
184 return true;
185
186 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
187
188 return false;
189}
190
191static uint32_t
192bios_rd32(struct nvbios *bios, uint32_t reg)
193{
194 uint32_t data;
195
196 reg = munge_reg(bios, reg);
197 if (!valid_reg(bios, reg))
198 return 0;
199
200 /*
201 * C51 sometimes uses regs with bit0 set in the address. For these
202 * cases there should exist a translation in a BIOS table to an IO
203 * port address which the BIOS uses for accessing the reg
204 *
205 * These only seem to appear for the power control regs to a flat panel,
206 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
207 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
208 * suspend-resume mmio trace from a C51 will be required to see if this
209 * is true for the power microcode in 0x14.., or whether the direct IO
210 * port access method is needed
211 */
212 if (reg & 0x1)
213 reg &= ~0x1;
214
215 data = nv_rd32(bios->dev, reg);
216
217 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
218
219 return data;
220}
221
222static void
223bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
224{
225 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
226
227 reg = munge_reg(bios, reg);
228 if (!valid_reg(bios, reg))
229 return;
230
231 /* see note in bios_rd32 */
232 if (reg & 0x1)
233 reg &= 0xfffffffe;
234
235 LOG_OLD_VALUE(bios_rd32(bios, reg));
236 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
237
04a39c57 238 if (dev_priv->vbios.execute) {
6ee73861
BS		 239 still_alive();
240 nv_wr32(bios->dev, reg, data);
241 }
242}
243
244static uint8_t
245bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
246{
247 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
248 struct drm_device *dev = bios->dev;
249 uint8_t data;
250
251 if (!valid_idx_port(bios, port))
252 return 0;
253
254 if (dev_priv->card_type < NV_50) {
255 if (port == NV_VIO_SRX)
256 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
257 else /* assume NV_CIO_CRX__COLOR */
258 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
259 } else {
260 uint32_t data32;
261
262 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
263 data = (data32 >> ((index & 3) << 3)) & 0xff;
264 }
265
266 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
267 "Head: 0x%02X, Data: 0x%02X\n",
268 port, index, bios->state.crtchead, data);
269 return data;
270}
271
272static void
273bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
274{
275 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
276 struct drm_device *dev = bios->dev;
277
278 if (!valid_idx_port(bios, port))
279 return;
280
281 /*
282 * The current head is maintained in the nvbios member state.crtchead.
283 * We trap changes to CR44 and update the head variable and hence the
284 * register set written.
285 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
286 * of the write, and to head1 after the write
287 */
288 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
289 data != NV_CIO_CRE_44_HEADB)
290 bios->state.crtchead = 0;
291
292 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
293 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
294 "Head: 0x%02X, Data: 0x%02X\n",
295 port, index, bios->state.crtchead, data);
296
297 if (bios->execute && dev_priv->card_type < NV_50) {
298 still_alive();
299 if (port == NV_VIO_SRX)
300 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
301 else /* assume NV_CIO_CRX__COLOR */
302 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
303 } else
304 if (bios->execute) {
305 uint32_t data32, shift = (index & 3) << 3;
306
307 still_alive();
308
309 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
310 data32 &= ~(0xff << shift);
311 data32 |= (data << shift);
312 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
313 }
314
315 if (port == NV_CIO_CRX__COLOR &&
316 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
317 bios->state.crtchead = 1;
318}
319
320static uint8_t
321bios_port_rd(struct nvbios *bios, uint16_t port)
322{
323 uint8_t data, head = bios->state.crtchead;
324
325 if (!valid_port(bios, port))
326 return 0;
327
328 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
329
330 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
331 port, head, data);
332
333 return data;
334}
335
336static void
337bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
338{
339 int head = bios->state.crtchead;
340
341 if (!valid_port(bios, port))
342 return;
343
344 LOG_OLD_VALUE(bios_port_rd(bios, port));
345 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
346 port, head, data);
347
348 if (!bios->execute)
349 return;
350
351 still_alive();
352 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
353}
354
355static bool
356io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
357{
358 /*
359 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
360 * for the CRTC index; 1 byte for the mask to apply to the value
361 * retrieved from the CRTC; 1 byte for the shift right to apply to the
362 * masked CRTC value; 2 bytes for the offset to the flag array, to
363 * which the shifted value is added; 1 byte for the mask applied to the
364 * value read from the flag array; and 1 byte for the value to compare
365 * against the masked byte from the flag table.
366 */
367
368 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
369 uint16_t crtcport = ROM16(bios->data[condptr]);
370 uint8_t crtcindex = bios->data[condptr + 2];
371 uint8_t mask = bios->data[condptr + 3];
372 uint8_t shift = bios->data[condptr + 4];
373 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
374 uint8_t flagarraymask = bios->data[condptr + 7];
375 uint8_t cmpval = bios->data[condptr + 8];
376 uint8_t data;
377
378 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
379 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
380 "Cmpval: 0x%02X\n",
381 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
382
383 data = bios_idxprt_rd(bios, crtcport, crtcindex);
384
385 data = bios->data[flagarray + ((data & mask) >> shift)];
386 data &= flagarraymask;
387
388 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
389 offset, data, cmpval);
390
391 return (data == cmpval);
392}
393
394static bool
395bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
396{
397 /*
398 * The condition table entry has 4 bytes for the address of the
399 * register to check, 4 bytes for a mask to apply to the register and
400 * 4 for a test comparison value
401 */
402
403 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
404 uint32_t reg = ROM32(bios->data[condptr]);
405 uint32_t mask = ROM32(bios->data[condptr + 4]);
406 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
407 uint32_t data;
408
409 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
410 offset, cond, reg, mask);
411
412 data = bios_rd32(bios, reg) & mask;
413
414 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
415 offset, data, cmpval);
416
417 return (data == cmpval);
418}
419
420static bool
421io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
422{
423 /*
424 * The IO condition entry has 2 bytes for the IO port address; 1 byte
425 * for the index to write to io_port; 1 byte for the mask to apply to
426 * the byte read from io_port+1; and 1 byte for the value to compare
427 * against the masked byte.
428 */
429
430 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
431 uint16_t io_port = ROM16(bios->data[condptr]);
432 uint8_t port_index = bios->data[condptr + 2];
433 uint8_t mask = bios->data[condptr + 3];
434 uint8_t cmpval = bios->data[condptr + 4];
435
436 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
437
438 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
439 offset, data, cmpval);
440
441 return (data == cmpval);
442}
443
6ee73861
BS		 444static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
445{
446 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 447 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 448
449 /*
450 * For the results of this function to be correct, CR44 must have been
451 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
452 * and the DCB table parsed, before the script calling the function is
453 * run. run_digital_op_script is example of how to do such setup
454 */
455
456 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
457
7f245b20 458 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 459 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
460 "(%02X)\n", dcb_entry);
461 dcb_entry = 0x7f; /* unused / invalid marker */
462 }
463
464 return dcb_entry;
465}
466
4196faa8 467static struct nouveau_i2c_port *
6ee73861
BS		 468init_i2c_device_find(struct drm_device *dev, int i2c_index)
469{
6ee73861 470 if (i2c_index == 0xff) {
486a45c2
BS		 471 struct drm_nouveau_private *dev_priv = dev->dev_private;
472 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861 473 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
486a45c2 474 int idx = dcb_entry_idx_from_crtchead(dev);
6ee73861 475
4196faa8 476 i2c_index = 0x80; //NV_I2C_DEFAULT(0);
7f245b20 477 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
4196faa8 478 i2c_index = 0x81; //NV_I2C_DEFAULT(1);
f8b0be1a
BS		 479 }
480
6ee73861
BS		 481 return nouveau_i2c_find(dev, i2c_index);
482}
483
7f245b20
BS		 484static uint32_t
485get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 486{
487 /*
488 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
489 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
490 * CR58 for CR57 = 0 to index a table of offsets to the basic
491 * 0x6808b0 address.
492 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
493 * CR58 for CR57 = 0 to index a table of offsets to the basic
494 * 0x6808b0 address, and then flip the offset by 8.
495 */
496
497 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 498 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 499 const int pramdac_offset[13] = {
500 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
501 const uint32_t pramdac_table[4] = {
502 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
503
504 if (mlv >= 0x80) {
505 int dcb_entry, dacoffset;
506
507 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
508 dcb_entry = dcb_entry_idx_from_crtchead(dev);
509 if (dcb_entry == 0x7f)
510 return 0;
7f245b20 511 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 512 if (mlv == 0x81)
513 dacoffset ^= 8;
514 return 0x6808b0 + dacoffset;
515 } else {
df31ef4d 516 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 517 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
518 mlv);
519 return 0;
520 }
521 return pramdac_table[mlv];
522 }
523}
524
37383650 525static int
6ee73861
BS		 526init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
527 struct init_exec *iexec)
528{
529 /*
530 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
531 *
532 * offset (8 bit): opcode
533 * offset + 1 (16 bit): CRTC port
534 * offset + 3 (8 bit): CRTC index
535 * offset + 4 (8 bit): mask
536 * offset + 5 (8 bit): shift
537 * offset + 6 (8 bit): count
538 * offset + 7 (32 bit): register
539 * offset + 11 (32 bit): configuration 1
540 * ...
541 *
542 * Starting at offset + 11 there are "count" 32 bit values.
543 * To find out which value to use read index "CRTC index" on "CRTC
544 * port", AND this value with "mask" and then bit shift right "shift"
545 * bits. Read the appropriate value using this index and write to
546 * "register"
547 */
548
549 uint16_t crtcport = ROM16(bios->data[offset + 1]);
550 uint8_t crtcindex = bios->data[offset + 3];
551 uint8_t mask = bios->data[offset + 4];
552 uint8_t shift = bios->data[offset + 5];
553 uint8_t count = bios->data[offset + 6];
554 uint32_t reg = ROM32(bios->data[offset + 7]);
555 uint8_t config;
556 uint32_t configval;
37383650 557 int len = 11 + count * 4;
6ee73861
BS		 558
559 if (!iexec->execute)
37383650 560 return len;
6ee73861
BS		 561
562 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
563 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
564 offset, crtcport, crtcindex, mask, shift, count, reg);
565
566 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
567 if (config > count) {
568 NV_ERROR(bios->dev,
569 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
570 offset, config, count);
309b8c89 571 return len;
6ee73861
BS		 572 }
573
574 configval = ROM32(bios->data[offset + 11 + config * 4]);
575
576 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
577
578 bios_wr32(bios, reg, configval);
579
37383650 580 return len;
6ee73861
BS		 581}
582
37383650 583static int
6ee73861
BS		 584init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
585{
586 /*
587 * INIT_REPEAT opcode: 0x33 ('3')
588 *
589 * offset (8 bit): opcode
590 * offset + 1 (8 bit): count
591 *
592 * Execute script following this opcode up to INIT_REPEAT_END
593 * "count" times
594 */
595
596 uint8_t count = bios->data[offset + 1];
597 uint8_t i;
598
599 /* no iexec->execute check by design */
600
601 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
602 offset, count);
603
604 iexec->repeat = true;
605
606 /*
607 * count - 1, as the script block will execute once when we leave this
608 * opcode -- this is compatible with bios behaviour as:
609 * a) the block is always executed at least once, even if count == 0
610 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
611 * while we don't
612 */
613 for (i = 0; i < count - 1; i++)
614 parse_init_table(bios, offset + 2, iexec);
615
616 iexec->repeat = false;
617
37383650 618 return 2;
6ee73861
BS		 619}
620
37383650 621static int
6ee73861
BS		 622init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
623 struct init_exec *iexec)
624{
625 /*
626 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
627 *
628 * offset (8 bit): opcode
629 * offset + 1 (16 bit): CRTC port
630 * offset + 3 (8 bit): CRTC index
631 * offset + 4 (8 bit): mask
632 * offset + 5 (8 bit): shift
633 * offset + 6 (8 bit): IO flag condition index
634 * offset + 7 (8 bit): count
635 * offset + 8 (32 bit): register
636 * offset + 12 (16 bit): frequency 1
637 * ...
638 *
639 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
640 * Set PLL register "register" to coefficients for frequency n,
641 * selected by reading index "CRTC index" of "CRTC port" ANDed with
642 * "mask" and shifted right by "shift".
643 *
644 * If "IO flag condition index" > 0, and condition met, double
645 * frequency before setting it.
646 */
647
648 uint16_t crtcport = ROM16(bios->data[offset + 1]);
649 uint8_t crtcindex = bios->data[offset + 3];
650 uint8_t mask = bios->data[offset + 4];
651 uint8_t shift = bios->data[offset + 5];
652 int8_t io_flag_condition_idx = bios->data[offset + 6];
653 uint8_t count = bios->data[offset + 7];
654 uint32_t reg = ROM32(bios->data[offset + 8]);
655 uint8_t config;
656 uint16_t freq;
37383650 657 int len = 12 + count * 2;
6ee73861
BS		 658
659 if (!iexec->execute)
37383650 660 return len;
6ee73861
BS		 661
662 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
663 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
664 "Count: 0x%02X, Reg: 0x%08X\n",
665 offset, crtcport, crtcindex, mask, shift,
666 io_flag_condition_idx, count, reg);
667
668 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
669 if (config > count) {
670 NV_ERROR(bios->dev,
671 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
672 offset, config, count);
309b8c89 673 return len;
6ee73861
BS		 674 }
675
676 freq = ROM16(bios->data[offset + 12 + config * 2]);
677
678 if (io_flag_condition_idx > 0) {
679 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
680 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
681 "frequency doubled\n", offset);
682 freq *= 2;
683 } else
684 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
685 "frequency unchanged\n", offset);
686 }
687
688 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
689 offset, reg, config, freq);
690
70790f4f 691 setPLL(bios->dev, reg, freq * 10);
6ee73861 692
37383650 693 return len;
6ee73861
BS		 694}
695
37383650 696static int
6ee73861
BS		 697init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
698{
699 /*
700 * INIT_END_REPEAT opcode: 0x36 ('6')
701 *
702 * offset (8 bit): opcode
703 *
704 * Marks the end of the block for INIT_REPEAT to repeat
705 */
706
707 /* no iexec->execute check by design */
708
709 /*
710 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
711 * we're not in repeat mode
712 */
713 if (iexec->repeat)
37383650 714 return 0;
6ee73861 715
37383650 716 return 1;
6ee73861
BS		 717}
718
37383650 719static int
6ee73861
BS		 720init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
721{
722 /*
723 * INIT_COPY opcode: 0x37 ('7')
724 *
725 * offset (8 bit): opcode
726 * offset + 1 (32 bit): register
727 * offset + 5 (8 bit): shift
728 * offset + 6 (8 bit): srcmask
729 * offset + 7 (16 bit): CRTC port
730 * offset + 9 (8 bit): CRTC index
731 * offset + 10 (8 bit): mask
732 *
733 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
734 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
735 * port
736 */
737
738 uint32_t reg = ROM32(bios->data[offset + 1]);
739 uint8_t shift = bios->data[offset + 5];
740 uint8_t srcmask = bios->data[offset + 6];
741 uint16_t crtcport = ROM16(bios->data[offset + 7]);
742 uint8_t crtcindex = bios->data[offset + 9];
743 uint8_t mask = bios->data[offset + 10];
744 uint32_t data;
745 uint8_t crtcdata;
746
747 if (!iexec->execute)
37383650 748 return 11;
6ee73861
BS		 749
750 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
751 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
752 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
753
754 data = bios_rd32(bios, reg);
755
756 if (shift < 0x80)
757 data >>= shift;
758 else
759 data <<= (0x100 - shift);
760
761 data &= srcmask;
762
763 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
764 crtcdata |= (uint8_t)data;
765 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
766
37383650 767 return 11;
6ee73861
BS		 768}
769
37383650 770static int
6ee73861
BS		 771init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
772{
773 /*
774 * INIT_NOT opcode: 0x38 ('8')
775 *
776 * offset (8 bit): opcode
777 *
778 * Invert the current execute / no-execute condition (i.e. "else")
779 */
780 if (iexec->execute)
781 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
782 else
783 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
784
785 iexec->execute = !iexec->execute;
37383650 786 return 1;
6ee73861
BS		 787}
788
37383650 789static int
6ee73861
BS		 790init_io_flag_condition(struct nvbios *bios, uint16_t offset,
791 struct init_exec *iexec)
792{
793 /*
794 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
795 *
796 * offset (8 bit): opcode
797 * offset + 1 (8 bit): condition number
798 *
799 * Check condition "condition number" in the IO flag condition table.
800 * If condition not met skip subsequent opcodes until condition is
801 * inverted (INIT_NOT), or we hit INIT_RESUME
802 */
803
804 uint8_t cond = bios->data[offset + 1];
805
806 if (!iexec->execute)
37383650 807 return 2;
6ee73861
BS		 808
809 if (io_flag_condition_met(bios, offset, cond))
810 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
811 else {
812 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
813 iexec->execute = false;
814 }
815
37383650 816 return 2;
6ee73861
BS		 817}
818
25908b77
BS		 819static int
820init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
821{
822 /*
823 * INIT_DP_CONDITION opcode: 0x3A ('')
824 *
825 * offset (8 bit): opcode
826 * offset + 1 (8 bit): "sub" opcode
827 * offset + 2 (8 bit): unknown
828 *
829 */
830
25908b77
BS		 831 struct dcb_entry *dcb = bios->display.output;
832 struct drm_device *dev = bios->dev;
833 uint8_t cond = bios->data[offset + 1];
5f1800bd 834 uint8_t *table, *entry;
25908b77
BS		 835
836 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
837
838 if (!iexec->execute)
839 return 3;
840
5f1800bd
BS		 841 table = nouveau_dp_bios_data(dev, dcb, &entry);
842 if (!table)
309b8c89 843 return 3;
25908b77
BS		 844
845 switch (cond) {
846 case 0:
befb51e9
BS		 847 entry = dcb_conn(dev, dcb->connector);
848 if (!entry || entry[0] != DCB_CONNECTOR_eDP)
25908b77 849 iexec->execute = false;
25908b77
BS		 850 break;
851 case 1:
852 case 2:
65445992
BS		 853 if ((table[0] < 0x40 && !(entry[5] & cond)) ||
854 (table[0] == 0x40 && !(entry[4] & cond)))
25908b77
BS		 855 iexec->execute = false;
856 break;
857 case 5:
858 {
4196faa8 859 struct nouveau_i2c_port *auxch;
25908b77
BS		 860 int ret;
861
862 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
309b8c89
BS		 863 if (!auxch) {
864 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
865 return 3;
866 }
25908b77 867
4196faa8 868 ret = auxch_rd(dev, auxch, 0xd, &cond, 1);
309b8c89
BS		 869 if (ret) {
870 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
871 return 3;
872 }
25908b77 873
64d202b4 874 if (!(cond & 1))
25908b77
BS		 875 iexec->execute = false;
876 }
877 break;
878 default:
879 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
880 break;
881 }
882
883 if (iexec->execute)
884 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
885 else
886 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
887
888 return 3;
889}
890
891static int
892init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
893{
894 /*
895 * INIT_3B opcode: 0x3B ('')
896 *
897 * offset (8 bit): opcode
898 * offset + 1 (8 bit): crtc index
899 *
900 */
901
902 uint8_t or = ffs(bios->display.output->or) - 1;
903 uint8_t index = bios->data[offset + 1];
904 uint8_t data;
905
906 if (!iexec->execute)
907 return 2;
908
909 data = bios_idxprt_rd(bios, 0x3d4, index);
910 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
911 return 2;
912}
913
914static int
915init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
916{
917 /*
918 * INIT_3C opcode: 0x3C ('')
919 *
920 * offset (8 bit): opcode
921 * offset + 1 (8 bit): crtc index
922 *
923 */
924
925 uint8_t or = ffs(bios->display.output->or) - 1;
926 uint8_t index = bios->data[offset + 1];
927 uint8_t data;
928
929 if (!iexec->execute)
930 return 2;
931
932 data = bios_idxprt_rd(bios, 0x3d4, index);
933 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
934 return 2;
935}
936
37383650 937static int
6ee73861
BS		 938init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
939 struct init_exec *iexec)
940{
941 /*
942 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
943 *
944 * offset (8 bit): opcode
945 * offset + 1 (32 bit): control register
946 * offset + 5 (32 bit): data register
947 * offset + 9 (32 bit): mask
948 * offset + 13 (32 bit): data
949 * offset + 17 (8 bit): count
950 * offset + 18 (8 bit): address 1
951 * offset + 19 (8 bit): data 1
952 * ...
953 *
954 * For each of "count" address and data pairs, write "data n" to
955 * "data register", read the current value of "control register",
956 * and write it back once ANDed with "mask", ORed with "data",
957 * and ORed with "address n"
958 */
959
960 uint32_t controlreg = ROM32(bios->data[offset + 1]);
961 uint32_t datareg = ROM32(bios->data[offset + 5]);
962 uint32_t mask = ROM32(bios->data[offset + 9]);
963 uint32_t data = ROM32(bios->data[offset + 13]);
964 uint8_t count = bios->data[offset + 17];
37383650 965 int len = 18 + count * 2;
6ee73861
BS		 966 uint32_t value;
967 int i;
968
969 if (!iexec->execute)
37383650 970 return len;
6ee73861
BS		 971
972 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
973 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
974 offset, controlreg, datareg, mask, data, count);
975
976 for (i = 0; i < count; i++) {
977 uint8_t instaddress = bios->data[offset + 18 + i * 2];
978 uint8_t instdata = bios->data[offset + 19 + i * 2];
979
980 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
981 offset, instaddress, instdata);
982
983 bios_wr32(bios, datareg, instdata);
984 value = bios_rd32(bios, controlreg) & mask;
985 value |= data;
986 value |= instaddress;
987 bios_wr32(bios, controlreg, value);
988 }
989
37383650 990 return len;
6ee73861
BS		 991}
992
37383650 993static int
6ee73861
BS		 994init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
995 struct init_exec *iexec)
996{
997 /*
998 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
999 *
1000 * offset (8 bit): opcode
1001 * offset + 1 (16 bit): CRTC port
1002 * offset + 3 (8 bit): CRTC index
1003 * offset + 4 (8 bit): mask
1004 * offset + 5 (8 bit): shift
1005 * offset + 6 (8 bit): count
1006 * offset + 7 (32 bit): register
1007 * offset + 11 (32 bit): frequency 1
1008 * ...
1009 *
1010 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1011 * Set PLL register "register" to coefficients for frequency n,
1012 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1013 * "mask" and shifted right by "shift".
1014 */
1015
1016 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1017 uint8_t crtcindex = bios->data[offset + 3];
1018 uint8_t mask = bios->data[offset + 4];
1019 uint8_t shift = bios->data[offset + 5];
1020 uint8_t count = bios->data[offset + 6];
1021 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1022 int len = 11 + count * 4;
6ee73861
BS		 1023 uint8_t config;
1024 uint32_t freq;
1025
1026 if (!iexec->execute)
37383650 1027 return len;
6ee73861
BS		 1028
1029 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1030 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1031 offset, crtcport, crtcindex, mask, shift, count, reg);
1032
1033 if (!reg)
37383650 1034 return len;
6ee73861
BS		 1035
1036 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1037 if (config > count) {
1038 NV_ERROR(bios->dev,
1039 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1040 offset, config, count);
309b8c89 1041 return len;
6ee73861
BS		 1042 }
1043
1044 freq = ROM32(bios->data[offset + 11 + config * 4]);
1045
1046 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1047 offset, reg, config, freq);
1048
70790f4f 1049 setPLL(bios->dev, reg, freq);
6ee73861 1050
37383650 1051 return len;
6ee73861
BS		 1052}
1053
37383650 1054static int
6ee73861
BS		 1055init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1056{
1057 /*
1058 * INIT_PLL2 opcode: 0x4B ('K')
1059 *
1060 * offset (8 bit): opcode
1061 * offset + 1 (32 bit): register
1062 * offset + 5 (32 bit): freq
1063 *
1064 * Set PLL register "register" to coefficients for frequency "freq"
1065 */
1066
1067 uint32_t reg = ROM32(bios->data[offset + 1]);
1068 uint32_t freq = ROM32(bios->data[offset + 5]);
1069
1070 if (!iexec->execute)
37383650 1071 return 9;
6ee73861
BS		 1072
1073 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1074 offset, reg, freq);
1075
70790f4f 1076 setPLL(bios->dev, reg, freq);
37383650 1077 return 9;
6ee73861
BS		 1078}
1079
37383650 1080static int
6ee73861
BS		 1081init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1082{
1083 /*
1084 * INIT_I2C_BYTE opcode: 0x4C ('L')
1085 *
1086 * offset (8 bit): opcode
1087 * offset + 1 (8 bit): DCB I2C table entry index
1088 * offset + 2 (8 bit): I2C slave address
1089 * offset + 3 (8 bit): count
1090 * offset + 4 (8 bit): I2C register 1
1091 * offset + 5 (8 bit): mask 1
1092 * offset + 6 (8 bit): data 1
1093 * ...
1094 *
1095 * For each of "count" registers given by "I2C register n" on the device
1096 * addressed by "I2C slave address" on the I2C bus given by
1097 * "DCB I2C table entry index", read the register, AND the result with
1098 * "mask n" and OR it with "data n" before writing it back to the device
1099 */
1100
309b8c89 1101 struct drm_device *dev = bios->dev;
6ee73861 1102 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1103 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1104 uint8_t count = bios->data[offset + 3];
4196faa8 1105 struct nouveau_i2c_port *chan;
893887ed
BS		 1106 int len = 4 + count * 3;
1107 int ret, i;
6ee73861
BS		 1108
1109 if (!iexec->execute)
37383650 1110 return len;
6ee73861
BS		 1111
1112 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1113 "Count: 0x%02X\n",
1114 offset, i2c_index, i2c_address, count);
1115
309b8c89
BS		 1116 chan = init_i2c_device_find(dev, i2c_index);
1117 if (!chan) {
1118 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1119 return len;
1120 }
6ee73861
BS		 1121
1122 for (i = 0; i < count; i++) {
893887ed 1123 uint8_t reg = bios->data[offset + 4 + i * 3];
6ee73861
BS		 1124 uint8_t mask = bios->data[offset + 5 + i * 3];
1125 uint8_t data = bios->data[offset + 6 + i * 3];
893887ed 1126 union i2c_smbus_data val;
6ee73861 1127
4196faa8 1128 ret = i2c_smbus_xfer(nouveau_i2c_adapter(chan), i2c_address, 0,
893887ed
BS		 1129 I2C_SMBUS_READ, reg,
1130 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1131 if (ret < 0) {
1132 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1133 return len;
1134 }
6ee73861
BS		 1135
1136 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1137 "Mask: 0x%02X, Data: 0x%02X\n",
893887ed 1138 offset, reg, val.byte, mask, data);
6ee73861 1139
893887ed
BS		 1140 if (!bios->execute)
1141 continue;
6ee73861 1142
893887ed
BS		 1143 val.byte &= mask;
1144 val.byte |= data;
4196faa8 1145 ret = i2c_smbus_xfer(nouveau_i2c_adapter(chan), i2c_address, 0,
893887ed
BS		 1146 I2C_SMBUS_WRITE, reg,
1147 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1148 if (ret < 0) {
1149 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1150 return len;
1151 }
6ee73861
BS		 1152 }
1153
37383650 1154 return len;
6ee73861
BS		 1155}
1156
37383650 1157static int
6ee73861
BS		 1158init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1159{
1160 /*
1161 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1162 *
1163 * offset (8 bit): opcode
1164 * offset + 1 (8 bit): DCB I2C table entry index
1165 * offset + 2 (8 bit): I2C slave address
1166 * offset + 3 (8 bit): count
1167 * offset + 4 (8 bit): I2C register 1
1168 * offset + 5 (8 bit): data 1
1169 * ...
1170 *
1171 * For each of "count" registers given by "I2C register n" on the device
1172 * addressed by "I2C slave address" on the I2C bus given by
1173 * "DCB I2C table entry index", set the register to "data n"
1174 */
1175
309b8c89 1176 struct drm_device *dev = bios->dev;
6ee73861 1177 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1178 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1179 uint8_t count = bios->data[offset + 3];
4196faa8 1180 struct nouveau_i2c_port *chan;
893887ed
BS		 1181 int len = 4 + count * 2;
1182 int ret, i;
6ee73861
BS		 1183
1184 if (!iexec->execute)
37383650 1185 return len;
6ee73861
BS		 1186
1187 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1188 "Count: 0x%02X\n",
1189 offset, i2c_index, i2c_address, count);
1190
309b8c89
BS		 1191 chan = init_i2c_device_find(dev, i2c_index);
1192 if (!chan) {
1193 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1194 return len;
1195 }
6ee73861
BS		 1196
1197 for (i = 0; i < count; i++) {
893887ed
BS		 1198 uint8_t reg = bios->data[offset + 4 + i * 2];
1199 union i2c_smbus_data val;
1200
1201 val.byte = bios->data[offset + 5 + i * 2];
6ee73861
BS		 1202
1203 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
893887ed
BS		 1204 offset, reg, val.byte);
1205
1206 if (!bios->execute)
1207 continue;
1208
4196faa8 1209 ret = i2c_smbus_xfer(nouveau_i2c_adapter(chan), i2c_address, 0,
893887ed
BS		 1210 I2C_SMBUS_WRITE, reg,
1211 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1212 if (ret < 0) {
1213 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1214 return len;
1215 }
6ee73861
BS		 1216 }
1217
37383650 1218 return len;
6ee73861
BS		 1219}
1220
37383650 1221static int
6ee73861
BS		 1222init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1223{
1224 /*
1225 * INIT_ZM_I2C opcode: 0x4E ('N')
1226 *
1227 * offset (8 bit): opcode
1228 * offset + 1 (8 bit): DCB I2C table entry index
1229 * offset + 2 (8 bit): I2C slave address
1230 * offset + 3 (8 bit): count
1231 * offset + 4 (8 bit): data 1
1232 * ...
1233 *
1234 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1235 * address" on the I2C bus given by "DCB I2C table entry index"
1236 */
1237
309b8c89 1238 struct drm_device *dev = bios->dev;
6ee73861 1239 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1240 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1241 uint8_t count = bios->data[offset + 3];
37383650 1242 int len = 4 + count;
4196faa8 1243 struct nouveau_i2c_port *chan;
6ee73861
BS		 1244 struct i2c_msg msg;
1245 uint8_t data[256];
309b8c89 1246 int ret, i;
6ee73861
BS		 1247
1248 if (!iexec->execute)
37383650 1249 return len;
6ee73861
BS		 1250
1251 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1252 "Count: 0x%02X\n",
1253 offset, i2c_index, i2c_address, count);
1254
309b8c89
BS		 1255 chan = init_i2c_device_find(dev, i2c_index);
1256 if (!chan) {
1257 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1258 return len;
1259 }
6ee73861
BS		 1260
1261 for (i = 0; i < count; i++) {
1262 data[i] = bios->data[offset + 4 + i];
1263
1264 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1265 }
1266
1267 if (bios->execute) {
1268 msg.addr = i2c_address;
1269 msg.flags = 0;
1270 msg.len = count;
1271 msg.buf = data;
4196faa8 1272 ret = i2c_transfer(nouveau_i2c_adapter(chan), &msg, 1);
309b8c89
BS		 1273 if (ret != 1) {
1274 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1275 return len;
1276 }
6ee73861
BS		 1277 }
1278
37383650 1279 return len;
6ee73861
BS		 1280}
1281
37383650 1282static int
6ee73861
BS		 1283init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1284{
1285 /*
1286 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1287 *
1288 * offset (8 bit): opcode
1289 * offset + 1 (8 bit): magic lookup value
1290 * offset + 2 (8 bit): TMDS address
1291 * offset + 3 (8 bit): mask
1292 * offset + 4 (8 bit): data
1293 *
1294 * Read the data reg for TMDS address "TMDS address", AND it with mask
1295 * and OR it with data, then write it back
1296 * "magic lookup value" determines which TMDS base address register is
1297 * used -- see get_tmds_index_reg()
1298 */
1299
309b8c89 1300 struct drm_device *dev = bios->dev;
6ee73861
BS		 1301 uint8_t mlv = bios->data[offset + 1];
1302 uint32_t tmdsaddr = bios->data[offset + 2];
1303 uint8_t mask = bios->data[offset + 3];
1304 uint8_t data = bios->data[offset + 4];
1305 uint32_t reg, value;
1306
1307 if (!iexec->execute)
37383650 1308 return 5;
6ee73861
BS		 1309
1310 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1311 "Mask: 0x%02X, Data: 0x%02X\n",
1312 offset, mlv, tmdsaddr, mask, data);
1313
1314 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1315 if (!reg) {
1316 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1317 return 5;
1318 }
6ee73861
BS		 1319
1320 bios_wr32(bios, reg,
1321 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1322 value = (bios_rd32(bios, reg + 4) & mask) | data;
1323 bios_wr32(bios, reg + 4, value);
1324 bios_wr32(bios, reg, tmdsaddr);
1325
37383650 1326 return 5;
6ee73861
BS		 1327}
1328
37383650 1329static int
6ee73861
BS		 1330init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1331 struct init_exec *iexec)
1332{
1333 /*
1334 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1335 *
1336 * offset (8 bit): opcode
1337 * offset + 1 (8 bit): magic lookup value
1338 * offset + 2 (8 bit): count
1339 * offset + 3 (8 bit): addr 1
1340 * offset + 4 (8 bit): data 1
1341 * ...
1342 *
1343 * For each of "count" TMDS address and data pairs write "data n" to
1344 * "addr n". "magic lookup value" determines which TMDS base address
1345 * register is used -- see get_tmds_index_reg()
1346 */
1347
309b8c89 1348 struct drm_device *dev = bios->dev;
6ee73861
BS		 1349 uint8_t mlv = bios->data[offset + 1];
1350 uint8_t count = bios->data[offset + 2];
37383650 1351 int len = 3 + count * 2;
6ee73861
BS		 1352 uint32_t reg;
1353 int i;
1354
1355 if (!iexec->execute)
37383650 1356 return len;
6ee73861
BS		 1357
1358 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1359 offset, mlv, count);
1360
1361 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1362 if (!reg) {
1363 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1364 return len;
1365 }
6ee73861
BS		 1366
1367 for (i = 0; i < count; i++) {
1368 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1369 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1370
1371 bios_wr32(bios, reg + 4, tmdsdata);
1372 bios_wr32(bios, reg, tmdsaddr);
1373 }
1374
37383650 1375 return len;
6ee73861
BS		 1376}
1377
37383650 1378static int
6ee73861
BS		 1379init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1380 struct init_exec *iexec)
1381{
1382 /*
1383 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1384 *
1385 * offset (8 bit): opcode
1386 * offset + 1 (8 bit): CRTC index1
1387 * offset + 2 (8 bit): CRTC index2
1388 * offset + 3 (8 bit): baseaddr
1389 * offset + 4 (8 bit): count
1390 * offset + 5 (8 bit): data 1
1391 * ...
1392 *
1393 * For each of "count" address and data pairs, write "baseaddr + n" to
1394 * "CRTC index1" and "data n" to "CRTC index2"
1395 * Once complete, restore initial value read from "CRTC index1"
1396 */
1397 uint8_t crtcindex1 = bios->data[offset + 1];
1398 uint8_t crtcindex2 = bios->data[offset + 2];
1399 uint8_t baseaddr = bios->data[offset + 3];
1400 uint8_t count = bios->data[offset + 4];
37383650 1401 int len = 5 + count;
6ee73861
BS		 1402 uint8_t oldaddr, data;
1403 int i;
1404
1405 if (!iexec->execute)
37383650 1406 return len;
6ee73861
BS		 1407
1408 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1409 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1410 offset, crtcindex1, crtcindex2, baseaddr, count);
1411
1412 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1413
1414 for (i = 0; i < count; i++) {
1415 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1416 baseaddr + i);
1417 data = bios->data[offset + 5 + i];
1418 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1419 }
1420
1421 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1422
37383650 1423 return len;
6ee73861
BS		 1424}
1425
37383650 1426static int
6ee73861
BS		 1427init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1428{
1429 /*
1430 * INIT_CR opcode: 0x52 ('R')
1431 *
1432 * offset (8 bit): opcode
1433 * offset + 1 (8 bit): CRTC index
1434 * offset + 2 (8 bit): mask
1435 * offset + 3 (8 bit): data
1436 *
1437 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1438 * data back to "CRTC index"
1439 */
1440
1441 uint8_t crtcindex = bios->data[offset + 1];
1442 uint8_t mask = bios->data[offset + 2];
1443 uint8_t data = bios->data[offset + 3];
1444 uint8_t value;
1445
1446 if (!iexec->execute)
37383650 1447 return 4;
6ee73861
BS		 1448
1449 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1450 offset, crtcindex, mask, data);
1451
1452 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1453 value |= data;
1454 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1455
37383650 1456 return 4;
6ee73861
BS		 1457}
1458
37383650 1459static int
6ee73861
BS		 1460init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1461{
1462 /*
1463 * INIT_ZM_CR opcode: 0x53 ('S')
1464 *
1465 * offset (8 bit): opcode
1466 * offset + 1 (8 bit): CRTC index
1467 * offset + 2 (8 bit): value
1468 *
1469 * Assign "value" to CRTC register with index "CRTC index".
1470 */
1471
1472 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1473 uint8_t data = bios->data[offset + 2];
1474
1475 if (!iexec->execute)
37383650 1476 return 3;
6ee73861
BS		 1477
1478 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1479
37383650 1480 return 3;
6ee73861
BS		 1481}
1482
37383650 1483static int
6ee73861
BS		 1484init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1485{
1486 /*
1487 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1488 *
1489 * offset (8 bit): opcode
1490 * offset + 1 (8 bit): count
1491 * offset + 2 (8 bit): CRTC index 1
1492 * offset + 3 (8 bit): value 1
1493 * ...
1494 *
1495 * For "count", assign "value n" to CRTC register with index
1496 * "CRTC index n".
1497 */
1498
1499 uint8_t count = bios->data[offset + 1];
37383650 1500 int len = 2 + count * 2;
6ee73861
BS		 1501 int i;
1502
1503 if (!iexec->execute)
37383650 1504 return len;
6ee73861
BS		 1505
1506 for (i = 0; i < count; i++)
1507 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1508
37383650 1509 return len;
6ee73861
BS		 1510}
1511
37383650 1512static int
6ee73861
BS		 1513init_condition_time(struct nvbios *bios, uint16_t offset,
1514 struct init_exec *iexec)
1515{
1516 /*
1517 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1518 *
1519 * offset (8 bit): opcode
1520 * offset + 1 (8 bit): condition number
1521 * offset + 2 (8 bit): retries / 50
1522 *
1523 * Check condition "condition number" in the condition table.
1524 * Bios code then sleeps for 2ms if the condition is not met, and
1525 * repeats up to "retries" times, but on one C51 this has proved
1526 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1527 * this, and bail after "retries" times, or 2s, whichever is less.
1528 * If still not met after retries, clear execution flag for this table.
1529 */
1530
1531 uint8_t cond = bios->data[offset + 1];
1532 uint16_t retries = bios->data[offset + 2] * 50;
1533 unsigned cnt;
1534
1535 if (!iexec->execute)
37383650 1536 return 3;
6ee73861
BS		 1537
1538 if (retries > 100)
1539 retries = 100;
1540
1541 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1542 offset, cond, retries);
1543
1544 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1545 retries = 1;
1546
1547 for (cnt = 0; cnt < retries; cnt++) {
1548 if (bios_condition_met(bios, offset, cond)) {
1549 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1550 offset);
1551 break;
1552 } else {
1553 BIOSLOG(bios, "0x%04X: "
1554 "Condition not met, sleeping for 20ms\n",
1555 offset);
c7ca4d1b 1556 mdelay(20);
6ee73861
BS		 1557 }
1558 }
1559
1560 if (!bios_condition_met(bios, offset, cond)) {
1561 NV_WARN(bios->dev,
1562 "0x%04X: Condition still not met after %dms, "
1563 "skipping following opcodes\n", offset, 20 * retries);
1564 iexec->execute = false;
1565 }
1566
37383650 1567 return 3;
6ee73861
BS		 1568}
1569
e3a1924f
MK		 1570static int
1571init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1572{
1573 /*
1574 * INIT_LTIME opcode: 0x57 ('V')
1575 *
1576 * offset (8 bit): opcode
1577 * offset + 1 (16 bit): time
1578 *
e8a8b252 1579 * Sleep for "time" milliseconds.
e3a1924f
MK		 1580 */
1581
1582 unsigned time = ROM16(bios->data[offset + 1]);
1583
1584 if (!iexec->execute)
1585 return 3;
1586
e8a8b252 1587 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
e3a1924f
MK		 1588 offset, time);
1589
c7ca4d1b 1590 mdelay(time);
e3a1924f
MK		 1591
1592 return 3;
1593}
1594
37383650 1595static int
6ee73861
BS		 1596init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1597 struct init_exec *iexec)
1598{
1599 /*
1600 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1601 *
1602 * offset (8 bit): opcode
1603 * offset + 1 (32 bit): base register
1604 * offset + 5 (8 bit): count
1605 * offset + 6 (32 bit): value 1
1606 * ...
1607 *
1608 * Starting at offset + 6 there are "count" 32 bit values.
1609 * For "count" iterations set "base register" + 4 * current_iteration
1610 * to "value current_iteration"
1611 */
1612
1613 uint32_t basereg = ROM32(bios->data[offset + 1]);
1614 uint32_t count = bios->data[offset + 5];
37383650 1615 int len = 6 + count * 4;
6ee73861
BS		 1616 int i;
1617
1618 if (!iexec->execute)
37383650 1619 return len;
6ee73861
BS		 1620
1621 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1622 offset, basereg, count);
1623
1624 for (i = 0; i < count; i++) {
1625 uint32_t reg = basereg + i * 4;
1626 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1627
1628 bios_wr32(bios, reg, data);
1629 }
1630
37383650 1631 return len;
6ee73861
BS		 1632}
1633
37383650 1634static int
6ee73861
BS		 1635init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1636{
1637 /*
1638 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1639 *
1640 * offset (8 bit): opcode
1641 * offset + 1 (16 bit): subroutine offset (in bios)
1642 *
1643 * Calls a subroutine that will execute commands until INIT_DONE
1644 * is found.
1645 */
1646
1647 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1648
1649 if (!iexec->execute)
37383650 1650 return 3;
6ee73861
BS		 1651
1652 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1653 offset, sub_offset);
1654
1655 parse_init_table(bios, sub_offset, iexec);
1656
1657 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1658
37383650 1659 return 3;
6ee73861
BS		 1660}
1661
ec64a408
BS		 1662static int
1663init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1664{
1665 /*
1666 * INIT_JUMP opcode: 0x5C ('\')
1667 *
1668 * offset (8 bit): opcode
1669 * offset + 1 (16 bit): offset (in bios)
1670 *
1671 * Continue execution of init table from 'offset'
1672 */
1673
1674 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
1675
1676 if (!iexec->execute)
1677 return 3;
1678
1679 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
1680 return jmp_offset - offset;
1681}
1682
b715d640
MK		 1683static int
1684init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1685{
1686 /*
1687 * INIT_I2C_IF opcode: 0x5E ('^')
1688 *
1689 * offset (8 bit): opcode
1690 * offset + 1 (8 bit): DCB I2C table entry index
1691 * offset + 2 (8 bit): I2C slave address
1692 * offset + 3 (8 bit): I2C register
1693 * offset + 4 (8 bit): mask
1694 * offset + 5 (8 bit): data
1695 *
1696 * Read the register given by "I2C register" on the device addressed
1697 * by "I2C slave address" on the I2C bus given by "DCB I2C table
1698 * entry index". Compare the result AND "mask" to "data".
1699 * If they're not equal, skip subsequent opcodes until condition is
1700 * inverted (INIT_NOT), or we hit INIT_RESUME
1701 */
1702
1703 uint8_t i2c_index = bios->data[offset + 1];
1704 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1705 uint8_t reg = bios->data[offset + 3];
1706 uint8_t mask = bios->data[offset + 4];
1707 uint8_t data = bios->data[offset + 5];
4196faa8 1708 struct nouveau_i2c_port *chan;
b715d640
MK		 1709 union i2c_smbus_data val;
1710 int ret;
1711
1712 /* no execute check by design */
1713
1714 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
1715 offset, i2c_index, i2c_address);
1716
1717 chan = init_i2c_device_find(bios->dev, i2c_index);
1718 if (!chan)
1719 return -ENODEV;
1720
4196faa8 1721 ret = i2c_smbus_xfer(nouveau_i2c_adapter(chan), i2c_address, 0,
b715d640
MK		 1722 I2C_SMBUS_READ, reg,
1723 I2C_SMBUS_BYTE_DATA, &val);
1724 if (ret < 0) {
1725 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
1726 "Mask: 0x%02X, Data: 0x%02X\n",
1727 offset, reg, mask, data);
1728 iexec->execute = 0;
1729 return 6;
1730 }
1731
1732 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1733 "Mask: 0x%02X, Data: 0x%02X\n",
1734 offset, reg, val.byte, mask, data);
1735
1736 iexec->execute = ((val.byte & mask) == data);
1737
1738 return 6;
1739}
1740
37383650 1741static int
6ee73861
BS		 1742init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1743{
1744 /*
1745 * INIT_COPY_NV_REG opcode: 0x5F ('_')
1746 *
1747 * offset (8 bit): opcode
1748 * offset + 1 (32 bit): src reg
1749 * offset + 5 (8 bit): shift
1750 * offset + 6 (32 bit): src mask
1751 * offset + 10 (32 bit): xor
1752 * offset + 14 (32 bit): dst reg
1753 * offset + 18 (32 bit): dst mask
1754 *
1755 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
1756 * "src mask", then XOR with "xor". Write this OR'd with
1757 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
1758 */
1759
1760 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
1761 uint8_t shift = bios->data[offset + 5];
1762 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
1763 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
1764 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
1765 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
1766 uint32_t srcvalue, dstvalue;
1767
1768 if (!iexec->execute)
37383650 1769 return 22;
6ee73861
BS		 1770
1771 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
1772 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
1773 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
1774
1775 srcvalue = bios_rd32(bios, srcreg);
1776
1777 if (shift < 0x80)
1778 srcvalue >>= shift;
1779 else
1780 srcvalue <<= (0x100 - shift);
1781
1782 srcvalue = (srcvalue & srcmask) ^ xor;
1783
1784 dstvalue = bios_rd32(bios, dstreg) & dstmask;
1785
1786 bios_wr32(bios, dstreg, dstvalue | srcvalue);
1787
37383650 1788 return 22;
6ee73861
BS		 1789}
1790
37383650 1791static int
6ee73861
BS		 1792init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1793{
1794 /*
1795 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
1796 *
1797 * offset (8 bit): opcode
1798 * offset + 1 (16 bit): CRTC port
1799 * offset + 3 (8 bit): CRTC index
1800 * offset + 4 (8 bit): data
1801 *
1802 * Write "data" to index "CRTC index" of "CRTC port"
1803 */
1804 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1805 uint8_t crtcindex = bios->data[offset + 3];
1806 uint8_t data = bios->data[offset + 4];
1807
1808 if (!iexec->execute)
37383650 1809 return 5;
6ee73861
BS		 1810
1811 bios_idxprt_wr(bios, crtcport, crtcindex, data);
1812
37383650 1813 return 5;
6ee73861
BS		 1814}
1815
67eda20e
FJ		 1816static inline void
1817bios_md32(struct nvbios *bios, uint32_t reg,
1818 uint32_t mask, uint32_t val)
1819{
1820 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
1821}
1822
1823static uint32_t
1824peek_fb(struct drm_device *dev, struct io_mapping *fb,
1825 uint32_t off)
1826{
1827 uint32_t val = 0;
1828
1829 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 1830 uint8_t __iomem *p =
3e4d3af5 1831 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 1832
0bf9b0e0 1833 val = ioread32(p + (off & ~PAGE_MASK));
67eda20e 1834
3e4d3af5 1835 io_mapping_unmap_atomic(p);
67eda20e
FJ		 1836 }
1837
1838 return val;
1839}
1840
1841static void
1842poke_fb(struct drm_device *dev, struct io_mapping *fb,
1843 uint32_t off, uint32_t val)
1844{
1845 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 1846 uint8_t __iomem *p =
3e4d3af5 1847 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 1848
0bf9b0e0 1849 iowrite32(val, p + (off & ~PAGE_MASK));
67eda20e
FJ		 1850 wmb();
1851
3e4d3af5 1852 io_mapping_unmap_atomic(p);
67eda20e
FJ		 1853 }
1854}
1855
1856static inline bool
1857read_back_fb(struct drm_device *dev, struct io_mapping *fb,
1858 uint32_t off, uint32_t val)
1859{
1860 poke_fb(dev, fb, off, val);
1861 return val == peek_fb(dev, fb, off);
1862}
1863
1864static int
1865nv04_init_compute_mem(struct nvbios *bios)
1866{
1867 struct drm_device *dev = bios->dev;
1868 uint32_t patt = 0xdeadbeef;
1869 struct io_mapping *fb;
1870 int i;
1871
1872 /* Map the framebuffer aperture */
1873 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
1874 pci_resource_len(dev->pdev, 1));
1875 if (!fb)
1876 return -ENOMEM;
1877
1878 /* Sequencer and refresh off */
1879 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
1880 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
1881
1882 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
1883 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
1884 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
1885 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
1886
1887 for (i = 0; i < 4; i++)
1888 poke_fb(dev, fb, 4 * i, patt);
1889
1890 poke_fb(dev, fb, 0x400000, patt + 1);
1891
1892 if (peek_fb(dev, fb, 0) == patt + 1) {
1893 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
1894 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
1895 bios_md32(bios, NV04_PFB_DEBUG_0,
1896 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
1897
1898 for (i = 0; i < 4; i++)
1899 poke_fb(dev, fb, 4 * i, patt);
1900
1901 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
1902 bios_md32(bios, NV04_PFB_BOOT_0,
1903 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
1904 NV04_PFB_BOOT_0_RAM_AMOUNT,
1905 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
1906
1907 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
1908 (patt & 0xffff0000)) {
1909 bios_md32(bios, NV04_PFB_BOOT_0,
1910 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
1911 NV04_PFB_BOOT_0_RAM_AMOUNT,
1912 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
1913
0746b5da 1914 } else if (peek_fb(dev, fb, 0) != patt) {
67eda20e
FJ		 1915 if (read_back_fb(dev, fb, 0x800000, patt))
1916 bios_md32(bios, NV04_PFB_BOOT_0,
1917 NV04_PFB_BOOT_0_RAM_AMOUNT,
1918 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
1919 else
1920 bios_md32(bios, NV04_PFB_BOOT_0,
1921 NV04_PFB_BOOT_0_RAM_AMOUNT,
1922 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
1923
1924 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
1925 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
1926
1927 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
1928 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
1929 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
1930
1931 }
1932
1933 /* Refresh on, sequencer on */
1934 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
1935 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
1936
1937 io_mapping_free(fb);
1938 return 0;
1939}
1940
1941static const uint8_t *
1942nv05_memory_config(struct nvbios *bios)
1943{
1944 /* Defaults for BIOSes lacking a memory config table */
1945 static const uint8_t default_config_tab[][2] = {
1946 { 0x24, 0x00 },
1947 { 0x28, 0x00 },
1948 { 0x24, 0x01 },
1949 { 0x1f, 0x00 },
1950 { 0x0f, 0x00 },
1951 { 0x17, 0x00 },
1952 { 0x06, 0x00 },
1953 { 0x00, 0x00 }
1954 };
1955 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
1956 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
1957
1958 if (bios->legacy.mem_init_tbl_ptr)
1959 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
1960 else
1961 return default_config_tab[i];
1962}
1963
1964static int
1965nv05_init_compute_mem(struct nvbios *bios)
1966{
1967 struct drm_device *dev = bios->dev;
1968 const uint8_t *ramcfg = nv05_memory_config(bios);
1969 uint32_t patt = 0xdeadbeef;
1970 struct io_mapping *fb;
1971 int i, v;
1972
1973 /* Map the framebuffer aperture */
1974 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
1975 pci_resource_len(dev->pdev, 1));
1976 if (!fb)
1977 return -ENOMEM;
1978
1979 /* Sequencer off */
1980 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
1981
1982 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
1983 goto out;
1984
1985 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
1986
1987 /* If present load the hardcoded scrambling table */
1988 if (bios->legacy.mem_init_tbl_ptr) {
1989 uint32_t *scramble_tab = (uint32_t *)&bios->data[
1990 bios->legacy.mem_init_tbl_ptr + 0x10];
1991
1992 for (i = 0; i < 8; i++)
1993 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
1994 ROM32(scramble_tab[i]));
1995 }
1996
1997 /* Set memory type/width/length defaults depending on the straps */
1998 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
1999
2000 if (ramcfg[1] & 0x80)
2001 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2002
2003 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2004 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2005
2006 /* Probe memory bus width */
2007 for (i = 0; i < 4; i++)
2008 poke_fb(dev, fb, 4 * i, patt);
2009
2010 if (peek_fb(dev, fb, 0xc) != patt)
2011 bios_md32(bios, NV04_PFB_BOOT_0,
2012 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2013
2014 /* Probe memory length */
2015 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2016
2017 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2018 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2019 !read_back_fb(dev, fb, 0, ++patt)))
2020 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2021 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2022
2023 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2024 !read_back_fb(dev, fb, 0x800000, ++patt))
2025 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2026 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2027
2028 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2029 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2030 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2031
2032out:
2033 /* Sequencer on */
2034 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2035
2036 io_mapping_free(fb);
2037 return 0;
2038}
2039
2040static int
2041nv10_init_compute_mem(struct nvbios *bios)
2042{
2043 struct drm_device *dev = bios->dev;
2044 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2045 const int mem_width[] = { 0x10, 0x00, 0x20 };
2046 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2047 uint32_t patt = 0xdeadbeef;
2048 struct io_mapping *fb;
2049 int i, j, k;
2050
2051 /* Map the framebuffer aperture */
2052 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2053 pci_resource_len(dev->pdev, 1));
2054 if (!fb)
2055 return -ENOMEM;
2056
2057 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2058
2059 /* Probe memory bus width */
2060 for (i = 0; i < mem_width_count; i++) {
2061 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2062
2063 for (j = 0; j < 4; j++) {
2064 for (k = 0; k < 4; k++)
2065 poke_fb(dev, fb, 0x1c, 0);
2066
2067 poke_fb(dev, fb, 0x1c, patt);
2068 poke_fb(dev, fb, 0x3c, 0);
2069
2070 if (peek_fb(dev, fb, 0x1c) == patt)
2071 goto mem_width_found;
2072 }
2073 }
2074
2075mem_width_found:
2076 patt <<= 1;
2077
2078 /* Probe amount of installed memory */
2079 for (i = 0; i < 4; i++) {
2080 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2081
2082 poke_fb(dev, fb, off, patt);
2083 poke_fb(dev, fb, 0, 0);
2084
2085 peek_fb(dev, fb, 0);
2086 peek_fb(dev, fb, 0);
2087 peek_fb(dev, fb, 0);
2088 peek_fb(dev, fb, 0);
2089
2090 if (peek_fb(dev, fb, off) == patt)
2091 goto amount_found;
2092 }
2093
2094 /* IC missing - disable the upper half memory space. */
2095 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2096
2097amount_found:
2098 io_mapping_free(fb);
2099 return 0;
2100}
2101
2102static int
2103nv20_init_compute_mem(struct nvbios *bios)
2104{
2105 struct drm_device *dev = bios->dev;
2106 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2107 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2108 uint32_t amount, off;
2109 struct io_mapping *fb;
2110
2111 /* Map the framebuffer aperture */
2112 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2113 pci_resource_len(dev->pdev, 1));
2114 if (!fb)
2115 return -ENOMEM;
2116
2117 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2118
2119 /* Allow full addressing */
2120 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2121
2122 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2123 for (off = amount; off > 0x2000000; off -= 0x2000000)
2124 poke_fb(dev, fb, off - 4, off);
2125
2126 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2127 if (amount != peek_fb(dev, fb, amount - 4))
2128 /* IC missing - disable the upper half memory space. */
2129 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2130
2131 io_mapping_free(fb);
2132 return 0;
2133}
2134
37383650 2135static int
6ee73861
BS		 2136init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2137{
2138 /*
2139 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2140 *
2141 * offset (8 bit): opcode
2142 *
67eda20e
FJ		 2143 * This opcode is meant to set the PFB memory config registers
2144 * appropriately so that we can correctly calculate how much VRAM it
2145 * has (on nv10 and better chipsets the amount of installed VRAM is
2146 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
6ee73861 2147 *
67eda20e
FJ		 2148 * The implementation of this opcode in general consists of several
2149 * parts:
6ee73861 2150 *
67eda20e
FJ		 2151 * 1) Determination of memory type and density. Only necessary for
2152 * really old chipsets, the memory type reported by the strap bits
2153 * (0x101000) is assumed to be accurate on nv05 and newer.
6ee73861 2154 *
67eda20e
FJ		 2155 * 2) Determination of the memory bus width. Usually done by a cunning
2156 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2157 * seeing whether the written values are read back correctly.
6ee73861 2158 *
67eda20e
FJ		 2159 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2160 * trust the straps.
6ee73861 2161 *
67eda20e
FJ		 2162 * 3) Determination of how many of the card's RAM pads have ICs
2163 * attached, usually done by a cunning combination of writes to an
2164 * offset slightly less than the maximum memory reported by
2165 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
6ee73861 2166 *
67eda20e
FJ		 2167 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2168 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2169 * card show nothing being done for this opcode. Why is it still listed
2170 * in the table?!
6ee73861
BS		 2171 */
2172
2173 /* no iexec->execute check by design */
2174
6ee73861 2175 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
67eda20e 2176 int ret;
6ee73861 2177
67eda20e
FJ		 2178 if (dev_priv->chipset >= 0x40 ||
2179 dev_priv->chipset == 0x1a ||
2180 dev_priv->chipset == 0x1f)
2181 ret = 0;
2182 else if (dev_priv->chipset >= 0x20 &&
2183 dev_priv->chipset != 0x34)
2184 ret = nv20_init_compute_mem(bios);
2185 else if (dev_priv->chipset >= 0x10)
2186 ret = nv10_init_compute_mem(bios);
2187 else if (dev_priv->chipset >= 0x5)
2188 ret = nv05_init_compute_mem(bios);
2189 else
2190 ret = nv04_init_compute_mem(bios);
6ee73861 2191
67eda20e
FJ		 2192 if (ret)
2193 return ret;
6ee73861 2194
37383650 2195 return 1;
6ee73861
BS		 2196}
2197
37383650 2198static int
6ee73861
BS		 2199init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2200{
2201 /*
2202 * INIT_RESET opcode: 0x65 ('e')
2203 *
2204 * offset (8 bit): opcode
2205 * offset + 1 (32 bit): register
2206 * offset + 5 (32 bit): value1
2207 * offset + 9 (32 bit): value2
2208 *
2209 * Assign "value1" to "register", then assign "value2" to "register"
2210 */
2211
2212 uint32_t reg = ROM32(bios->data[offset + 1]);
2213 uint32_t value1 = ROM32(bios->data[offset + 5]);
2214 uint32_t value2 = ROM32(bios->data[offset + 9]);
2215 uint32_t pci_nv_19, pci_nv_20;
2216
2217 /* no iexec->execute check by design */
2218
2219 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
190a4378
FJ		 2220 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2221
6ee73861
BS		 2222 bios_wr32(bios, reg, value1);
2223
2224 udelay(10);
2225
2226 bios_wr32(bios, reg, value2);
2227 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2228
2229 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2230 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2231 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2232
37383650 2233 return 13;
6ee73861
BS		 2234}
2235
37383650 2236static int
6ee73861
BS		 2237init_configure_mem(struct nvbios *bios, uint16_t offset,
2238 struct init_exec *iexec)
2239{
2240 /*
2241 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2242 *
2243 * offset (8 bit): opcode
2244 *
2245 * Equivalent to INIT_DONE on bios version 3 or greater.
2246 * For early bios versions, sets up the memory registers, using values
2247 * taken from the memory init table
2248 */
2249
2250 /* no iexec->execute check by design */
2251
2252 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2253 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2254 uint32_t reg, data;
2255
2256 if (bios->major_version > 2)
ae55321c 2257 return 0;
6ee73861
BS		 2258
2259 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2260 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2261
2262 if (bios->data[meminitoffs] & 1)
2263 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2264
2265 for (reg = ROM32(bios->data[seqtbloffs]);
2266 reg != 0xffffffff;
2267 reg = ROM32(bios->data[seqtbloffs += 4])) {
2268
2269 switch (reg) {
3c7066bc
FJ		 2270 case NV04_PFB_PRE:
2271 data = NV04_PFB_PRE_CMD_PRECHARGE;
6ee73861 2272 break;
3c7066bc
FJ		 2273 case NV04_PFB_PAD:
2274 data = NV04_PFB_PAD_CKE_NORMAL;
6ee73861 2275 break;
3c7066bc
FJ		 2276 case NV04_PFB_REF:
2277 data = NV04_PFB_REF_CMD_REFRESH;
6ee73861
BS		 2278 break;
2279 default:
2280 data = ROM32(bios->data[meminitdata]);
2281 meminitdata += 4;
2282 if (data == 0xffffffff)
2283 continue;
2284 }
2285
2286 bios_wr32(bios, reg, data);
2287 }
2288
37383650 2289 return 1;
6ee73861
BS		 2290}
2291
37383650 2292static int
6ee73861
BS		 2293init_configure_clk(struct nvbios *bios, uint16_t offset,
2294 struct init_exec *iexec)
2295{
2296 /*
2297 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2298 *
2299 * offset (8 bit): opcode
2300 *
2301 * Equivalent to INIT_DONE on bios version 3 or greater.
2302 * For early bios versions, sets up the NVClk and MClk PLLs, using
2303 * values taken from the memory init table
2304 */
2305
2306 /* no iexec->execute check by design */
2307
2308 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2309 int clock;
2310
2311 if (bios->major_version > 2)
ae55321c 2312 return 0;
6ee73861
BS		 2313
2314 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
70790f4f 2315 setPLL(bios->dev, NV_PRAMDAC_NVPLL_COEFF, clock);
6ee73861
BS		 2316
2317 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2318 if (bios->data[meminitoffs] & 1) /* DDR */
2319 clock *= 2;
70790f4f 2320 setPLL(bios->dev, NV_PRAMDAC_MPLL_COEFF, clock);
6ee73861 2321
37383650 2322 return 1;
6ee73861
BS		 2323}
2324
37383650 2325static int
6ee73861
BS		 2326init_configure_preinit(struct nvbios *bios, uint16_t offset,
2327 struct init_exec *iexec)
2328{
2329 /*
2330 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2331 *
2332 * offset (8 bit): opcode
2333 *
2334 * Equivalent to INIT_DONE on bios version 3 or greater.
2335 * For early bios versions, does early init, loading ram and crystal
2336 * configuration from straps into CR3C
2337 */
2338
2339 /* no iexec->execute check by design */
2340
2341 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
3c9b2534 2342 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
6ee73861
BS		 2343
2344 if (bios->major_version > 2)
ae55321c 2345 return 0;
6ee73861
BS		 2346
2347 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2348 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2349
37383650 2350 return 1;
6ee73861
BS		 2351}
2352
37383650 2353static int
6ee73861
BS		 2354init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2355{
2356 /*
2357 * INIT_IO opcode: 0x69 ('i')
2358 *
2359 * offset (8 bit): opcode
2360 * offset + 1 (16 bit): CRTC port
2361 * offset + 3 (8 bit): mask
2362 * offset + 4 (8 bit): data
2363 *
2364 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2365 */
2366
2367 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2368 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2369 uint8_t mask = bios->data[offset + 3];
2370 uint8_t data = bios->data[offset + 4];
2371
2372 if (!iexec->execute)
37383650 2373 return 5;
6ee73861
BS		 2374
2375 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2376 offset, crtcport, mask, data);
2377
2378 /*
2379 * I have no idea what this does, but NVIDIA do this magic sequence
2380 * in the places where this INIT_IO happens..
2381 */
2382 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2383 int i;
2384
2385 bios_wr32(bios, 0x614100, (bios_rd32(
2386 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2387
2388 bios_wr32(bios, 0x00e18c, bios_rd32(
2389 bios, 0x00e18c) | 0x00020000);
2390
2391 bios_wr32(bios, 0x614900, (bios_rd32(
2392 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2393
2394 bios_wr32(bios, 0x000200, bios_rd32(
2395 bios, 0x000200) & ~0x40000000);
2396
2397 mdelay(10);
2398
2399 bios_wr32(bios, 0x00e18c, bios_rd32(
2400 bios, 0x00e18c) & ~0x00020000);
2401
2402 bios_wr32(bios, 0x000200, bios_rd32(
2403 bios, 0x000200) | 0x40000000);
2404
2405 bios_wr32(bios, 0x614100, 0x00800018);
2406 bios_wr32(bios, 0x614900, 0x00800018);
2407
2408 mdelay(10);
2409
2410 bios_wr32(bios, 0x614100, 0x10000018);
2411 bios_wr32(bios, 0x614900, 0x10000018);
2412
2413 for (i = 0; i < 3; i++)
2414 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2415 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2416
2417 for (i = 0; i < 2; i++)
2418 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2419 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2420
2421 for (i = 0; i < 3; i++)
2422 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2423 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2424
2425 for (i = 0; i < 2; i++)
2426 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2427 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2428
2429 for (i = 0; i < 2; i++)
2430 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2431 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2432 return 5;
6ee73861
BS		 2433 }
2434
2435 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2436 data);
37383650 2437 return 5;
6ee73861
BS		 2438}
2439
37383650 2440static int
6ee73861
BS		 2441init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2442{
2443 /*
2444 * INIT_SUB opcode: 0x6B ('k')
2445 *
2446 * offset (8 bit): opcode
2447 * offset + 1 (8 bit): script number
2448 *
2449 * Execute script number "script number", as a subroutine
2450 */
2451
2452 uint8_t sub = bios->data[offset + 1];
2453
2454 if (!iexec->execute)
37383650 2455 return 2;
6ee73861
BS		 2456
2457 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2458
2459 parse_init_table(bios,
2460 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2461 iexec);
2462
2463 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2464
37383650 2465 return 2;
6ee73861
BS		 2466}
2467
37383650 2468static int
6ee73861
BS		 2469init_ram_condition(struct nvbios *bios, uint16_t offset,
2470 struct init_exec *iexec)
2471{
2472 /*
2473 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2474 *
2475 * offset (8 bit): opcode
2476 * offset + 1 (8 bit): mask
2477 * offset + 2 (8 bit): cmpval
2478 *
3c7066bc 2479 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
6ee73861
BS		 2480 * If condition not met skip subsequent opcodes until condition is
2481 * inverted (INIT_NOT), or we hit INIT_RESUME
2482 */
2483
2484 uint8_t mask = bios->data[offset + 1];
2485 uint8_t cmpval = bios->data[offset + 2];
2486 uint8_t data;
2487
2488 if (!iexec->execute)
37383650 2489 return 3;
6ee73861 2490
3c7066bc 2491 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
6ee73861
BS		 2492
2493 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2494 offset, data, cmpval);
2495
2496 if (data == cmpval)
2497 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2498 else {
2499 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2500 iexec->execute = false;
2501 }
2502
37383650 2503 return 3;
6ee73861
BS		 2504}
2505
37383650 2506static int
6ee73861
BS		 2507init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2508{
2509 /*
2510 * INIT_NV_REG opcode: 0x6E ('n')
2511 *
2512 * offset (8 bit): opcode
2513 * offset + 1 (32 bit): register
2514 * offset + 5 (32 bit): mask
2515 * offset + 9 (32 bit): data
2516 *
2517 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2518 */
2519
2520 uint32_t reg = ROM32(bios->data[offset + 1]);
2521 uint32_t mask = ROM32(bios->data[offset + 5]);
2522 uint32_t data = ROM32(bios->data[offset + 9]);
2523
2524 if (!iexec->execute)
37383650 2525 return 13;
6ee73861
BS		 2526
2527 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2528 offset, reg, mask, data);
2529
2530 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2531
37383650 2532 return 13;
6ee73861
BS		 2533}
2534
37383650 2535static int
6ee73861
BS		 2536init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2537{
2538 /*
2539 * INIT_MACRO opcode: 0x6F ('o')
2540 *
2541 * offset (8 bit): opcode
2542 * offset + 1 (8 bit): macro number
2543 *
2544 * Look up macro index "macro number" in the macro index table.
2545 * The macro index table entry has 1 byte for the index in the macro
2546 * table, and 1 byte for the number of times to repeat the macro.
2547 * The macro table entry has 4 bytes for the register address and
2548 * 4 bytes for the value to write to that register
2549 */
2550
2551 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2552 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2553 uint8_t macro_tbl_idx = bios->data[tmp];
2554 uint8_t count = bios->data[tmp + 1];
2555 uint32_t reg, data;
2556 int i;
2557
2558 if (!iexec->execute)
37383650 2559 return 2;
6ee73861
BS		 2560
2561 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2562 "Count: 0x%02X\n",
2563 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2564
2565 for (i = 0; i < count; i++) {
2566 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2567
2568 reg = ROM32(bios->data[macroentryptr]);
2569 data = ROM32(bios->data[macroentryptr + 4]);
2570
2571 bios_wr32(bios, reg, data);
2572 }
2573
37383650 2574 return 2;
6ee73861
BS		 2575}
2576
37383650 2577static int
6ee73861
BS		 2578init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2579{
2580 /*
2581 * INIT_DONE opcode: 0x71 ('q')
2582 *
2583 * offset (8 bit): opcode
2584 *
2585 * End the current script
2586 */
2587
2588 /* mild retval abuse to stop parsing this table */
37383650 2589 return 0;
6ee73861
BS		 2590}
2591
37383650 2592static int
6ee73861
BS		 2593init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2594{
2595 /*
2596 * INIT_RESUME opcode: 0x72 ('r')
2597 *
2598 * offset (8 bit): opcode
2599 *
2600 * End the current execute / no-execute condition
2601 */
2602
2603 if (iexec->execute)
37383650 2604 return 1;
6ee73861
BS		 2605
2606 iexec->execute = true;
2607 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2608
37383650 2609 return 1;
6ee73861
BS		 2610}
2611
37383650 2612static int
6ee73861
BS		 2613init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2614{
2615 /*
2616 * INIT_TIME opcode: 0x74 ('t')
2617 *
2618 * offset (8 bit): opcode
2619 * offset + 1 (16 bit): time
2620 *
2621 * Sleep for "time" microseconds.
2622 */
2623
2624 unsigned time = ROM16(bios->data[offset + 1]);
2625
2626 if (!iexec->execute)
37383650 2627 return 3;
6ee73861
BS		 2628
2629 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2630 offset, time);
2631
2632 if (time < 1000)
2633 udelay(time);
2634 else
c7ca4d1b 2635 mdelay((time + 900) / 1000);
6ee73861 2636
37383650 2637 return 3;
6ee73861
BS		 2638}
2639
37383650 2640static int
6ee73861
BS		 2641init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2642{
2643 /*
2644 * INIT_CONDITION opcode: 0x75 ('u')
2645 *
2646 * offset (8 bit): opcode
2647 * offset + 1 (8 bit): condition number
2648 *
2649 * Check condition "condition number" in the condition table.
2650 * If condition not met skip subsequent opcodes until condition is
2651 * inverted (INIT_NOT), or we hit INIT_RESUME
2652 */
2653
2654 uint8_t cond = bios->data[offset + 1];
2655
2656 if (!iexec->execute)
37383650 2657 return 2;
6ee73861
BS		 2658
2659 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2660
2661 if (bios_condition_met(bios, offset, cond))
2662 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2663 else {
2664 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2665 iexec->execute = false;
2666 }
2667
37383650 2668 return 2;
6ee73861
BS		 2669}
2670
37383650 2671static int
6ee73861
BS		 2672init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2673{
2674 /*
2675 * INIT_IO_CONDITION opcode: 0x76
2676 *
2677 * offset (8 bit): opcode
2678 * offset + 1 (8 bit): condition number
2679 *
2680 * Check condition "condition number" in the io condition table.
2681 * If condition not met skip subsequent opcodes until condition is
2682 * inverted (INIT_NOT), or we hit INIT_RESUME
2683 */
2684
2685 uint8_t cond = bios->data[offset + 1];
2686
2687 if (!iexec->execute)
37383650 2688 return 2;
6ee73861
BS		 2689
2690 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2691
2692 if (io_condition_met(bios, offset, cond))
2693 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2694 else {
2695 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2696 iexec->execute = false;
2697 }
2698
37383650 2699 return 2;
6ee73861
BS		 2700}
2701
37383650 2702static int
6ee73861
BS		 2703init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2704{
2705 /*
2706 * INIT_INDEX_IO opcode: 0x78 ('x')
2707 *
2708 * offset (8 bit): opcode
2709 * offset + 1 (16 bit): CRTC port
2710 * offset + 3 (8 bit): CRTC index
2711 * offset + 4 (8 bit): mask
2712 * offset + 5 (8 bit): data
2713 *
2714 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2715 * OR with "data", write-back
2716 */
2717
2718 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2719 uint8_t crtcindex = bios->data[offset + 3];
2720 uint8_t mask = bios->data[offset + 4];
2721 uint8_t data = bios->data[offset + 5];
2722 uint8_t value;
2723
2724 if (!iexec->execute)
37383650 2725 return 6;
6ee73861
BS		 2726
2727 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2728 "Data: 0x%02X\n",
2729 offset, crtcport, crtcindex, mask, data);
2730
2731 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2732 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2733
37383650 2734 return 6;
6ee73861
BS		 2735}
2736
37383650 2737static int
6ee73861
BS		 2738init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2739{
2740 /*
2741 * INIT_PLL opcode: 0x79 ('y')
2742 *
2743 * offset (8 bit): opcode
2744 * offset + 1 (32 bit): register
2745 * offset + 5 (16 bit): freq
2746 *
2747 * Set PLL register "register" to coefficients for frequency (10kHz)
2748 * "freq"
2749 */
2750
2751 uint32_t reg = ROM32(bios->data[offset + 1]);
2752 uint16_t freq = ROM16(bios->data[offset + 5]);
2753
2754 if (!iexec->execute)
37383650 2755 return 7;
6ee73861
BS		 2756
2757 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
2758
70790f4f 2759 setPLL(bios->dev, reg, freq * 10);
6ee73861 2760
37383650 2761 return 7;
6ee73861
BS		 2762}
2763
37383650 2764static int
6ee73861
BS		 2765init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2766{
2767 /*
2768 * INIT_ZM_REG opcode: 0x7A ('z')
2769 *
2770 * offset (8 bit): opcode
2771 * offset + 1 (32 bit): register
2772 * offset + 5 (32 bit): value
2773 *
2774 * Assign "value" to "register"
2775 */
2776
2777 uint32_t reg = ROM32(bios->data[offset + 1]);
2778 uint32_t value = ROM32(bios->data[offset + 5]);
2779
2780 if (!iexec->execute)
37383650 2781 return 9;
6ee73861
BS		 2782
2783 if (reg == 0x000200)
2784 value |= 1;
2785
2786 bios_wr32(bios, reg, value);
2787
37383650 2788 return 9;
6ee73861
BS		 2789}
2790
37383650 2791static int
6ee73861
BS		 2792init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
2793 struct init_exec *iexec)
2794{
2795 /*
2796 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
2797 *
2798 * offset (8 bit): opcode
2799 * offset + 1 (8 bit): PLL type
2800 * offset + 2 (32 bit): frequency 0
2801 *
2802 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2803 * ram_restrict_table_ptr. The value read from there is used to select
2804 * a frequency from the table starting at 'frequency 0' to be
2805 * programmed into the PLL corresponding to 'type'.
2806 *
2807 * The PLL limits table on cards using this opcode has a mapping of
2808 * 'type' to the relevant registers.
2809 */
2810
2811 struct drm_device *dev = bios->dev;
2812 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
2813 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
2814 uint8_t type = bios->data[offset + 1];
2815 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
2816 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 2817 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 2818 int i;
2819
2820 if (!iexec->execute)
37383650 2821 return len;
6ee73861
BS		 2822
2823 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
2824 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 2825 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 2826 }
2827
2828 entry = pll_limits + pll_limits[1];
2829 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
2830 if (entry[0] == type) {
2831 uint32_t reg = ROM32(entry[3]);
2832
2833 BIOSLOG(bios, "0x%04X: "
2834 "Type %02x Reg 0x%08x Freq %dKHz\n",
2835 offset, type, reg, freq);
2836
70790f4f 2837 setPLL(bios->dev, reg, freq);
37383650 2838 return len;
6ee73861
BS		 2839 }
2840 }
2841
2842 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 2843 return len;
6ee73861
BS		 2844}
2845
37383650 2846static int
6ee73861
BS		 2847init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2848{
2849 /*
2850 * INIT_8C opcode: 0x8C ('')
2851 *
2852 * NOP so far....
2853 *
2854 */
2855
37383650 2856 return 1;
6ee73861
BS		 2857}
2858
37383650 2859static int
6ee73861
BS		 2860init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2861{
2862 /*
2863 * INIT_8D opcode: 0x8D ('')
2864 *
2865 * NOP so far....
2866 *
2867 */
2868
37383650 2869 return 1;
6ee73861
BS		 2870}
2871
37383650 2872static int
6ee73861
BS		 2873init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2874{
2875 /*
2876 * INIT_GPIO opcode: 0x8E ('')
2877 *
2878 * offset (8 bit): opcode
2879 *
2880 * Loop over all entries in the DCB GPIO table, and initialise
2881 * each GPIO according to various values listed in each entry
2882 */
2883
a0b25635
BS		 2884 if (iexec->execute && bios->execute)
2885 nouveau_gpio_reset(bios->dev);
6ee73861 2886
37383650 2887 return 1;
6ee73861
BS		 2888}
2889
37383650 2890static int
6ee73861
BS		 2891init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
2892 struct init_exec *iexec)
2893{
2894 /*
2895 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
2896 *
2897 * offset (8 bit): opcode
2898 * offset + 1 (32 bit): reg
2899 * offset + 5 (8 bit): regincrement
2900 * offset + 6 (8 bit): count
2901 * offset + 7 (32 bit): value 1,1
2902 * ...
2903 *
2904 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
2905 * ram_restrict_table_ptr. The value read from here is 'n', and
2906 * "value 1,n" gets written to "reg". This repeats "count" times and on
2907 * each iteration 'm', "reg" increases by "regincrement" and
2908 * "value m,n" is used. The extent of n is limited by a number read
2909 * from the 'M' BIT table, herein called "blocklen"
2910 */
2911
2912 uint32_t reg = ROM32(bios->data[offset + 1]);
2913 uint8_t regincrement = bios->data[offset + 5];
2914 uint8_t count = bios->data[offset + 6];
2915 uint32_t strap_ramcfg, data;
37383650
MK		 2916 /* previously set by 'M' BIT table */
2917 uint16_t blocklen = bios->ram_restrict_group_count * 4;
2918 int len = 7 + count * blocklen;
6ee73861
BS		 2919 uint8_t index;
2920 int i;
2921
309b8c89 2922 /* critical! to know the length of the opcode */;
6ee73861
BS		 2923 if (!blocklen) {
2924 NV_ERROR(bios->dev,
2925 "0x%04X: Zero block length - has the M table "
2926 "been parsed?\n", offset);
9170a824 2927 return -EINVAL;
6ee73861
BS		 2928 }
2929
309b8c89
BS		 2930 if (!iexec->execute)
2931 return len;
2932
6ee73861
BS		 2933 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
2934 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
2935
2936 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
2937 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
2938 offset, reg, regincrement, count, strap_ramcfg, index);
2939
2940 for (i = 0; i < count; i++) {
2941 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
2942
2943 bios_wr32(bios, reg, data);
2944
2945 reg += regincrement;
2946 }
2947
37383650 2948 return len;
6ee73861
BS		 2949}
2950
37383650 2951static int
6ee73861
BS		 2952init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2953{
2954 /*
2955 * INIT_COPY_ZM_REG opcode: 0x90 ('')
2956 *
2957 * offset (8 bit): opcode
2958 * offset + 1 (32 bit): src reg
2959 * offset + 5 (32 bit): dst reg
2960 *
2961 * Put contents of "src reg" into "dst reg"
2962 */
2963
2964 uint32_t srcreg = ROM32(bios->data[offset + 1]);
2965 uint32_t dstreg = ROM32(bios->data[offset + 5]);
2966
2967 if (!iexec->execute)
37383650 2968 return 9;
6ee73861
BS		 2969
2970 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
2971
37383650 2972 return 9;
6ee73861
BS		 2973}
2974
37383650 2975static int
6ee73861
BS		 2976init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
2977 struct init_exec *iexec)
2978{
2979 /*
2980 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
2981 *
2982 * offset (8 bit): opcode
2983 * offset + 1 (32 bit): dst reg
2984 * offset + 5 (8 bit): count
2985 * offset + 6 (32 bit): data 1
2986 * ...
2987 *
2988 * For each of "count" values write "data n" to "dst reg"
2989 */
2990
2991 uint32_t reg = ROM32(bios->data[offset + 1]);
2992 uint8_t count = bios->data[offset + 5];
37383650 2993 int len = 6 + count * 4;
6ee73861
BS		 2994 int i;
2995
2996 if (!iexec->execute)
37383650 2997 return len;
6ee73861
BS		 2998
2999 for (i = 0; i < count; i++) {
3000 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3001 bios_wr32(bios, reg, data);
3002 }
3003
37383650 3004 return len;
6ee73861
BS		 3005}
3006
37383650 3007static int
6ee73861
BS		 3008init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3009{
3010 /*
3011 * INIT_RESERVED opcode: 0x92 ('')
3012 *
3013 * offset (8 bit): opcode
3014 *
3015 * Seemingly does nothing
3016 */
3017
37383650 3018 return 1;
6ee73861
BS		 3019}
3020
37383650 3021static int
6ee73861
BS		 3022init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3023{
3024 /*
3025 * INIT_96 opcode: 0x96 ('')
3026 *
3027 * offset (8 bit): opcode
3028 * offset + 1 (32 bit): sreg
3029 * offset + 5 (8 bit): sshift
3030 * offset + 6 (8 bit): smask
3031 * offset + 7 (8 bit): index
3032 * offset + 8 (32 bit): reg
3033 * offset + 12 (32 bit): mask
3034 * offset + 16 (8 bit): shift
3035 *
3036 */
3037
3038 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3039 uint32_t reg = ROM32(bios->data[offset + 8]);
3040 uint32_t mask = ROM32(bios->data[offset + 12]);
3041 uint32_t val;
3042
3043 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3044 if (bios->data[offset + 5] < 0x80)
3045 val >>= bios->data[offset + 5];
3046 else
3047 val <<= (0x100 - bios->data[offset + 5]);
3048 val &= bios->data[offset + 6];
3049
3050 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3051 val <<= bios->data[offset + 16];
3052
3053 if (!iexec->execute)
37383650 3054 return 17;
6ee73861
BS		 3055
3056 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3057 return 17;
6ee73861
BS		 3058}
3059
37383650 3060static int
6ee73861
BS		 3061init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3062{
3063 /*
3064 * INIT_97 opcode: 0x97 ('')
3065 *
3066 * offset (8 bit): opcode
3067 * offset + 1 (32 bit): register
3068 * offset + 5 (32 bit): mask
3069 * offset + 9 (32 bit): value
3070 *
3071 * Adds "value" to "register" preserving the fields specified
3072 * by "mask"
3073 */
3074
3075 uint32_t reg = ROM32(bios->data[offset + 1]);
3076 uint32_t mask = ROM32(bios->data[offset + 5]);
3077 uint32_t add = ROM32(bios->data[offset + 9]);
3078 uint32_t val;
3079
3080 val = bios_rd32(bios, reg);
3081 val = (val & mask) | ((val + add) & ~mask);
3082
3083 if (!iexec->execute)
37383650 3084 return 13;
6ee73861
BS		 3085
3086 bios_wr32(bios, reg, val);
37383650 3087 return 13;
6ee73861
BS		 3088}
3089
37383650 3090static int
6ee73861
BS		 3091init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3092{
3093 /*
3094 * INIT_AUXCH opcode: 0x98 ('')
3095 *
3096 * offset (8 bit): opcode
3097 * offset + 1 (32 bit): address
3098 * offset + 5 (8 bit): count
3099 * offset + 6 (8 bit): mask 0
3100 * offset + 7 (8 bit): data 0
3101 * ...
3102 *
3103 */
3104
3105 struct drm_device *dev = bios->dev;
4196faa8 3106 struct nouveau_i2c_port *auxch;
6ee73861 3107 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3108 uint8_t count = bios->data[offset + 5];
3109 int len = 6 + count * 2;
6ee73861
BS		 3110 int ret, i;
3111
3112 if (!bios->display.output) {
3113 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
309b8c89 3114 return len;
6ee73861
BS		 3115 }
3116
3117 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3118 if (!auxch) {
3119 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3120 bios->display.output->i2c_index);
309b8c89 3121 return len;
6ee73861
BS		 3122 }
3123
3124 if (!iexec->execute)
37383650 3125 return len;
6ee73861
BS		 3126
3127 offset += 6;
37383650 3128 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3129 uint8_t data;
3130
4196faa8 3131 ret = auxch_rd(dev, auxch, addr, &data, 1);
6ee73861
BS		 3132 if (ret) {
3133 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
309b8c89 3134 return len;
6ee73861
BS		 3135 }
3136
3137 data &= bios->data[offset + 0];
3138 data |= bios->data[offset + 1];
3139
4196faa8 3140 ret = auxch_wr(dev, auxch, addr, &data, 1);
6ee73861
BS		 3141 if (ret) {
3142 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3143 return len;
6ee73861
BS		 3144 }
3145 }
3146
37383650 3147 return len;
6ee73861
BS		 3148}
3149
37383650 3150static int
6ee73861
BS		 3151init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3152{
3153 /*
3154 * INIT_ZM_AUXCH opcode: 0x99 ('')
3155 *
3156 * offset (8 bit): opcode
3157 * offset + 1 (32 bit): address
3158 * offset + 5 (8 bit): count
3159 * offset + 6 (8 bit): data 0
3160 * ...
3161 *
3162 */
3163
3164 struct drm_device *dev = bios->dev;
4196faa8 3165 struct nouveau_i2c_port *auxch;
6ee73861 3166 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3167 uint8_t count = bios->data[offset + 5];
3168 int len = 6 + count;
6ee73861
BS		 3169 int ret, i;
3170
3171 if (!bios->display.output) {
3172 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
309b8c89 3173 return len;
6ee73861
BS		 3174 }
3175
3176 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3177 if (!auxch) {
3178 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3179 bios->display.output->i2c_index);
309b8c89 3180 return len;
6ee73861
BS		 3181 }
3182
3183 if (!iexec->execute)
37383650 3184 return len;
6ee73861
BS		 3185
3186 offset += 6;
37383650 3187 for (i = 0; i < count; i++, offset++) {
4196faa8 3188 ret = auxch_wr(dev, auxch, addr, &bios->data[offset], 1);
6ee73861
BS		 3189 if (ret) {
3190 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3191 return len;
6ee73861
BS		 3192 }
3193 }
3194
37383650 3195 return len;
6ee73861
BS		 3196}
3197
b715d640
MK		 3198static int
3199init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3200{
3201 /*
3202 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3203 *
3204 * offset (8 bit): opcode
3205 * offset + 1 (8 bit): DCB I2C table entry index
3206 * offset + 2 (8 bit): I2C slave address
3207 * offset + 3 (16 bit): I2C register
3208 * offset + 5 (8 bit): mask
3209 * offset + 6 (8 bit): data
3210 *
3211 * Read the register given by "I2C register" on the device addressed
3212 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3213 * entry index". Compare the result AND "mask" to "data".
3214 * If they're not equal, skip subsequent opcodes until condition is
3215 * inverted (INIT_NOT), or we hit INIT_RESUME
3216 */
3217
3218 uint8_t i2c_index = bios->data[offset + 1];
3219 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3220 uint8_t reglo = bios->data[offset + 3];
3221 uint8_t reghi = bios->data[offset + 4];
3222 uint8_t mask = bios->data[offset + 5];
3223 uint8_t data = bios->data[offset + 6];
4196faa8 3224 struct nouveau_i2c_port *chan;
b715d640
MK		 3225 uint8_t buf0[2] = { reghi, reglo };
3226 uint8_t buf1[1];
3227 struct i2c_msg msg[2] = {
3228 { i2c_address, 0, 1, buf0 },
3229 { i2c_address, I2C_M_RD, 1, buf1 },
3230 };
3231 int ret;
3232
3233 /* no execute check by design */
3234
3235 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3236 offset, i2c_index, i2c_address);
3237
3238 chan = init_i2c_device_find(bios->dev, i2c_index);
3239 if (!chan)
3240 return -ENODEV;
3241
3242
4196faa8 3243 ret = i2c_transfer(nouveau_i2c_adapter(chan), msg, 2);
b715d640
MK		 3244 if (ret < 0) {
3245 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3246 "Mask: 0x%02X, Data: 0x%02X\n",
3247 offset, reghi, reglo, mask, data);
3248 iexec->execute = 0;
3249 return 7;
3250 }
3251
3252 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3253 "Mask: 0x%02X, Data: 0x%02X\n",
3254 offset, reghi, reglo, buf1[0], mask, data);
3255
3256 iexec->execute = ((buf1[0] & mask) == data);
3257
3258 return 7;
3259}
3260
6ee73861
BS		 3261static struct init_tbl_entry itbl_entry[] = {
3262 /* command name , id , length , offset , mult , command handler */
3263 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3264 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3265 { "INIT_REPEAT" , 0x33, init_repeat },
3266 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3267 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3268 { "INIT_COPY" , 0x37, init_copy },
3269 { "INIT_NOT" , 0x38, init_not },
3270 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3271 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3272 { "INIT_OP_3B" , 0x3B, init_op_3b },
3273 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3274 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3275 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3276 { "INIT_PLL2" , 0x4B, init_pll2 },
3277 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3278 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3279 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3280 { "INIT_TMDS" , 0x4F, init_tmds },
3281 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3282 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3283 { "INIT_CR" , 0x52, init_cr },
3284 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3285 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3286 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
e3a1924f 3287 { "INIT_LTIME" , 0x57, init_ltime },
37383650 3288 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3289 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650 3290 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
ec64a408 3291 { "INIT_JUMP" , 0x5C, init_jump },
b715d640 3292 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
37383650
MK		 3293 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3294 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3295 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3296 { "INIT_RESET" , 0x65, init_reset },
3297 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3298 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3299 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3300 { "INIT_IO" , 0x69, init_io },
3301 { "INIT_SUB" , 0x6B, init_sub },
3302 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3303 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3304 { "INIT_MACRO" , 0x6F, init_macro },
3305 { "INIT_DONE" , 0x71, init_done },
3306 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3307 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3308 { "INIT_TIME" , 0x74, init_time },
3309 { "INIT_CONDITION" , 0x75, init_condition },
3310 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3311 { "INIT_INDEX_IO" , 0x78, init_index_io },
3312 { "INIT_PLL" , 0x79, init_pll },
3313 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3314 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3315 { "INIT_8C" , 0x8C, init_8c },
3316 { "INIT_8D" , 0x8D, init_8d },
3317 { "INIT_GPIO" , 0x8E, init_gpio },
3318 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3319 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3320 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3321 { "INIT_RESERVED" , 0x92, init_reserved },
3322 { "INIT_96" , 0x96, init_96 },
3323 { "INIT_97" , 0x97, init_97 },
3324 { "INIT_AUXCH" , 0x98, init_auxch },
3325 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
b715d640 3326 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
37383650 3327 { NULL , 0 , NULL }
6ee73861
BS		 3328};
3329
6ee73861
BS		 3330#define MAX_TABLE_OPS 1000
3331
3332static int
ec64a408 3333parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
6ee73861
BS		 3334{
3335 /*
3336 * Parses all commands in an init table.
3337 *
3338 * We start out executing all commands found in the init table. Some
3339 * opcodes may change the status of iexec->execute to SKIP, which will
3340 * cause the following opcodes to perform no operation until the value
3341 * is changed back to EXECUTE.
3342 */
3343
92b96187 3344 int count = 0, i, ret;
6ee73861
BS		 3345 uint8_t id;
3346
a8e415d3
BS		 3347 /* catch NULL script pointers */
3348 if (offset == 0)
3349 return 0;
3350
6ee73861
BS		 3351 /*
3352 * Loop until INIT_DONE causes us to break out of the loop
3353 * (or until offset > bios length just in case... )
3354 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3355 */
3356 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3357 id = bios->data[offset];
3358
3359 /* Find matching id in itbl_entry */
3360 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3361 ;
3362
92b96187 3363 if (!itbl_entry[i].name) {
6ee73861
BS		 3364 NV_ERROR(bios->dev,
3365 "0x%04X: Init table command not found: "
3366 "0x%02X\n", offset, id);
3367 return -ENOENT;
3368 }
92b96187
BS		 3369
3370 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3371 itbl_entry[i].id, itbl_entry[i].name);
3372
3373 /* execute eventual command handler */
3374 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3375 if (ret < 0) {
3376 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3377 "table opcode: %s %d\n", offset,
3378 itbl_entry[i].name, ret);
3379 }
3380
3381 if (ret <= 0)
3382 break;
3383
3384 /*
3385 * Add the offset of the current command including all data
3386 * of that command. The offset will then be pointing on the
3387 * next op code.
3388 */
3389 offset += ret;
6ee73861
BS		 3390 }
3391
3392 if (offset >= bios->length)
3393 NV_WARN(bios->dev,
3394 "Offset 0x%04X greater than known bios image length. "
3395 "Corrupt image?\n", offset);
3396 if (count >= MAX_TABLE_OPS)
3397 NV_WARN(bios->dev,
3398 "More than %d opcodes to a table is unlikely, "
3399 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3400
3401 return 0;
3402}
3403
3404static void
3405parse_init_tables(struct nvbios *bios)
3406{
3407 /* Loops and calls parse_init_table() for each present table. */
3408
3409 int i = 0;
3410 uint16_t table;
3411 struct init_exec iexec = {true, false};
3412
3413 if (bios->old_style_init) {
3414 if (bios->init_script_tbls_ptr)
3415 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3416 if (bios->extra_init_script_tbl_ptr)
3417 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3418
3419 return;
3420 }
3421
3422 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3423 NV_INFO(bios->dev,
3424 "Parsing VBIOS init table %d at offset 0x%04X\n",
3425 i / 2, table);
3426 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3427
3428 parse_init_table(bios, table, &iexec);
3429 i += 2;
3430 }
3431}
3432
3433static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3434{
3435 int compare_record_len, i = 0;
3436 uint16_t compareclk, scriptptr = 0;
3437
3438 if (bios->major_version < 5) /* pre BIT */
3439 compare_record_len = 3;
3440 else
3441 compare_record_len = 4;
3442
3443 do {
3444 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3445 if (pxclk >= compareclk * 10) {
3446 if (bios->major_version < 5) {
3447 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3448 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3449 } else
3450 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3451 break;
3452 }
3453 i++;
3454 } while (compareclk);
3455
3456 return scriptptr;
3457}
3458
3459static void
3460run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3461 struct dcb_entry *dcbent, int head, bool dl)
3462{
3463 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3464 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3465 struct init_exec iexec = {true, false};
3466
3467 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3468 scriptptr);
3469 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3470 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3471 /* note: if dcb entries have been merged, index may be misleading */
3472 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3473 parse_init_table(bios, scriptptr, &iexec);
3474
3475 nv04_dfp_bind_head(dev, dcbent, head, dl);
3476}
3477
3478static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3479{
3480 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3481 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3482 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3483 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3484
3485 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3486 return -EINVAL;
3487
3488 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3489
3490 if (script == LVDS_PANEL_OFF) {
3491 /* off-on delay in ms */
c7ca4d1b 3492 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
6ee73861
BS		 3493 }
3494#ifdef __powerpc__
3495 /* Powerbook specific quirks */
d31e078d
FJ		 3496 if (script == LVDS_RESET &&
3497 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3498 dev->pci_device == 0x0329))
3499 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
6ee73861
BS		 3500#endif
3501
3502 return 0;
3503}
3504
3505static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3506{
3507 /*
3508 * The BIT LVDS table's header has the information to setup the
3509 * necessary registers. Following the standard 4 byte header are:
3510 * A bitmask byte and a dual-link transition pxclk value for use in
3511 * selecting the init script when not using straps; 4 script pointers
3512 * for panel power, selected by output and on/off; and 8 table pointers
3513 * for panel init, the needed one determined by output, and bits in the
3514 * conf byte. These tables are similar to the TMDS tables, consisting
3515 * of a list of pxclks and script pointers.
3516 */
3517 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3518 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3519 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3520 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3521
3522 /*
3523 * For now we assume version 3.0 table - g80 support will need some
3524 * changes
3525 */
3526
3527 switch (script) {
3528 case LVDS_INIT:
3529 return -ENOSYS;
3530 case LVDS_BACKLIGHT_ON:
3531 case LVDS_PANEL_ON:
3532 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3533 break;
3534 case LVDS_BACKLIGHT_OFF:
3535 case LVDS_PANEL_OFF:
3536 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3537 break;
3538 case LVDS_RESET:
f3bbb9cc
BS		 3539 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3540 if (dcbent->or == 4)
3541 clktable += 8;
3542
6ee73861
BS		 3543 if (dcbent->lvdsconf.use_straps_for_mode) {
3544 if (bios->fp.dual_link)
f3bbb9cc
BS		 3545 clktable += 4;
3546 if (bios->fp.if_is_24bit)
3547 clktable += 2;
6ee73861
BS		 3548 } else {
3549 /* using EDID */
f3bbb9cc 3550 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3551
3552 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3553 clktable += 4;
3554 cmpval_24bit <<= 1;
6ee73861 3555 }
f3bbb9cc
BS		 3556
3557 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3558 clktable += 2;
6ee73861
BS		 3559 }
3560
f3bbb9cc 3561 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3562 if (!clktable) {
3563 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3564 return -ENOENT;
3565 }
3566 scriptptr = clkcmptable(bios, clktable, pxclk);
3567 }
3568
3569 if (!scriptptr) {
3570 NV_ERROR(dev, "LVDS output init script not found\n");
3571 return -ENOENT;
3572 }
3573 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3574
3575 return 0;
3576}
3577
3578int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3579{
3580 /*
3581 * LVDS operations are multiplexed in an effort to present a single API
3582 * which works with two vastly differing underlying structures.
3583 * This acts as the demux
3584 */
3585
3586 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3587 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3588 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3589 uint32_t sel_clk_binding, sel_clk;
3590 int ret;
3591
3592 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3593 (lvds_ver >= 0x30 && script == LVDS_INIT))
3594 return 0;
3595
3596 if (!bios->fp.lvds_init_run) {
3597 bios->fp.lvds_init_run = true;
3598 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3599 }
3600
3601 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3602 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3603 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3604 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3605
3606 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3607
3608 /* don't let script change pll->head binding */
3609 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3610
3611 if (lvds_ver < 0x30)
3612 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3613 else
3614 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3615
3616 bios->fp.last_script_invoc = (script << 1 | head);
3617
3618 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3619 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3620 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3621 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3622
3623 return ret;
3624}
3625
3626struct lvdstableheader {
3627 uint8_t lvds_ver, headerlen, recordlen;
3628};
3629
3630static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3631{
3632 /*
3633 * BMP version (0xa) LVDS table has a simple header of version and
3634 * record length. The BIT LVDS table has the typical BIT table header:
3635 * version byte, header length byte, record length byte, and a byte for
3636 * the maximum number of records that can be held in the table.
3637 */
3638
3639 uint8_t lvds_ver, headerlen, recordlen;
3640
3641 memset(lth, 0, sizeof(struct lvdstableheader));
3642
3643 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3644 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3645 return -EINVAL;
3646 }
3647
3648 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3649
3650 switch (lvds_ver) {
3651 case 0x0a: /* pre NV40 */
3652 headerlen = 2;
3653 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3654 break;
3655 case 0x30: /* NV4x */
3656 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3657 if (headerlen < 0x1f) {
3658 NV_ERROR(dev, "LVDS table header not understood\n");
3659 return -EINVAL;
3660 }
3661 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3662 break;
3663 case 0x40: /* G80/G90 */
3664 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3665 if (headerlen < 0x7) {
3666 NV_ERROR(dev, "LVDS table header not understood\n");
3667 return -EINVAL;
3668 }
3669 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3670 break;
3671 default:
3672 NV_ERROR(dev,
3673 "LVDS table revision %d.%d not currently supported\n",
3674 lvds_ver >> 4, lvds_ver & 0xf);
3675 return -ENOSYS;
3676 }
3677
3678 lth->lvds_ver = lvds_ver;
3679 lth->headerlen = headerlen;
3680 lth->recordlen = recordlen;
3681
3682 return 0;
3683}
3684
3685static int
3686get_fp_strap(struct drm_device *dev, struct nvbios *bios)
3687{
3688 struct drm_nouveau_private *dev_priv = dev->dev_private;
3689
3690 /*
3691 * The fp strap is normally dictated by the "User Strap" in
3692 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
3693 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
3694 * by the PCI subsystem ID during POST, but not before the previous user
3695 * strap has been committed to CR58 for CR57=0xf on head A, which may be
3696 * read and used instead
3697 */
3698
3699 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
3700 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
3701
3702 if (dev_priv->card_type >= NV_50)
3703 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
3704 else
3705 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
3706}
3707
3708static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
3709{
3710 uint8_t *fptable;
3711 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
3712 int ret, ofs, fpstrapping;
3713 struct lvdstableheader lth;
3714
3715 if (bios->fp.fptablepointer == 0x0) {
3716 /* Apple cards don't have the fp table; the laptops use DDC */
3717 /* The table is also missing on some x86 IGPs */
3718#ifndef __powerpc__
3719 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
3720#endif
04a39c57 3721 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 3722 return 0;
3723 }
3724
3725 fptable = &bios->data[bios->fp.fptablepointer];
3726 fptable_ver = fptable[0];
3727
3728 switch (fptable_ver) {
3729 /*
3730 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
3731 * version field, and miss one of the spread spectrum/PWM bytes.
3732 * This could affect early GF2Go parts (not seen any appropriate ROMs
3733 * though). Here we assume that a version of 0x05 matches this case
3734 * (combining with a BMP version check would be better), as the
3735 * common case for the panel type field is 0x0005, and that is in
3736 * fact what we are reading the first byte of.
3737 */
3738 case 0x05: /* some NV10, 11, 15, 16 */
3739 recordlen = 42;
3740 ofs = -1;
3741 break;
3742 case 0x10: /* some NV15/16, and NV11+ */
3743 recordlen = 44;
3744 ofs = 0;
3745 break;
3746 case 0x20: /* NV40+ */
3747 headerlen = fptable[1];
3748 recordlen = fptable[2];
3749 fpentries = fptable[3];
3750 /*
3751 * fptable[4] is the minimum
3752 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
3753 */
04a39c57 3754 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 3755 ofs = -7;
3756 break;
3757 default:
3758 NV_ERROR(dev,
3759 "FP table revision %d.%d not currently supported\n",
3760 fptable_ver >> 4, fptable_ver & 0xf);
3761 return -ENOSYS;
3762 }
3763
3764 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
3765 return 0;
3766
3767 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3768 if (ret)
3769 return ret;
3770
3771 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
3772 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
3773 lth.headerlen + 1;
3774 bios->fp.xlatwidth = lth.recordlen;
3775 }
3776 if (bios->fp.fpxlatetableptr == 0x0) {
3777 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
3778 return -EINVAL;
3779 }
3780
3781 fpstrapping = get_fp_strap(dev, bios);
3782
3783 fpindex = bios->data[bios->fp.fpxlatetableptr +
3784 fpstrapping * bios->fp.xlatwidth];
3785
3786 if (fpindex > fpentries) {
3787 NV_ERROR(dev, "Bad flat panel table index\n");
3788 return -ENOENT;
3789 }
3790
3791 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
3792 if (lth.lvds_ver > 0x10)
04a39c57 3793 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 3794
3795 /*
3796 * If either the strap or xlated fpindex value are 0xf there is no
3797 * panel using a strap-derived bios mode present. this condition
3798 * includes, but is different from, the DDC panel indicator above
3799 */
3800 if (fpstrapping == 0xf || fpindex == 0xf)
3801 return 0;
3802
3803 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
3804 recordlen * fpindex + ofs;
3805
3806 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
3807 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
3808 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
3809 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
3810
3811 return 0;
3812}
3813
3814bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
3815{
3816 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3817 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3818 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
3819
3820 if (!mode) /* just checking whether we can produce a mode */
3821 return bios->fp.mode_ptr;
3822
3823 memset(mode, 0, sizeof(struct drm_display_mode));
3824 /*
3825 * For version 1.0 (version in byte 0):
3826 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
3827 * single/dual link, and type (TFT etc.)
3828 * bytes 3-6 are bits per colour in RGBX
3829 */
3830 mode->clock = ROM16(mode_entry[7]) * 10;
3831 /* bytes 9-10 is HActive */
3832 mode->hdisplay = ROM16(mode_entry[11]) + 1;
3833 /*
3834 * bytes 13-14 is HValid Start
3835 * bytes 15-16 is HValid End
3836 */
3837 mode->hsync_start = ROM16(mode_entry[17]) + 1;
3838 mode->hsync_end = ROM16(mode_entry[19]) + 1;
3839 mode->htotal = ROM16(mode_entry[21]) + 1;
3840 /* bytes 23-24, 27-30 similarly, but vertical */
3841 mode->vdisplay = ROM16(mode_entry[25]) + 1;
3842 mode->vsync_start = ROM16(mode_entry[31]) + 1;
3843 mode->vsync_end = ROM16(mode_entry[33]) + 1;
3844 mode->vtotal = ROM16(mode_entry[35]) + 1;
3845 mode->flags |= (mode_entry[37] & 0x10) ?
3846 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
3847 mode->flags |= (mode_entry[37] & 0x1) ?
3848 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
3849 /*
3850 * bytes 38-39 relate to spread spectrum settings
3851 * bytes 40-43 are something to do with PWM
3852 */
3853
3854 mode->status = MODE_OK;
3855 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
3856 drm_mode_set_name(mode);
3857 return bios->fp.mode_ptr;
3858}
3859
3860int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
3861{
3862 /*
3863 * The LVDS table header is (mostly) described in
3864 * parse_lvds_manufacturer_table_header(): the BIT header additionally
3865 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
3866 * straps are not being used for the panel, this specifies the frequency
3867 * at which modes should be set up in the dual link style.
3868 *
3869 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 3870 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 3871 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
3872 * numbers for use by INIT_SUB which controlled panel init and power,
3873 * and finally a dword of ms to sleep between power off and on
3874 * operations.
3875 *
3876 * In the BIT versions, the table following the header serves as an
3877 * integrated config and xlat table: the records in the table are
3878 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
3879 * two bytes - the first as a config byte, the second for indexing the
3880 * fp mode table pointed to by the BIT 'D' table
3881 *
3882 * DDC is not used until after card init, so selecting the correct table
3883 * entry and setting the dual link flag for EDID equipped panels,
3884 * requiring tests against the native-mode pixel clock, cannot be done
3885 * until later, when this function should be called with non-zero pxclk
3886 */
3887 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3888 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3889 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
3890 struct lvdstableheader lth;
3891 uint16_t lvdsofs;
04a39c57 3892 int ret, chip_version = bios->chip_version;
6ee73861
BS		 3893
3894 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
3895 if (ret)
3896 return ret;
3897
3898 switch (lth.lvds_ver) {
3899 case 0x0a: /* pre NV40 */
3900 lvdsmanufacturerindex = bios->data[
3901 bios->fp.fpxlatemanufacturertableptr +
3902 fpstrapping];
3903
3904 /* we're done if this isn't the EDID panel case */
3905 if (!pxclk)
3906 break;
3907
3908 if (chip_version < 0x25) {
3909 /* nv17 behaviour
3910 *
3911 * It seems the old style lvds script pointer is reused
3912 * to select 18/24 bit colour depth for EDID panels.
3913 */
3914 lvdsmanufacturerindex =
3915 (bios->legacy.lvds_single_a_script_ptr & 1) ?
3916 2 : 0;
3917 if (pxclk >= bios->fp.duallink_transition_clk)
3918 lvdsmanufacturerindex++;
3919 } else if (chip_version < 0x30) {
3920 /* nv28 behaviour (off-chip encoder)
3921 *
3922 * nv28 does a complex dance of first using byte 121 of
3923 * the EDID to choose the lvdsmanufacturerindex, then
3924 * later attempting to match the EDID manufacturer and
3925 * product IDs in a table (signature 'pidt' (panel id
3926 * table?)), setting an lvdsmanufacturerindex of 0 and
3927 * an fp strap of the match index (or 0xf if none)
3928 */
3929 lvdsmanufacturerindex = 0;
3930 } else {
3931 /* nv31, nv34 behaviour */
3932 lvdsmanufacturerindex = 0;
3933 if (pxclk >= bios->fp.duallink_transition_clk)
3934 lvdsmanufacturerindex = 2;
3935 if (pxclk >= 140000)
3936 lvdsmanufacturerindex = 3;
3937 }
3938
3939 /*
3940 * nvidia set the high nibble of (cr57=f, cr58) to
3941 * lvdsmanufacturerindex in this case; we don't
3942 */
3943 break;
3944 case 0x30: /* NV4x */
3945 case 0x40: /* G80/G90 */
3946 lvdsmanufacturerindex = fpstrapping;
3947 break;
3948 default:
3949 NV_ERROR(dev, "LVDS table revision not currently supported\n");
3950 return -ENOSYS;
3951 }
3952
3953 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
3954 switch (lth.lvds_ver) {
3955 case 0x0a:
3956 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
3957 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
3958 bios->fp.dual_link = bios->data[lvdsofs] & 4;
3959 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
3960 *if_is_24bit = bios->data[lvdsofs] & 16;
3961 break;
3962 case 0x30:
f3bbb9cc 3963 case 0x40:
6ee73861
BS		 3964 /*
3965 * No sign of the "power off for reset" or "reset for panel
3966 * on" bits, but it's safer to assume we should
3967 */
3968 bios->fp.power_off_for_reset = true;
3969 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 3970
6ee73861
BS		 3971 /*
3972 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 3973 * over-written, and if_is_24bit isn't used
6ee73861
BS		 3974 */
3975 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 3976 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
3977 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
3978 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
3979 break;
3980 }
3981
3982 /* set dual_link flag for EDID case */
3983 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
3984 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
3985
3986 *dl = bios->fp.dual_link;
3987
3988 return 0;
3989}
3990
721b0821
BS		 3991/* BIT 'U'/'d' table encoder subtables have hashes matching them to
3992 * a particular set of encoders.
3993 *
3994 * This function returns true if a particular DCB entry matches.
3995 */
3996bool
3997bios_encoder_match(struct dcb_entry *dcb, u32 hash)
6ee73861 3998{
721b0821
BS		 3999 if ((hash & 0x000000f0) != (dcb->location << 4))
4000 return false;
4001 if ((hash & 0x0000000f) != dcb->type)
4002 return false;
4003 if (!(hash & (dcb->or << 16)))
4004 return false;
4005
4006 switch (dcb->type) {
1eb38100
BS		 4007 case OUTPUT_TMDS:
4008 case OUTPUT_LVDS:
4009 case OUTPUT_DP:
721b0821
BS		 4010 if (hash & 0x00c00000) {
4011 if (!(hash & (dcb->sorconf.link << 22)))
4012 return false;
1eb38100 4013 }
721b0821
BS		 4014 default:
4015 return true;
6ee73861 4016 }
6ee73861
BS		 4017}
4018
6ee73861 4019int
02e4f587
BS		 4020nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4021 struct dcb_entry *dcbent, int crtc)
6ee73861
BS		 4022{
4023 /*
4024 * The display script table is located by the BIT 'U' table.
4025 *
4026 * It contains an array of pointers to various tables describing
4027 * a particular output type. The first 32-bits of the output
4028 * tables contains similar information to a DCB entry, and is
4029 * used to decide whether that particular table is suitable for
4030 * the output you want to access.
4031 *
4032 * The "record header length" field here seems to indicate the
4033 * offset of the first configuration entry in the output tables.
4034 * This is 10 on most cards I've seen, but 12 has been witnessed
4035 * on DP cards, and there's another script pointer within the
4036 * header.
4037 *
4038 * offset + 0 ( 8 bits): version
4039 * offset + 1 ( 8 bits): header length
4040 * offset + 2 ( 8 bits): record length
4041 * offset + 3 ( 8 bits): number of records
4042 * offset + 4 ( 8 bits): record header length
4043 * offset + 5 (16 bits): pointer to first output script table
4044 */
4045
4046 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4047 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4048 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4049 uint8_t *otable = NULL;
4050 uint16_t script;
721b0821 4051 int i;
6ee73861
BS		 4052
4053 if (!bios->display.script_table_ptr) {
4054 NV_ERROR(dev, "No pointer to output script table\n");
4055 return 1;
4056 }
4057
4058 /*
4059 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4060 * so until they are, we really don't need to care.
4061 */
4062 if (table[0] < 0x20)
4063 return 1;
4064
4065 if (table[0] != 0x20 && table[0] != 0x21) {
4066 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4067 table[0]);
4068 return 1;
4069 }
4070
4071 /*
4072 * The output script tables describing a particular output type
4073 * look as follows:
4074 *
4075 * offset + 0 (32 bits): output this table matches (hash of DCB)
4076 * offset + 4 ( 8 bits): unknown
4077 * offset + 5 ( 8 bits): number of configurations
4078 * offset + 6 (16 bits): pointer to some script
4079 * offset + 8 (16 bits): pointer to some script
4080 *
4081 * headerlen == 10
4082 * offset + 10 : configuration 0
4083 *
4084 * headerlen == 12
4085 * offset + 10 : pointer to some script
4086 * offset + 12 : configuration 0
4087 *
4088 * Each config entry is as follows:
4089 *
4090 * offset + 0 (16 bits): unknown, assumed to be a match value
4091 * offset + 2 (16 bits): pointer to script table (clock set?)
4092 * offset + 4 (16 bits): pointer to script table (reset?)
4093 *
4094 * There doesn't appear to be a count value to say how many
4095 * entries exist in each script table, instead, a 0 value in
4096 * the first 16-bit word seems to indicate both the end of the
4097 * list and the default entry. The second 16-bit word in the
4098 * script tables is a pointer to the script to execute.
4099 */
4100
ef2bb506 4101 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861 4102 dcbent->type, dcbent->location, dcbent->or);
721b0821 4103 for (i = 0; i < table[3]; i++) {
f9f9f536 4104 otable = ROMPTR(dev, table[table[1] + (i * table[2])]);
721b0821
BS		 4105 if (otable && bios_encoder_match(dcbent, ROM32(otable[0])))
4106 break;
4107 }
4108
6ee73861 4109 if (!otable) {
54bf67de 4110 NV_DEBUG_KMS(dev, "failed to match any output table\n");
6ee73861
BS		 4111 return 1;
4112 }
4113
02e4f587 4114 if (pclk < -2 || pclk > 0) {
6ee73861
BS		 4115 /* Try to find matching script table entry */
4116 for (i = 0; i < otable[5]; i++) {
02e4f587 4117 if (ROM16(otable[table[4] + i*6]) == type)
6ee73861
BS		 4118 break;
4119 }
4120
4121 if (i == otable[5]) {
4122 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4123 "using first\n",
02e4f587 4124 type, dcbent->type, dcbent->or);
6ee73861
BS		 4125 i = 0;
4126 }
4127 }
4128
02e4f587 4129 if (pclk == 0) {
6ee73861
BS		 4130 script = ROM16(otable[6]);
4131 if (!script) {
ef2bb506 4132 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4133 return 1;
4134 }
4135
45a68a07 4136 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
02e4f587 4137 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4138 } else
02e4f587 4139 if (pclk == -1) {
6ee73861
BS		 4140 script = ROM16(otable[8]);
4141 if (!script) {
ef2bb506 4142 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4143 return 1;
4144 }
4145
45a68a07 4146 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
02e4f587 4147 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4148 } else
02e4f587 4149 if (pclk == -2) {
6ee73861
BS		 4150 if (table[4] >= 12)
4151 script = ROM16(otable[10]);
4152 else
4153 script = 0;
4154 if (!script) {
ef2bb506 4155 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4156 return 1;
4157 }
4158
45a68a07 4159 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
02e4f587 4160 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4161 } else
02e4f587 4162 if (pclk > 0) {
6ee73861
BS		 4163 script = ROM16(otable[table[4] + i*6 + 2]);
4164 if (script)
02e4f587 4165 script = clkcmptable(bios, script, pclk);
6ee73861 4166 if (!script) {
54bf67de 4167 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
6ee73861
BS		 4168 return 1;
4169 }
4170
45a68a07 4171 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
02e4f587 4172 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4173 } else
02e4f587 4174 if (pclk < 0) {
6ee73861
BS		 4175 script = ROM16(otable[table[4] + i*6 + 4]);
4176 if (script)
02e4f587 4177 script = clkcmptable(bios, script, -pclk);
6ee73861 4178 if (!script) {
ef2bb506 4179 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4180 return 1;
4181 }
4182
45a68a07 4183 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
02e4f587 4184 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861
BS		 4185 }
4186
4187 return 0;
4188}
4189
4190
4191int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4192{
4193 /*
4194 * the pxclk parameter is in kHz
4195 *
4196 * This runs the TMDS regs setting code found on BIT bios cards
4197 *
4198 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4199 * ffs(or) == 3, use the second.
4200 */
4201
4202 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4203 struct nvbios *bios = &dev_priv->vbios;
4204 int cv = bios->chip_version;
6ee73861
BS		 4205 uint16_t clktable = 0, scriptptr;
4206 uint32_t sel_clk_binding, sel_clk;
4207
4208 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4209 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4210 dcbent->location != DCB_LOC_ON_CHIP)
4211 return 0;
4212
4213 switch (ffs(dcbent->or)) {
4214 case 1:
4215 clktable = bios->tmds.output0_script_ptr;
4216 break;
4217 case 2:
4218 case 3:
4219 clktable = bios->tmds.output1_script_ptr;
4220 break;
4221 }
4222
4223 if (!clktable) {
4224 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4225 return -EINVAL;
4226 }
4227
4228 scriptptr = clkcmptable(bios, clktable, pxclk);
4229
4230 if (!scriptptr) {
4231 NV_ERROR(dev, "TMDS output init script not found\n");
4232 return -ENOENT;
4233 }
4234
4235 /* don't let script change pll->head binding */
4236 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4237 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4238 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4239 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4240
4241 return 0;
4242}
4243
6ee73861
BS		 4244static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
4245{
4246 /*
4247 * offset + 0 (8 bits): Micro version
4248 * offset + 1 (8 bits): Minor version
4249 * offset + 2 (8 bits): Chip version
4250 * offset + 3 (8 bits): Major version
4251 */
4252
4253 bios->major_version = bios->data[offset + 3];
04a39c57 4254 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 4255 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
4256 bios->data[offset + 3], bios->data[offset + 2],
4257 bios->data[offset + 1], bios->data[offset]);
4258}
4259
4260static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
4261{
4262 /*
4263 * Parses the init table segment for pointers used in script execution.
4264 *
4265 * offset + 0 (16 bits): init script tables pointer
4266 * offset + 2 (16 bits): macro index table pointer
4267 * offset + 4 (16 bits): macro table pointer
4268 * offset + 6 (16 bits): condition table pointer
4269 * offset + 8 (16 bits): io condition table pointer
4270 * offset + 10 (16 bits): io flag condition table pointer
4271 * offset + 12 (16 bits): init function table pointer
4272 */
4273
4274 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
4275 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
4276 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
4277 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
4278 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
4279 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
4280 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
4281}
4282
4283static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4284{
4285 /*
4286 * Parses the load detect values for g80 cards.
4287 *
4288 * offset + 0 (16 bits): loadval table pointer
4289 */
4290
4291 uint16_t load_table_ptr;
4292 uint8_t version, headerlen, entrylen, num_entries;
4293
4294 if (bitentry->length != 3) {
4295 NV_ERROR(dev, "Do not understand BIT A table\n");
4296 return -EINVAL;
4297 }
4298
4299 load_table_ptr = ROM16(bios->data[bitentry->offset]);
4300
4301 if (load_table_ptr == 0x0) {
1562ffde 4302 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
6ee73861
BS		 4303 return -EINVAL;
4304 }
4305
4306 version = bios->data[load_table_ptr];
4307
4308 if (version != 0x10) {
4309 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
4310 version >> 4, version & 0xF);
4311 return -ENOSYS;
4312 }
4313
4314 headerlen = bios->data[load_table_ptr + 1];
4315 entrylen = bios->data[load_table_ptr + 2];
4316 num_entries = bios->data[load_table_ptr + 3];
4317
4318 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
4319 NV_ERROR(dev, "Do not understand BIT loadval table\n");
4320 return -EINVAL;
4321 }
4322
4323 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 4324 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 4325
4326 return 0;
4327}
4328
4329static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4330{
4331 /*
4332 * offset + 8 (16 bits): PLL limits table pointer
4333 *
4334 * There's more in here, but that's unknown.
4335 */
4336
4337 if (bitentry->length < 10) {
4338 NV_ERROR(dev, "Do not understand BIT C table\n");
4339 return -EINVAL;
4340 }
4341
4342 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
4343
4344 return 0;
4345}
4346
4347static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4348{
4349 /*
4350 * Parses the flat panel table segment that the bit entry points to.
4351 * Starting at bitentry->offset:
4352 *
4353 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
4354 * records beginning with a freq.
4355 * offset + 2 (16 bits): mode table pointer
4356 */
4357
4358 if (bitentry->length != 4) {
4359 NV_ERROR(dev, "Do not understand BIT display table\n");
4360 return -EINVAL;
4361 }
4362
4363 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
4364
4365 return 0;
4366}
4367
4368static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4369{
4370 /*
4371 * Parses the init table segment that the bit entry points to.
4372 *
4373 * See parse_script_table_pointers for layout
4374 */
4375
4376 if (bitentry->length < 14) {
4377 NV_ERROR(dev, "Do not understand init table\n");
4378 return -EINVAL;
4379 }
4380
4381 parse_script_table_pointers(bios, bitentry->offset);
4382
4383 if (bitentry->length >= 16)
4384 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
4385 if (bitentry->length >= 18)
4386 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
4387
4388 return 0;
4389}
4390
4391static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4392{
4393 /*
4394 * BIT 'i' (info?) table
4395 *
4396 * offset + 0 (32 bits): BIOS version dword (as in B table)
4397 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
4398 * offset + 13 (16 bits): pointer to table containing DAC load
4399 * detection comparison values
4400 *
4401 * There's other things in the table, purpose unknown
4402 */
4403
4404 uint16_t daccmpoffset;
4405 uint8_t dacver, dacheaderlen;
4406
4407 if (bitentry->length < 6) {
4408 NV_ERROR(dev, "BIT i table too short for needed information\n");
4409 return -EINVAL;
4410 }
4411
4412 parse_bios_version(dev, bios, bitentry->offset);
4413
4414 /*
4415 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
4416 * Quadro identity crisis), other bits possibly as for BMP feature byte
4417 */
4418 bios->feature_byte = bios->data[bitentry->offset + 5];
4419 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
4420
4421 if (bitentry->length < 15) {
4422 NV_WARN(dev, "BIT i table not long enough for DAC load "
4423 "detection comparison table\n");
4424 return -EINVAL;
4425 }
4426
4427 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
4428
4429 /* doesn't exist on g80 */
4430 if (!daccmpoffset)
4431 return 0;
4432
4433 /*
4434 * The first value in the table, following the header, is the
4435 * comparison value, the second entry is a comparison value for
4436 * TV load detection.
4437 */
4438
4439 dacver = bios->data[daccmpoffset];
4440 dacheaderlen = bios->data[daccmpoffset + 1];
4441
4442 if (dacver != 0x00 && dacver != 0x10) {
4443 NV_WARN(dev, "DAC load detection comparison table version "
4444 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
4445 return -ENOSYS;
4446 }
4447
04a39c57
BS		 4448 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
4449 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 4450
4451 return 0;
4452}
4453
4454static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4455{
4456 /*
4457 * Parses the LVDS table segment that the bit entry points to.
4458 * Starting at bitentry->offset:
4459 *
4460 * offset + 0 (16 bits): LVDS strap xlate table pointer
4461 */
4462
4463 if (bitentry->length != 2) {
4464 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
4465 return -EINVAL;
4466 }
4467
4468 /*
4469 * No idea if it's still called the LVDS manufacturer table, but
4470 * the concept's close enough.
4471 */
4472 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
4473
4474 return 0;
4475}
4476
4477static int
4478parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4479 struct bit_entry *bitentry)
4480{
4481 /*
4482 * offset + 2 (8 bits): number of options in an
4483 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
4484 * offset + 3 (16 bits): pointer to strap xlate table for RAM
4485 * restrict option selection
4486 *
4487 * There's a bunch of bits in this table other than the RAM restrict
4488 * stuff that we don't use - their use currently unknown
4489 */
4490
6ee73861
BS		 4491 /*
4492 * Older bios versions don't have a sufficiently long table for
4493 * what we want
4494 */
4495 if (bitentry->length < 0x5)
4496 return 0;
4497
4709bff0 4498 if (bitentry->version < 2) {
37383650
MK		 4499 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
4500 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 4501 } else {
37383650
MK		 4502 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
4503 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 4504 }
4505
6ee73861
BS		 4506 return 0;
4507}
4508
4509static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
4510{
4511 /*
4512 * Parses the pointer to the TMDS table
4513 *
4514 * Starting at bitentry->offset:
4515 *
4516 * offset + 0 (16 bits): TMDS table pointer
4517 *
4518 * The TMDS table is typically found just before the DCB table, with a
4519 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
4520 * length?)
4521 *
4522 * At offset +7 is a pointer to a script, which I don't know how to
4523 * run yet.
4524 * At offset +9 is a pointer to another script, likewise
4525 * Offset +11 has a pointer to a table where the first word is a pxclk
4526 * frequency and the second word a pointer to a script, which should be
4527 * run if the comparison pxclk frequency is less than the pxclk desired.
4528 * This repeats for decreasing comparison frequencies
4529 * Offset +13 has a pointer to a similar table
4530 * The selection of table (and possibly +7/+9 script) is dictated by
4531 * "or" from the DCB.
4532 */
4533
4534 uint16_t tmdstableptr, script1, script2;
4535
4536 if (bitentry->length != 2) {
4537 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
4538 return -EINVAL;
4539 }
4540
4541 tmdstableptr = ROM16(bios->data[bitentry->offset]);
98720bf4 4542 if (!tmdstableptr) {
6ee73861
BS		 4543 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
4544 return -EINVAL;
4545 }
4546
98720bf4
BS		 4547 NV_INFO(dev, "TMDS table version %d.%d\n",
4548 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
4549
6ee73861 4550 /* nv50+ has v2.0, but we don't parse it atm */
98720bf4 4551 if (bios->data[tmdstableptr] != 0x11)
6ee73861 4552 return -ENOSYS;
6ee73861
BS		 4553
4554 /*
4555 * These two scripts are odd: they don't seem to get run even when
4556 * they are not stubbed.
4557 */
4558 script1 = ROM16(bios->data[tmdstableptr + 7]);
4559 script2 = ROM16(bios->data[tmdstableptr + 9]);
4560 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
4561 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
4562
4563 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
4564 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
4565
4566 return 0;
4567}
4568
4569static int
4570parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
4571 struct bit_entry *bitentry)
4572{
4573 /*
4574 * Parses the pointer to the G80 output script tables
4575 *
4576 * Starting at bitentry->offset:
4577 *
4578 * offset + 0 (16 bits): output script table pointer
4579 */
4580
4581 uint16_t outputscripttableptr;
4582
4583 if (bitentry->length != 3) {
4584 NV_ERROR(dev, "Do not understand BIT U table\n");
4585 return -EINVAL;
4586 }
4587
4588 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
4589 bios->display.script_table_ptr = outputscripttableptr;
4590 return 0;
4591}
4592
6ee73861
BS		 4593struct bit_table {
4594 const char id;
4595 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
4596};
4597
4598#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
4599
4709bff0
BS		 4600int
4601bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
4602{
4603 struct drm_nouveau_private *dev_priv = dev->dev_private;
4604 struct nvbios *bios = &dev_priv->vbios;
4605 u8 entries, *entry;
4606
b4c26818
BS		 4607 if (bios->type != NVBIOS_BIT)
4608 return -ENODEV;
4609
4709bff0
BS		 4610 entries = bios->data[bios->offset + 10];
4611 entry = &bios->data[bios->offset + 12];
4612 while (entries--) {
4613 if (entry[0] == id) {
4614 bit->id = entry[0];
4615 bit->version = entry[1];
4616 bit->length = ROM16(entry[2]);
4617 bit->offset = ROM16(entry[4]);
f9f9f536 4618 bit->data = ROMPTR(dev, entry[4]);
4709bff0
BS		 4619 return 0;
4620 }
4621
4622 entry += bios->data[bios->offset + 9];
4623 }
4624
4625 return -ENOENT;
4626}
4627
6ee73861
BS		 4628static int
4629parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
4630 struct bit_table *table)
4631{
4632 struct drm_device *dev = bios->dev;
6ee73861
BS		 4633 struct bit_entry bitentry;
4634
4709bff0 4635 if (bit_table(dev, table->id, &bitentry) == 0)
6ee73861 4636 return table->parse_fn(dev, bios, &bitentry);
6ee73861
BS		 4637
4638 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
4639 return -ENOSYS;
4640}
4641
4642static int
4643parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
4644{
4645 int ret;
4646
4647 /*
4648 * The only restriction on parsing order currently is having 'i' first
4649 * for use of bios->*_version or bios->feature_byte while parsing;
4650 * functions shouldn't be actually *doing* anything apart from pulling
4651 * data from the image into the bios struct, thus no interdependencies
4652 */
4653 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
4654 if (ret) /* info? */
4655 return ret;
4656 if (bios->major_version >= 0x60) /* g80+ */
4657 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
4658 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
4659 if (ret)
4660 return ret;
4661 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
4662 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
4663 if (ret)
4664 return ret;
4665 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
4666 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
4667 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
4668 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
6ee73861
BS		 4669
4670 return 0;
4671}
4672
4673static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
4674{
4675 /*
4676 * Parses the BMP structure for useful things, but does not act on them
4677 *
4678 * offset + 5: BMP major version
4679 * offset + 6: BMP minor version
4680 * offset + 9: BMP feature byte
4681 * offset + 10: BCD encoded BIOS version
4682 *
4683 * offset + 18: init script table pointer (for bios versions < 5.10h)
4684 * offset + 20: extra init script table pointer (for bios
4685 * versions < 5.10h)
4686 *
4687 * offset + 24: memory init table pointer (used on early bios versions)
4688 * offset + 26: SDR memory sequencing setup data table
4689 * offset + 28: DDR memory sequencing setup data table
4690 *
4691 * offset + 54: index of I2C CRTC pair to use for CRT output
4692 * offset + 55: index of I2C CRTC pair to use for TV output
4693 * offset + 56: index of I2C CRTC pair to use for flat panel output
4694 * offset + 58: write CRTC index for I2C pair 0
4695 * offset + 59: read CRTC index for I2C pair 0
4696 * offset + 60: write CRTC index for I2C pair 1
4697 * offset + 61: read CRTC index for I2C pair 1
4698 *
4699 * offset + 67: maximum internal PLL frequency (single stage PLL)
4700 * offset + 71: minimum internal PLL frequency (single stage PLL)
4701 *
4702 * offset + 75: script table pointers, as described in
4703 * parse_script_table_pointers
4704 *
4705 * offset + 89: TMDS single link output A table pointer
4706 * offset + 91: TMDS single link output B table pointer
4707 * offset + 95: LVDS single link output A table pointer
4708 * offset + 105: flat panel timings table pointer
4709 * offset + 107: flat panel strapping translation table pointer
4710 * offset + 117: LVDS manufacturer panel config table pointer
4711 * offset + 119: LVDS manufacturer strapping translation table pointer
4712 *
4713 * offset + 142: PLL limits table pointer
4714 *
4715 * offset + 156: minimum pixel clock for LVDS dual link
4716 */
4717
4718 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
4719 uint16_t bmplength;
4720 uint16_t legacy_scripts_offset, legacy_i2c_offset;
4721
4722 /* load needed defaults in case we can't parse this info */
04a39c57 4723 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 4724 bios->fmaxvco = 256000;
4725 bios->fminvco = 128000;
4726 bios->fp.duallink_transition_clk = 90000;
4727
4728 bmp_version_major = bmp[5];
4729 bmp_version_minor = bmp[6];
4730
4731 NV_TRACE(dev, "BMP version %d.%d\n",
4732 bmp_version_major, bmp_version_minor);
4733
4734 /*
4735 * Make sure that 0x36 is blank and can't be mistaken for a DCB
4736 * pointer on early versions
4737 */
4738 if (bmp_version_major < 5)
4739 *(uint16_t *)&bios->data[0x36] = 0;
4740
4741 /*
4742 * Seems that the minor version was 1 for all major versions prior
4743 * to 5. Version 6 could theoretically exist, but I suspect BIT
4744 * happened instead.
4745 */
4746 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
4747 NV_ERROR(dev, "You have an unsupported BMP version. "
4748 "Please send in your bios\n");
4749 return -ENOSYS;
4750 }
4751
4752 if (bmp_version_major == 0)
4753 /* nothing that's currently useful in this version */
4754 return 0;
4755 else if (bmp_version_major == 1)
4756 bmplength = 44; /* exact for 1.01 */
4757 else if (bmp_version_major == 2)
4758 bmplength = 48; /* exact for 2.01 */
4759 else if (bmp_version_major == 3)
4760 bmplength = 54;
4761 /* guessed - mem init tables added in this version */
4762 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
4763 /* don't know if 5.0 exists... */
4764 bmplength = 62;
4765 /* guessed - BMP I2C indices added in version 4*/
4766 else if (bmp_version_minor < 0x6)
4767 bmplength = 67; /* exact for 5.01 */
4768 else if (bmp_version_minor < 0x10)
4769 bmplength = 75; /* exact for 5.06 */
4770 else if (bmp_version_minor == 0x10)
4771 bmplength = 89; /* exact for 5.10h */
4772 else if (bmp_version_minor < 0x14)
4773 bmplength = 118; /* exact for 5.11h */
4774 else if (bmp_version_minor < 0x24)
4775 /*
4776 * Not sure of version where pll limits came in;
4777 * certainly exist by 0x24 though.
4778 */
4779 /* length not exact: this is long enough to get lvds members */
4780 bmplength = 123;
4781 else if (bmp_version_minor < 0x27)
4782 /*
4783 * Length not exact: this is long enough to get pll limit
4784 * member
4785 */
4786 bmplength = 144;
4787 else
4788 /*
4789 * Length not exact: this is long enough to get dual link
4790 * transition clock.
4791 */
4792 bmplength = 158;
4793
4794 /* checksum */
4795 if (nv_cksum(bmp, 8)) {
4796 NV_ERROR(dev, "Bad BMP checksum\n");
4797 return -EINVAL;
4798 }
4799
4800 /*
4801 * Bit 4 seems to indicate either a mobile bios or a quadro card --
4802 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
4803 * (not nv10gl), bit 5 that the flat panel tables are present, and
4804 * bit 6 a tv bios.
4805 */
4806 bios->feature_byte = bmp[9];
4807
4808 parse_bios_version(dev, bios, offset + 10);
4809
4810 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
4811 bios->old_style_init = true;
4812 legacy_scripts_offset = 18;
4813 if (bmp_version_major < 2)
4814 legacy_scripts_offset -= 4;
4815 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
4816 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
4817
4818 if (bmp_version_major > 2) { /* appears in BMP 3 */
4819 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
4820 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
4821 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
4822 }
4823
4824 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
4825 if (bmplength > 61)
4826 legacy_i2c_offset = offset + 54;
4827 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
4828 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
4829 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
6ee73861
BS		 4830
4831 if (bmplength > 74) {
4832 bios->fmaxvco = ROM32(bmp[67]);
4833 bios->fminvco = ROM32(bmp[71]);
4834 }
4835 if (bmplength > 88)
4836 parse_script_table_pointers(bios, offset + 75);
4837 if (bmplength > 94) {
4838 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
4839 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
4840 /*
4841 * Never observed in use with lvds scripts, but is reused for
4842 * 18/24 bit panel interface default for EDID equipped panels
4843 * (if_is_24bit not set directly to avoid any oscillation).
4844 */
4845 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
4846 }
4847 if (bmplength > 108) {
4848 bios->fp.fptablepointer = ROM16(bmp[105]);
4849 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
4850 bios->fp.xlatwidth = 1;
4851 }
4852 if (bmplength > 120) {
4853 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
4854 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
4855 }
4856 if (bmplength > 143)
4857 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
4858
4859 if (bmplength > 157)
4860 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
4861
4862 return 0;
4863}
4864
4865static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
4866{
4867 int i, j;
4868
4869 for (i = 0; i <= (n - len); i++) {
4870 for (j = 0; j < len; j++)
4871 if (data[i + j] != str[j])
4872 break;
4873 if (j == len)
4874 return i;
4875 }
4876
4877 return 0;
4878}
4879
6b5a81a2 4880void *
e0996aea 4881olddcb_table(struct drm_device *dev)
6b5a81a2
BS		 4882{
4883 struct drm_nouveau_private *dev_priv = dev->dev_private;
4884 u8 *dcb = NULL;
4885
4886 if (dev_priv->card_type > NV_04)
4887 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]);
4888 if (!dcb) {
4889 NV_WARNONCE(dev, "No DCB data found in VBIOS\n");
4890 return NULL;
4891 }
4892
4893 if (dcb[0] >= 0x41) {
4894 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]);
4895 return NULL;
4896 } else
4897 if (dcb[0] >= 0x30) {
4898 if (ROM32(dcb[6]) == 0x4edcbdcb)
4899 return dcb;
4900 } else
4901 if (dcb[0] >= 0x20) {
4902 if (ROM32(dcb[4]) == 0x4edcbdcb)
4903 return dcb;
4904 } else
4905 if (dcb[0] >= 0x15) {
4906 if (!memcmp(&dcb[-7], "DEV_REC", 7))
4907 return dcb;
4908 } else {
4909 /*
4910 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but
4911 * always has the same single (crt) entry, even when tv-out
4912 * present, so the conclusion is this version cannot really
4913 * be used.
4914 *
4915 * v1.2 tables (some NV6/10, and NV15+) normally have the
4916 * same 5 entries, which are not specific to the card and so
4917 * no use.
4918 *
4919 * v1.2 does have an I2C table that read_dcb_i2c_table can
4920 * handle, but cards exist (nv11 in #14821) with a bad i2c
4921 * table pointer, so use the indices parsed in
4922 * parse_bmp_structure.
4923 *
4924 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
4925 */
4926 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n");
4927 return NULL;
4928 }
4929
4930 NV_WARNONCE(dev, "DCB header validation failed\n");
4931 return NULL;
4932}
4933
b4c26818 4934void *
e0996aea 4935olddcb_outp(struct drm_device *dev, u8 idx)
6b5a81a2 4936{
e0996aea 4937 u8 *dcb = olddcb_table(dev);
6b5a81a2
BS		 4938 if (dcb && dcb[0] >= 0x30) {
4939 if (idx < dcb[2])
4940 return dcb + dcb[1] + (idx * dcb[3]);
4941 } else
4942 if (dcb && dcb[0] >= 0x20) {
4943 u8 *i2c = ROMPTR(dev, dcb[2]);
4944 u8 *ent = dcb + 8 + (idx * 8);
4945 if (i2c && ent < i2c)
4946 return ent;
4947 } else
4948 if (dcb && dcb[0] >= 0x15) {
4949 u8 *i2c = ROMPTR(dev, dcb[2]);
4950 u8 *ent = dcb + 4 + (idx * 10);
4951 if (i2c && ent < i2c)
4952 return ent;
4953 }
4954
4955 return NULL;
4956}
4957
4958int
e0996aea 4959olddcb_outp_foreach(struct drm_device *dev, void *data,
6b5a81a2
BS		 4960 int (*exec)(struct drm_device *, void *, int idx, u8 *outp))
4961{
4962 int ret, idx = -1;
4963 u8 *outp = NULL;
e0996aea 4964 while ((outp = olddcb_outp(dev, ++idx))) {
6b5a81a2
BS		 4965 if (ROM32(outp[0]) == 0x00000000)
4966 break; /* seen on an NV11 with DCB v1.5 */
4967 if (ROM32(outp[0]) == 0xffffffff)
4968 break; /* seen on an NV17 with DCB v2.0 */
4969
4970 if ((outp[0] & 0x0f) == OUTPUT_UNUSED)
4971 continue;
4972 if ((outp[0] & 0x0f) == OUTPUT_EOL)
4973 break;
4974
4975 ret = exec(dev, data, idx, outp);
4976 if (ret)
4977 return ret;
4978 }
4979
4980 return 0;
4981}
4982
befb51e9
BS		 4983u8 *
4984dcb_conntab(struct drm_device *dev)
4985{
e0996aea 4986 u8 *dcb = olddcb_table(dev);
befb51e9
BS		 4987 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) {
4988 u8 *conntab = ROMPTR(dev, dcb[0x14]);
4989 if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40)
4990 return conntab;
4991 }
4992 return NULL;
4993}
4994
4995u8 *
4996dcb_conn(struct drm_device *dev, u8 idx)
4997{
4998 u8 *conntab = dcb_conntab(dev);
4999 if (conntab && idx < conntab[2])
5000 return conntab + conntab[1] + (idx * conntab[3]);
5001 return NULL;
5002}
5003
7f245b20 5004static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5005{
5006 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5007
5008 memset(entry, 0, sizeof(struct dcb_entry));
5009 entry->index = dcb->entries++;
5010
5011 return entry;
5012}
5013
2e5702af
FJ		 5014static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
5015 int heads, int or)
6ee73861
BS		 5016{
5017 struct dcb_entry *entry = new_dcb_entry(dcb);
5018
2e5702af 5019 entry->type = type;
6ee73861
BS		 5020 entry->i2c_index = i2c;
5021 entry->heads = heads;
2e5702af
FJ		 5022 if (type != OUTPUT_ANALOG)
5023 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5024 entry->or = or;
6ee73861
BS		 5025}
5026
5027static bool
7f245b20 5028parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5029 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5030{
5031 entry->type = conn & 0xf;
5032 entry->i2c_index = (conn >> 4) & 0xf;
5033 entry->heads = (conn >> 8) & 0xf;
befb51e9 5034 entry->connector = (conn >> 12) & 0xf;
6ee73861
BS		 5035 entry->bus = (conn >> 16) & 0xf;
5036 entry->location = (conn >> 20) & 0x3;
5037 entry->or = (conn >> 24) & 0xf;
6ee73861
BS		 5038
5039 switch (entry->type) {
5040 case OUTPUT_ANALOG:
5041 /*
5042 * Although the rest of a CRT conf dword is usually
5043 * zeros, mac biosen have stuff there so we must mask
5044 */
7f245b20 5045 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5046 (conf & 0xffff) * 10 :
5047 (conf & 0xff) * 10000;
5048 break;
5049 case OUTPUT_LVDS:
5050 {
5051 uint32_t mask;
5052 if (conf & 0x1)
5053 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5054 if (dcb->version < 0x22) {
6ee73861
BS		 5055 mask = ~0xd;
5056 /*
5057 * The laptop in bug 14567 lies and claims to not use
5058 * straps when it does, so assume all DCB 2.0 laptops
5059 * use straps, until a broken EDID using one is produced
5060 */
5061 entry->lvdsconf.use_straps_for_mode = true;
5062 /*
5063 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5064 * mean the same thing (probably wrong, but might work)
5065 */
5066 if (conf & 0x4 || conf & 0x8)
5067 entry->lvdsconf.use_power_scripts = true;
5068 } else {
a6ed76d7
BS		 5069 mask = ~0x7;
5070 if (conf & 0x2)
5071 entry->lvdsconf.use_acpi_for_edid = true;
6ee73861
BS		 5072 if (conf & 0x4)
5073 entry->lvdsconf.use_power_scripts = true;
c5875470 5074 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6ee73861
BS		 5075 }
5076 if (conf & mask) {
5077 /*
5078 * Until we even try to use these on G8x, it's
5079 * useless reporting unknown bits. They all are.
5080 */
7f245b20 5081 if (dcb->version >= 0x40)
6ee73861
BS		 5082 break;
5083
5084 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5085 "please report\n");
5086 }
5087 break;
5088 }
5089 case OUTPUT_TV:
5090 {
7f245b20 5091 if (dcb->version >= 0x30)
6ee73861
BS		 5092 entry->tvconf.has_component_output = conf & (0x8 << 4);
5093 else
5094 entry->tvconf.has_component_output = false;
5095
5096 break;
5097 }
5098 case OUTPUT_DP:
5099 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
75a1fccf
BS		 5100 switch ((conf & 0x00e00000) >> 21) {
5101 case 0:
5102 entry->dpconf.link_bw = 162000;
5103 break;
5104 default:
5105 entry->dpconf.link_bw = 270000;
5106 break;
5107 }
6ee73861
BS		 5108 switch ((conf & 0x0f000000) >> 24) {
5109 case 0xf:
5110 entry->dpconf.link_nr = 4;
5111 break;
5112 case 0x3:
5113 entry->dpconf.link_nr = 2;
5114 break;
5115 default:
5116 entry->dpconf.link_nr = 1;
5117 break;
5118 }
5119 break;
5120 case OUTPUT_TMDS:
27d50fcc
FJ		 5121 if (dcb->version >= 0x40)
5122 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
4a9f822f
FJ		 5123 else if (dcb->version >= 0x30)
5124 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
27d50fcc
FJ		 5125 else if (dcb->version >= 0x22)
5126 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
4a9f822f 5127
6ee73861 5128 break;
44a1246f 5129 case OUTPUT_EOL:
6ee73861 5130 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 5131 dcb->entries--;
6ee73861 5132 return false;
e7cc51c5
BS		 5133 default:
5134 break;
6ee73861
BS		 5135 }
5136
23484874
BS		 5137 if (dcb->version < 0x40) {
5138 /* Normal entries consist of a single bit, but dual link has
5139 * the next most significant bit set too
5140 */
5141 entry->duallink_possible =
5142 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
5143 } else {
5144 entry->duallink_possible = (entry->sorconf.link == 3);
5145 }
5146
6ee73861
BS		 5147 /* unsure what DCB version introduces this, 3.0? */
5148 if (conf & 0x100000)
5149 entry->i2c_upper_default = true;
5150
5151 return true;
5152}
5153
5154static bool
7f245b20 5155parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5156 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5157{
b0d2de86
BS		 5158 switch (conn & 0x0000000f) {
5159 case 0:
5160 entry->type = OUTPUT_ANALOG;
5161 break;
5162 case 1:
5163 entry->type = OUTPUT_TV;
5164 break;
5165 case 2:
b0d2de86 5166 case 4:
fba67528 5167 if (conn & 0x10)
b0d2de86 5168 entry->type = OUTPUT_LVDS;
fba67528
FJ		 5169 else
5170 entry->type = OUTPUT_TMDS;
5171 break;
5172 case 3:
5173 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 5174 break;
5175 default:
5176 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
5177 return false;
6ee73861 5178 }
b0d2de86
BS		 5179
5180 entry->i2c_index = (conn & 0x0003c000) >> 14;
5181 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
5182 entry->or = entry->heads; /* same as heads, hopefully safe enough */
5183 entry->location = (conn & 0x01e00000) >> 21;
5184 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 5185 entry->duallink_possible = false;
5186
5187 switch (entry->type) {
5188 case OUTPUT_ANALOG:
5189 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
5190 break;
b0d2de86
BS		 5191 case OUTPUT_TV:
5192 entry->tvconf.has_component_output = false;
6ee73861 5193 break;
b0d2de86 5194 case OUTPUT_LVDS:
77b1d5dc 5195 if ((conn & 0x00003f00) >> 8 != 0x10)
b0d2de86
BS		 5196 entry->lvdsconf.use_straps_for_mode = true;
5197 entry->lvdsconf.use_power_scripts = true;
5198 break;
5199 default:
6ee73861
BS		 5200 break;
5201 }
5202
5203 return true;
5204}
5205
6ee73861 5206static
7f245b20 5207void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 5208{
5209 /*
5210 * DCB v2.0 lists each output combination separately.
5211 * Here we merge compatible entries to have fewer outputs, with
5212 * more options
5213 */
5214
5215 int i, newentries = 0;
5216
5217 for (i = 0; i < dcb->entries; i++) {
5218 struct dcb_entry *ient = &dcb->entry[i];
5219 int j;
5220
5221 for (j = i + 1; j < dcb->entries; j++) {
5222 struct dcb_entry *jent = &dcb->entry[j];
5223
5224 if (jent->type == 100) /* already merged entry */
5225 continue;
5226
5227 /* merge heads field when all other fields the same */
5228 if (jent->i2c_index == ient->i2c_index &&
5229 jent->type == ient->type &&
5230 jent->location == ient->location &&
5231 jent->or == ient->or) {
5232 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
5233 i, j);
5234 ient->heads |= jent->heads;
5235 jent->type = 100; /* dummy value */
5236 }
5237 }
5238 }
5239
5240 /* Compact entries merged into others out of dcb */
5241 for (i = 0; i < dcb->entries; i++) {
5242 if (dcb->entry[i].type == 100)
5243 continue;
5244
5245 if (newentries != i) {
5246 dcb->entry[newentries] = dcb->entry[i];
5247 dcb->entry[newentries].index = newentries;
5248 }
5249 newentries++;
5250 }
5251
5252 dcb->entries = newentries;
5253}
5254
df4cf1b7
BS		 5255static bool
5256apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
5257{
670820c0
FJ		 5258 struct drm_nouveau_private *dev_priv = dev->dev_private;
5259 struct dcb_table *dcb = &dev_priv->vbios.dcb;
5260
df4cf1b7
BS		 5261 /* Dell Precision M6300
5262 * DCB entry 2: 02025312 00000010
5263 * DCB entry 3: 02026312 00000020
5264 *
5265 * Identical, except apparently a different connector on a
5266 * different SOR link. Not a clue how we're supposed to know
5267 * which one is in use if it even shares an i2c line...
5268 *
5269 * Ignore the connector on the second SOR link to prevent
5270 * nasty problems until this is sorted (assuming it's not a
5271 * VBIOS bug).
5272 */
acae116c 5273 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
df4cf1b7
BS		 5274 if (*conn == 0x02026312 && *conf == 0x00000020)
5275 return false;
5276 }
5277
670820c0
FJ		 5278 /* GeForce3 Ti 200
5279 *
5280 * DCB reports an LVDS output that should be TMDS:
5281 * DCB entry 1: f2005014 ffffffff
5282 */
5283 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
5284 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
5285 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
5286 return false;
5287 }
5288 }
5289
c0929b49
BS		 5290 /* XFX GT-240X-YA
5291 *
5292 * So many things wrong here, replace the entire encoder table..
5293 */
5294 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
5295 if (idx == 0) {
5296 *conn = 0x02001300; /* VGA, connector 1 */
5297 *conf = 0x00000028;
5298 } else
5299 if (idx == 1) {
5300 *conn = 0x01010312; /* DVI, connector 0 */
5301 *conf = 0x00020030;
5302 } else
5303 if (idx == 2) {
5304 *conn = 0x01010310; /* VGA, connector 0 */
5305 *conf = 0x00000028;
5306 } else
5307 if (idx == 3) {
5308 *conn = 0x02022362; /* HDMI, connector 2 */
5309 *conf = 0x00020010;
5310 } else {
5311 *conn = 0x0000000e; /* EOL */
5312 *conf = 0x00000000;
5313 }
5314 }
5315
e540afc3
BS		 5316 /* Some other twisted XFX board (rhbz#694914)
5317 *
5318 * The DVI/VGA encoder combo that's supposed to represent the
5319 * DVI-I connector actually point at two different ones, and
5320 * the HDMI connector ends up paired with the VGA instead.
5321 *
5322 * Connector table is missing anything for VGA at all, pointing it
5323 * an invalid conntab entry 2 so we figure it out ourself.
5324 */
5325 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
5326 if (idx == 0) {
5327 *conn = 0x02002300; /* VGA, connector 2 */
5328 *conf = 0x00000028;
5329 } else
5330 if (idx == 1) {
5331 *conn = 0x01010312; /* DVI, connector 0 */
5332 *conf = 0x00020030;
5333 } else
5334 if (idx == 2) {
5335 *conn = 0x04020310; /* VGA, connector 0 */
5336 *conf = 0x00000028;
5337 } else
5338 if (idx == 3) {
5339 *conn = 0x02021322; /* HDMI, connector 1 */
5340 *conf = 0x00020010;
5341 } else {
5342 *conn = 0x0000000e; /* EOL */
5343 *conf = 0x00000000;
5344 }
5345 }
5346
16fde6cd
BS		 5347 /* fdo#50830: connector indices for VGA and DVI-I are backwards */
5348 if (nv_match_device(dev, 0x0421, 0x3842, 0xc793)) {
5349 if (idx == 0 && *conn == 0x02000300)
5350 *conn = 0x02011300;
5351 else
5352 if (idx == 1 && *conn == 0x04011310)
5353 *conn = 0x04000310;
5354 else
5355 if (idx == 2 && *conn == 0x02011312)
5356 *conn = 0x02000312;
5357 }
5358
df4cf1b7
BS		 5359 return true;
5360}
5361
2e5702af
FJ		 5362static void
5363fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
5364{
5365 struct dcb_table *dcb = &bios->dcb;
5366 int all_heads = (nv_two_heads(dev) ? 3 : 1);
5367
5368#ifdef __powerpc__
5369 /* Apple iMac G4 NV17 */
5370 if (of_machine_is_compatible("PowerMac4,5")) {
5371 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
5372 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
5373 return;
5374 }
5375#endif
5376
5377 /* Make up some sane defaults */
0f8067c7
BS		 5378 fabricate_dcb_output(dcb, OUTPUT_ANALOG,
5379 bios->legacy.i2c_indices.crt, 1, 1);
2e5702af
FJ		 5380
5381 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
0f8067c7
BS		 5382 fabricate_dcb_output(dcb, OUTPUT_TV,
5383 bios->legacy.i2c_indices.tv,
2e5702af
FJ		 5384 all_heads, 0);
5385
5386 else if (bios->tmds.output0_script_ptr ||
5387 bios->tmds.output1_script_ptr)
0f8067c7
BS		 5388 fabricate_dcb_output(dcb, OUTPUT_TMDS,
5389 bios->legacy.i2c_indices.panel,
2e5702af
FJ		 5390 all_heads, 1);
5391}
5392
ed42f824 5393static int
6b5a81a2 5394parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
6ee73861 5395{
ed42f824 5396 struct drm_nouveau_private *dev_priv = dev->dev_private;
6b5a81a2
BS		 5397 struct dcb_table *dcb = &dev_priv->vbios.dcb;
5398 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]);
5399 u32 conn = ROM32(outp[0]);
5400 bool ret;
6ee73861 5401
6b5a81a2
BS		 5402 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) {
5403 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861 5404
befb51e9 5405 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf);
6ee73861 5406
6b5a81a2
BS		 5407 if (dcb->version >= 0x20)
5408 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
5409 else
5410 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
5411 if (!ret)
5412 return 1; /* stop parsing */
befb51e9
BS		 5413
5414 /* Ignore the I2C index for on-chip TV-out, as there
5415 * are cards with bogus values (nv31m in bug 23212),
5416 * and it's otherwise useless.
5417 */
5418 if (entry->type == OUTPUT_TV &&
5419 entry->location == DCB_LOC_ON_CHIP)
5420 entry->i2c_index = 0x0f;
6b5a81a2 5421 }
6ee73861 5422
6b5a81a2
BS		 5423 return 0;
5424}
6ee73861 5425
befb51e9
BS		 5426static void
5427dcb_fake_connectors(struct nvbios *bios)
5428{
5429 struct dcb_table *dcbt = &bios->dcb;
5430 u8 map[16] = { };
5431 int i, idx = 0;
5432
5433 /* heuristic: if we ever get a non-zero connector field, assume
5434 * that all the indices are valid and we don't need fake them.
5206b524
BS		 5435 *
5436 * and, as usual, a blacklist of boards with bad bios data..
befb51e9 5437 */
5206b524
BS		 5438 if (!nv_match_device(bios->dev, 0x0392, 0x107d, 0x20a2)) {
5439 for (i = 0; i < dcbt->entries; i++) {
5440 if (dcbt->entry[i].connector)
5441 return;
5442 }
befb51e9
BS		 5443 }
5444
5445 /* no useful connector info available, we need to make it up
5446 * ourselves. the rule here is: anything on the same i2c bus
5447 * is considered to be on the same connector. any output
5448 * without an associated i2c bus is assigned its own unique
5449 * connector index.
5450 */
5451 for (i = 0; i < dcbt->entries; i++) {
5452 u8 i2c = dcbt->entry[i].i2c_index;
5453 if (i2c == 0x0f) {
5454 dcbt->entry[i].connector = idx++;
5455 } else {
5456 if (!map[i2c])
5457 map[i2c] = ++idx;
5458 dcbt->entry[i].connector = map[i2c] - 1;
5459 }
5460 }
5461
5462 /* if we created more than one connector, destroy the connector
5463 * table - just in case it has random, rather than stub, entries.
5464 */
5465 if (i > 1) {
5466 u8 *conntab = dcb_conntab(bios->dev);
5467 if (conntab)
5468 conntab[0] = 0x00;
5469 }
5470}
5471
6b5a81a2
BS		 5472static int
5473parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
5474{
5475 struct dcb_table *dcb = &bios->dcb;
befb51e9
BS		 5476 u8 *dcbt, *conn;
5477 int idx;
6b5a81a2 5478
e0996aea 5479 dcbt = olddcb_table(dev);
6b5a81a2
BS		 5480 if (!dcbt) {
5481 /* handle pre-DCB boards */
5482 if (bios->type == NVBIOS_BMP) {
5483 fabricate_dcb_encoder_table(dev, bios);
5484 return 0;
6ee73861
BS		 5485 }
5486
6b5a81a2
BS		 5487 return -EINVAL;
5488 }
6ee73861 5489
6b5a81a2 5490 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf);
6ee73861 5491
6b5a81a2 5492 dcb->version = dcbt[0];
e0996aea 5493 olddcb_outp_foreach(dev, NULL, parse_dcb_entry);
6ee73861
BS		 5494
5495 /*
5496 * apart for v2.1+ not being known for requiring merging, this
5497 * guarantees dcbent->index is the index of the entry in the rom image
5498 */
7f245b20 5499 if (dcb->version < 0x21)
6ee73861
BS		 5500 merge_like_dcb_entries(dev, dcb);
5501
54abb5dd
BS		 5502 if (!dcb->entries)
5503 return -ENXIO;
5504
befb51e9
BS		 5505 /* dump connector table entries to log, if any exist */
5506 idx = -1;
5507 while ((conn = dcb_conn(dev, ++idx))) {
5508 if (conn[0] != 0xff) {
5509 NV_TRACE(dev, "DCB conn %02d: ", idx);
5510 if (dcb_conntab(dev)[3] < 4)
5511 printk("%04x\n", ROM16(conn[0]));
5512 else
5513 printk("%08x\n", ROM32(conn[0]));
6ee73861 5514 }
6ee73861 5515 }
befb51e9 5516 dcb_fake_connectors(bios);
befb51e9 5517 return 0;
6ee73861
BS		 5518}
5519
6ee73861
BS		 5520static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
5521{
5522 /*
5523 * The header following the "HWSQ" signature has the number of entries,
5524 * and the entry size
5525 *
5526 * An entry consists of a dword to write to the sequencer control reg
5527 * (0x00001304), followed by the ucode bytes, written sequentially,
5528 * starting at reg 0x00001400
5529 */
5530
5531 uint8_t bytes_to_write;
5532 uint16_t hwsq_entry_offset;
5533 int i;
5534
5535 if (bios->data[hwsq_offset] <= entry) {
5536 NV_ERROR(dev, "Too few entries in HW sequencer table for "
5537 "requested entry\n");
5538 return -ENOENT;
5539 }
5540
5541 bytes_to_write = bios->data[hwsq_offset + 1];
5542
5543 if (bytes_to_write != 36) {
5544 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
5545 return -EINVAL;
5546 }
5547
5548 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
5549
5550 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
5551
5552 /* set sequencer control */
5553 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
5554 bytes_to_write -= 4;
5555
5556 /* write ucode */
5557 for (i = 0; i < bytes_to_write; i += 4)
5558 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
5559
5560 /* twiddle NV_PBUS_DEBUG_4 */
5561 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
5562
5563 return 0;
5564}
5565
5566static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
5567 struct nvbios *bios)
5568{
5569 /*
5570 * BMP based cards, from NV17, need a microcode loading to correctly
5571 * control the GPIO etc for LVDS panels
5572 *
5573 * BIT based cards seem to do this directly in the init scripts
5574 *
5575 * The microcode entries are found by the "HWSQ" signature.
5576 */
5577
5578 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
5579 const int sz = sizeof(hwsq_signature);
5580 int hwsq_offset;
5581
5582 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
5583 if (!hwsq_offset)
5584 return 0;
5585
5586 /* always use entry 0? */
5587 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
5588}
5589
5590uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
5591{
5592 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5593 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5594 const uint8_t edid_sig[] = {
5595 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
5596 uint16_t offset = 0;
5597 uint16_t newoffset;
5598 int searchlen = NV_PROM_SIZE;
5599
5600 if (bios->fp.edid)
5601 return bios->fp.edid;
5602
5603 while (searchlen) {
5604 newoffset = findstr(&bios->data[offset], searchlen,
5605 edid_sig, 8);
5606 if (!newoffset)
5607 return NULL;
5608 offset += newoffset;
5609 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
5610 break;
5611
5612 searchlen -= offset;
5613 offset++;
5614 }
5615
5616 NV_TRACE(dev, "Found EDID in BIOS\n");
5617
5618 return bios->fp.edid = &bios->data[offset];
5619}
5620
5621void
5622nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
02e4f587 5623 struct dcb_entry *dcbent, int crtc)
6ee73861
BS		 5624{
5625 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5626 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5627 struct init_exec iexec = { true, false };
5628
c7ca4d1b 5629 spin_lock_bh(&bios->lock);
6ee73861 5630 bios->display.output = dcbent;
02e4f587 5631 bios->display.crtc = crtc;
6ee73861
BS		 5632 parse_init_table(bios, table, &iexec);
5633 bios->display.output = NULL;
c7ca4d1b 5634 spin_unlock_bh(&bios->lock);
6ee73861
BS		 5635}
5636
59ef9742
BS		 5637void
5638nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
5639{
5640 struct drm_nouveau_private *dev_priv = dev->dev_private;
5641 struct nvbios *bios = &dev_priv->vbios;
5642 struct init_exec iexec = { true, false };
5643
5644 parse_init_table(bios, table, &iexec);
5645}
5646
6ee73861
BS		 5647static bool NVInitVBIOS(struct drm_device *dev)
5648{
5649 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5650 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5651
5652 memset(bios, 0, sizeof(struct nvbios));
c7ca4d1b 5653 spin_lock_init(&bios->lock);
6ee73861
BS		 5654 bios->dev = dev;
5655
cd42439d 5656 return _nv_bios(dev, &bios->data, &bios->length);
6ee73861
BS		 5657}
5658
5659static int nouveau_parse_vbios_struct(struct drm_device *dev)
5660{
5661 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5662 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5663 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
5664 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
5665 int offset;
5666
5667 offset = findstr(bios->data, bios->length,
5668 bit_signature, sizeof(bit_signature));
5669 if (offset) {
5670 NV_TRACE(dev, "BIT BIOS found\n");
4709bff0
BS		 5671 bios->type = NVBIOS_BIT;
5672 bios->offset = offset;
6ee73861
BS		 5673 return parse_bit_structure(bios, offset + 6);
5674 }
5675
5676 offset = findstr(bios->data, bios->length,
5677 bmp_signature, sizeof(bmp_signature));
5678 if (offset) {
5679 NV_TRACE(dev, "BMP BIOS found\n");
4709bff0
BS		 5680 bios->type = NVBIOS_BMP;
5681 bios->offset = offset;
6ee73861
BS		 5682 return parse_bmp_structure(dev, bios, offset);
5683 }
5684
5685 NV_ERROR(dev, "No known BIOS signature found\n");
5686 return -ENODEV;
5687}
5688
5689int
5690nouveau_run_vbios_init(struct drm_device *dev)
5691{
5692 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5693 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5694 int i, ret = 0;
5695
946fd35f
FJ		 5696 /* Reset the BIOS head to 0. */
5697 bios->state.crtchead = 0;
6ee73861
BS		 5698
5699 if (bios->major_version < 5) /* BMP only */
5700 load_nv17_hw_sequencer_ucode(dev, bios);
5701
5702 if (bios->execute) {
5703 bios->fp.last_script_invoc = 0;
5704 bios->fp.lvds_init_run = false;
5705 }
5706
5707 parse_init_tables(bios);
5708
5709 /*
5710 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
5711 * parser will run this right after the init tables, the binary
5712 * driver appears to run it at some point later.
5713 */
5714 if (bios->some_script_ptr) {
5715 struct init_exec iexec = {true, false};
5716
5717 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
5718 bios->some_script_ptr);
5719 parse_init_table(bios, bios->some_script_ptr, &iexec);
5720 }
5721
5722 if (dev_priv->card_type >= NV_50) {
7f245b20 5723 for (i = 0; i < bios->dcb.entries; i++) {
02e4f587
BS		 5724 nouveau_bios_run_display_table(dev, 0, 0,
5725 &bios->dcb.entry[i], -1);
6ee73861
BS		 5726 }
5727 }
5728
6ee73861
BS		 5729 return ret;
5730}
5731
d13102c6
BS		 5732static bool
5733nouveau_bios_posted(struct drm_device *dev)
5734{
5735 struct drm_nouveau_private *dev_priv = dev->dev_private;
d13102c6
BS		 5736 unsigned htotal;
5737
c1b60ece 5738 if (dev_priv->card_type >= NV_50) {
d13102c6
BS		 5739 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
5740 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
5741 return false;
5742 return true;
5743 }
5744
d13102c6
BS		 5745 htotal = NVReadVgaCrtc(dev, 0, 0x06);
5746 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
5747 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
5748 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
5749 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
03cd06ca 5750
d13102c6
BS		 5751 return (htotal != 0);
5752}
5753
6ee73861
BS		 5754int
5755nouveau_bios_init(struct drm_device *dev)
5756{
5757 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5758 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5759 int ret;
5760
6ee73861
BS		 5761 if (!NVInitVBIOS(dev))
5762 return -ENODEV;
5763
5764 ret = nouveau_parse_vbios_struct(dev);
5765 if (ret)
5766 return ret;
5767
b4c26818
BS		 5768 ret = nouveau_mxm_init(dev);
5769 if (ret)
5770 return ret;
5771
2e5702af 5772 ret = parse_dcb_table(dev, bios);
6ee73861
BS		 5773 if (ret)
5774 return ret;
5775
6ee73861
BS		 5776 if (!bios->major_version) /* we don't run version 0 bios */
5777 return 0;
5778
6ee73861
BS		 5779 /* init script execution disabled */
5780 bios->execute = false;
5781
5782 /* ... unless card isn't POSTed already */
d13102c6 5783 if (!nouveau_bios_posted(dev)) {
67eda20e
FJ		 5784 NV_INFO(dev, "Adaptor not initialised, "
5785 "running VBIOS init tables.\n");
6ee73861
BS		 5786 bios->execute = true;
5787 }
0cba1b76
MK		 5788 if (nouveau_force_post)
5789 bios->execute = true;
6ee73861 5790
6ee73861 5791 ret = nouveau_run_vbios_init(dev);
04a39c57 5792 if (ret)
6ee73861 5793 return ret;
6ee73861
BS		 5794
5795 /* feature_byte on BMP is poor, but init always sets CR4B */
6ee73861
BS		 5796 if (bios->major_version < 5)
5797 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
5798
5799 /* all BIT systems need p_f_m_t for digital_min_front_porch */
5800 if (bios->is_mobile || bios->major_version >= 5)
5801 ret = parse_fp_mode_table(dev, bios);
6ee73861
BS		 5802
5803 /* allow subsequent scripts to execute */
5804 bios->execute = true;
5805
5806 return 0;
5807}
5808
5809void
5810nouveau_bios_takedown(struct drm_device *dev)
5811{
b4c26818 5812 nouveau_mxm_fini(dev);
6ee73861 5813}
Linux kernel - Deliverables
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