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drm/nouveau/i2c: handle bit-banging ourselves
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861 30
67eda20e
FJ		 31#include <linux/io-mapping.h>
32
6ee73861
BS		 33/* these defines are made up */
34#define NV_CIO_CRE_44_HEADA 0x0
35#define NV_CIO_CRE_44_HEADB 0x3
36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
6ee73861
BS		 37
38#define EDID1_LEN 128
39
40#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
41#define LOG_OLD_VALUE(x)
42
6ee73861
BS		 43struct init_exec {
44 bool execute;
45 bool repeat;
46};
47
48static bool nv_cksum(const uint8_t *data, unsigned int length)
49{
50 /*
51 * There's a few checksums in the BIOS, so here's a generic checking
52 * function.
53 */
54 int i;
55 uint8_t sum = 0;
56
57 for (i = 0; i < length; i++)
58 sum += data[i];
59
60 if (sum)
61 return true;
62
63 return false;
64}
65
66static int
67score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
68{
69 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
70 NV_TRACEWARN(dev, "... BIOS signature not found\n");
71 return 0;
72 }
73
74 if (nv_cksum(data, data[2] * 512)) {
75 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
76 /* if a ro image is somewhat bad, it's probably all rubbish */
77 return writeable ? 2 : 1;
78 } else
79 NV_TRACE(dev, "... appears to be valid\n");
80
81 return 3;
82}
83
84static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
85{
86 struct drm_nouveau_private *dev_priv = dev->dev_private;
87 uint32_t pci_nv_20, save_pci_nv_20;
88 int pcir_ptr;
89 int i;
90
91 if (dev_priv->card_type >= NV_50)
92 pci_nv_20 = 0x88050;
93 else
94 pci_nv_20 = NV_PBUS_PCI_NV_20;
95
96 /* enable ROM access */
97 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
98 nvWriteMC(dev, pci_nv_20,
99 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
100
101 /* bail if no rom signature */
102 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
103 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
104 goto out;
105
106 /* additional check (see note below) - read PCI record header */
107 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
108 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
109 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
110 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
111 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
112 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
113 goto out;
114
115 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
116 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
117 * each byte. we'll hope pramin has something usable instead
118 */
119 for (i = 0; i < NV_PROM_SIZE; i++)
120 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
121
122out:
123 /* disable ROM access */
124 nvWriteMC(dev, pci_nv_20,
125 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
126}
127
128static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
129{
130 struct drm_nouveau_private *dev_priv = dev->dev_private;
131 uint32_t old_bar0_pramin = 0;
132 int i;
133
134 if (dev_priv->card_type >= NV_50) {
9617757f
BS		 135 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
136 if (!addr) {
137 addr = (u64)nv_rd32(dev, 0x1700) << 16;
138 addr += 0xf0000;
139 }
6ee73861
BS		 140
141 old_bar0_pramin = nv_rd32(dev, 0x1700);
9617757f 142 nv_wr32(dev, 0x1700, addr >> 16);
6ee73861
BS		 143 }
144
145 /* bail if no rom signature */
146 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
147 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
148 goto out;
149
150 for (i = 0; i < NV_PROM_SIZE; i++)
151 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
152
153out:
154 if (dev_priv->card_type >= NV_50)
155 nv_wr32(dev, 0x1700, old_bar0_pramin);
156}
157
158static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
159{
160 void __iomem *rom = NULL;
161 size_t rom_len;
162 int ret;
163
164 ret = pci_enable_rom(dev->pdev);
165 if (ret)
166 return;
167
168 rom = pci_map_rom(dev->pdev, &rom_len);
169 if (!rom)
170 goto out;
171 memcpy_fromio(data, rom, rom_len);
172 pci_unmap_rom(dev->pdev, rom);
173
174out:
175 pci_disable_rom(dev->pdev);
176}
177
afeb3e11
DA		 178static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
179{
180 int i;
181 int ret;
182 int size = 64 * 1024;
183
184 if (!nouveau_acpi_rom_supported(dev->pdev))
185 return;
186
187 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
188 ret = nouveau_acpi_get_bios_chunk(data,
189 (i * ROM_BIOS_PAGE),
190 ROM_BIOS_PAGE);
191 if (ret <= 0)
192 break;
193 }
194 return;
195}
196
6ee73861
BS		 197struct methods {
198 const char desc[8];
199 void (*loadbios)(struct drm_device *, uint8_t *);
200 const bool rw;
6ee73861
BS		 201};
202
41090eb4 203static struct methods shadow_methods[] = {
6ee73861
BS		 204 { "PRAMIN", load_vbios_pramin, true },
205 { "PROM", load_vbios_prom, false },
206 { "PCIROM", load_vbios_pci, true },
41090eb4 207 { "ACPI", load_vbios_acpi, true },
6ee73861 208};
eae6192a 209#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
6ee73861
BS		 210
211static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
212{
41090eb4 213 struct methods *methods = shadow_methods;
6ee73861 214 int testscore = 3;
eae6192a 215 int scores[NUM_SHADOW_METHODS], i;
6ee73861
BS		 216
217 if (nouveau_vbios) {
eae6192a 218 for (i = 0; i < NUM_SHADOW_METHODS; i++)
657b6245 219 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 220 break;
6ee73861 221
eae6192a 222 if (i < NUM_SHADOW_METHODS) {
6ee73861 223 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 224 methods[i].desc);
6ee73861 225
657b6245
MK		 226 methods[i].loadbios(dev, data);
227 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 228 return true;
229 }
230
231 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
232 }
233
eae6192a 234 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
6ee73861 235 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 236 methods[i].desc);
6ee73861 237 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 238 methods[i].loadbios(dev, data);
239 scores[i] = score_vbios(dev, data, methods[i].rw);
240 if (scores[i] == testscore)
6ee73861 241 return true;
6ee73861
BS		 242 }
243
244 while (--testscore > 0) {
eae6192a 245 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
657b6245 246 if (scores[i] == testscore) {
6ee73861 247 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 248 methods[i].desc);
249 methods[i].loadbios(dev, data);
6ee73861
BS		 250 return true;
251 }
6ee73861
BS		 252 }
253 }
254
255 NV_ERROR(dev, "No valid BIOS image found\n");
256 return false;
257}
258
259struct init_tbl_entry {
260 char *name;
261 uint8_t id;
9170a824
BS		 262 /* Return:
263 * > 0: success, length of opcode
264 * 0: success, but abort further parsing of table (INIT_DONE etc)
265 * < 0: failure, table parsing will be aborted
266 */
37383650 267 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 268};
269
ec64a408 270static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 271
272#define MACRO_INDEX_SIZE 2
273#define MACRO_SIZE 8
274#define CONDITION_SIZE 12
275#define IO_FLAG_CONDITION_SIZE 9
276#define IO_CONDITION_SIZE 5
277#define MEM_INIT_SIZE 66
278
279static void still_alive(void)
280{
281#if 0
282 sync();
c7ca4d1b 283 mdelay(2);
6ee73861
BS		 284#endif
285}
286
287static uint32_t
288munge_reg(struct nvbios *bios, uint32_t reg)
289{
290 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
291 struct dcb_entry *dcbent = bios->display.output;
292
293 if (dev_priv->card_type < NV_50)
294 return reg;
295
02e4f587
BS		 296 if (reg & 0x80000000) {
297 BUG_ON(bios->display.crtc < 0);
298 reg += bios->display.crtc * 0x800;
299 }
300
6ee73861
BS		 301 if (reg & 0x40000000) {
302 BUG_ON(!dcbent);
303
304 reg += (ffs(dcbent->or) - 1) * 0x800;
305 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
306 reg += 0x00000080;
307 }
308
02e4f587 309 reg &= ~0xe0000000;
6ee73861
BS		 310 return reg;
311}
312
313static int
314valid_reg(struct nvbios *bios, uint32_t reg)
315{
316 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
317 struct drm_device *dev = bios->dev;
318
319 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 320 if (reg & 0x2 ||
04a39c57 321 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 322 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
323
324 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 325 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 326 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
327 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
328 reg);
329
9855e584
BS		 330 if (reg >= (8*1024*1024)) {
331 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
332 return 0;
6ee73861 333 }
9855e584
BS		 334
335 return 1;
6ee73861
BS		 336}
337
338static bool
339valid_idx_port(struct nvbios *bios, uint16_t port)
340{
341 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
342 struct drm_device *dev = bios->dev;
343
344 /*
345 * If adding more ports here, the read/write functions below will need
346 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
347 * used for the port in question
348 */
349 if (dev_priv->card_type < NV_50) {
350 if (port == NV_CIO_CRX__COLOR)
351 return true;
352 if (port == NV_VIO_SRX)
353 return true;
354 } else {
355 if (port == NV_CIO_CRX__COLOR)
356 return true;
357 }
358
359 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
360 port);
361
362 return false;
363}
364
365static bool
366valid_port(struct nvbios *bios, uint16_t port)
367{
368 struct drm_device *dev = bios->dev;
369
370 /*
371 * If adding more ports here, the read/write functions below will need
372 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
373 * used for the port in question
374 */
375 if (port == NV_VIO_VSE2)
376 return true;
377
378 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
379
380 return false;
381}
382
383static uint32_t
384bios_rd32(struct nvbios *bios, uint32_t reg)
385{
386 uint32_t data;
387
388 reg = munge_reg(bios, reg);
389 if (!valid_reg(bios, reg))
390 return 0;
391
392 /*
393 * C51 sometimes uses regs with bit0 set in the address. For these
394 * cases there should exist a translation in a BIOS table to an IO
395 * port address which the BIOS uses for accessing the reg
396 *
397 * These only seem to appear for the power control regs to a flat panel,
398 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
399 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
400 * suspend-resume mmio trace from a C51 will be required to see if this
401 * is true for the power microcode in 0x14.., or whether the direct IO
402 * port access method is needed
403 */
404 if (reg & 0x1)
405 reg &= ~0x1;
406
407 data = nv_rd32(bios->dev, reg);
408
409 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
410
411 return data;
412}
413
414static void
415bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
416{
417 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
418
419 reg = munge_reg(bios, reg);
420 if (!valid_reg(bios, reg))
421 return;
422
423 /* see note in bios_rd32 */
424 if (reg & 0x1)
425 reg &= 0xfffffffe;
426
427 LOG_OLD_VALUE(bios_rd32(bios, reg));
428 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
429
04a39c57 430 if (dev_priv->vbios.execute) {
6ee73861
BS		 431 still_alive();
432 nv_wr32(bios->dev, reg, data);
433 }
434}
435
436static uint8_t
437bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
438{
439 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
440 struct drm_device *dev = bios->dev;
441 uint8_t data;
442
443 if (!valid_idx_port(bios, port))
444 return 0;
445
446 if (dev_priv->card_type < NV_50) {
447 if (port == NV_VIO_SRX)
448 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
449 else /* assume NV_CIO_CRX__COLOR */
450 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
451 } else {
452 uint32_t data32;
453
454 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
455 data = (data32 >> ((index & 3) << 3)) & 0xff;
456 }
457
458 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
459 "Head: 0x%02X, Data: 0x%02X\n",
460 port, index, bios->state.crtchead, data);
461 return data;
462}
463
464static void
465bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
466{
467 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
468 struct drm_device *dev = bios->dev;
469
470 if (!valid_idx_port(bios, port))
471 return;
472
473 /*
474 * The current head is maintained in the nvbios member state.crtchead.
475 * We trap changes to CR44 and update the head variable and hence the
476 * register set written.
477 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
478 * of the write, and to head1 after the write
479 */
480 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
481 data != NV_CIO_CRE_44_HEADB)
482 bios->state.crtchead = 0;
483
484 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
485 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
486 "Head: 0x%02X, Data: 0x%02X\n",
487 port, index, bios->state.crtchead, data);
488
489 if (bios->execute && dev_priv->card_type < NV_50) {
490 still_alive();
491 if (port == NV_VIO_SRX)
492 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
493 else /* assume NV_CIO_CRX__COLOR */
494 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
495 } else
496 if (bios->execute) {
497 uint32_t data32, shift = (index & 3) << 3;
498
499 still_alive();
500
501 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
502 data32 &= ~(0xff << shift);
503 data32 |= (data << shift);
504 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
505 }
506
507 if (port == NV_CIO_CRX__COLOR &&
508 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
509 bios->state.crtchead = 1;
510}
511
512static uint8_t
513bios_port_rd(struct nvbios *bios, uint16_t port)
514{
515 uint8_t data, head = bios->state.crtchead;
516
517 if (!valid_port(bios, port))
518 return 0;
519
520 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
521
522 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
523 port, head, data);
524
525 return data;
526}
527
528static void
529bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
530{
531 int head = bios->state.crtchead;
532
533 if (!valid_port(bios, port))
534 return;
535
536 LOG_OLD_VALUE(bios_port_rd(bios, port));
537 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
538 port, head, data);
539
540 if (!bios->execute)
541 return;
542
543 still_alive();
544 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
545}
546
547static bool
548io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
549{
550 /*
551 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
552 * for the CRTC index; 1 byte for the mask to apply to the value
553 * retrieved from the CRTC; 1 byte for the shift right to apply to the
554 * masked CRTC value; 2 bytes for the offset to the flag array, to
555 * which the shifted value is added; 1 byte for the mask applied to the
556 * value read from the flag array; and 1 byte for the value to compare
557 * against the masked byte from the flag table.
558 */
559
560 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
561 uint16_t crtcport = ROM16(bios->data[condptr]);
562 uint8_t crtcindex = bios->data[condptr + 2];
563 uint8_t mask = bios->data[condptr + 3];
564 uint8_t shift = bios->data[condptr + 4];
565 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
566 uint8_t flagarraymask = bios->data[condptr + 7];
567 uint8_t cmpval = bios->data[condptr + 8];
568 uint8_t data;
569
570 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
571 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
572 "Cmpval: 0x%02X\n",
573 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
574
575 data = bios_idxprt_rd(bios, crtcport, crtcindex);
576
577 data = bios->data[flagarray + ((data & mask) >> shift)];
578 data &= flagarraymask;
579
580 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
581 offset, data, cmpval);
582
583 return (data == cmpval);
584}
585
586static bool
587bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
588{
589 /*
590 * The condition table entry has 4 bytes for the address of the
591 * register to check, 4 bytes for a mask to apply to the register and
592 * 4 for a test comparison value
593 */
594
595 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
596 uint32_t reg = ROM32(bios->data[condptr]);
597 uint32_t mask = ROM32(bios->data[condptr + 4]);
598 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
599 uint32_t data;
600
601 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
602 offset, cond, reg, mask);
603
604 data = bios_rd32(bios, reg) & mask;
605
606 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
607 offset, data, cmpval);
608
609 return (data == cmpval);
610}
611
612static bool
613io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
614{
615 /*
616 * The IO condition entry has 2 bytes for the IO port address; 1 byte
617 * for the index to write to io_port; 1 byte for the mask to apply to
618 * the byte read from io_port+1; and 1 byte for the value to compare
619 * against the masked byte.
620 */
621
622 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
623 uint16_t io_port = ROM16(bios->data[condptr]);
624 uint8_t port_index = bios->data[condptr + 2];
625 uint8_t mask = bios->data[condptr + 3];
626 uint8_t cmpval = bios->data[condptr + 4];
627
628 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
629
630 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
631 offset, data, cmpval);
632
633 return (data == cmpval);
634}
635
636static int
637nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
638{
639 struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861
BS		 640 struct nouveau_pll_vals pll;
641 struct pll_lims pll_limits;
ee9f7ef9 642 u32 ctrl, mask, coef;
6ee73861
BS		 643 int ret;
644
645 ret = get_pll_limits(dev, reg, &pll_limits);
646 if (ret)
647 return ret;
648
649 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
650 if (!clk)
651 return -ERANGE;
652
ee9f7ef9
BS		 653 coef = pll.N1 << 8 | pll.M1;
654 ctrl = pll.log2P << 16;
655 mask = 0x00070000;
656 if (reg == 0x004008) {
657 mask |= 0x01f80000;
658 ctrl |= (pll_limits.log2p_bias << 19);
659 ctrl |= (pll.log2P << 22);
6ee73861
BS		 660 }
661
ee9f7ef9
BS		 662 if (!dev_priv->vbios.execute)
663 return 0;
664
665 nv_mask(dev, reg + 0, mask, ctrl);
666 nv_wr32(dev, reg + 4, coef);
6ee73861
BS		 667 return 0;
668}
669
670static int
671setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
672{
673 struct drm_device *dev = bios->dev;
674 struct drm_nouveau_private *dev_priv = dev->dev_private;
675 /* clk in kHz */
676 struct pll_lims pll_lim;
677 struct nouveau_pll_vals pllvals;
678 int ret;
679
680 if (dev_priv->card_type >= NV_50)
681 return nv50_pll_set(dev, reg, clk);
682
683 /* high regs (such as in the mac g5 table) are not -= 4 */
684 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
685 if (ret)
686 return ret;
687
688 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
689 if (!clk)
690 return -ERANGE;
691
692 if (bios->execute) {
693 still_alive();
694 nouveau_hw_setpll(dev, reg, &pllvals);
695 }
696
697 return 0;
698}
699
700static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
701{
702 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 703 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 704
705 /*
706 * For the results of this function to be correct, CR44 must have been
707 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
708 * and the DCB table parsed, before the script calling the function is
709 * run. run_digital_op_script is example of how to do such setup
710 */
711
712 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
713
7f245b20 714 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 715 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
716 "(%02X)\n", dcb_entry);
717 dcb_entry = 0x7f; /* unused / invalid marker */
718 }
719
720 return dcb_entry;
721}
722
723static struct nouveau_i2c_chan *
724init_i2c_device_find(struct drm_device *dev, int i2c_index)
725{
6ee73861 726 if (i2c_index == 0xff) {
486a45c2
BS		 727 struct drm_nouveau_private *dev_priv = dev->dev_private;
728 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861 729 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
486a45c2 730 int idx = dcb_entry_idx_from_crtchead(dev);
6ee73861 731
486a45c2 732 i2c_index = NV_I2C_DEFAULT(0);
7f245b20 733 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
486a45c2 734 i2c_index = NV_I2C_DEFAULT(1);
f8b0be1a
BS		 735 }
736
6ee73861
BS		 737 return nouveau_i2c_find(dev, i2c_index);
738}
739
7f245b20
BS		 740static uint32_t
741get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 742{
743 /*
744 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
745 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
746 * CR58 for CR57 = 0 to index a table of offsets to the basic
747 * 0x6808b0 address.
748 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
749 * CR58 for CR57 = 0 to index a table of offsets to the basic
750 * 0x6808b0 address, and then flip the offset by 8.
751 */
752
753 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 754 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 755 const int pramdac_offset[13] = {
756 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
757 const uint32_t pramdac_table[4] = {
758 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
759
760 if (mlv >= 0x80) {
761 int dcb_entry, dacoffset;
762
763 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
764 dcb_entry = dcb_entry_idx_from_crtchead(dev);
765 if (dcb_entry == 0x7f)
766 return 0;
7f245b20 767 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 768 if (mlv == 0x81)
769 dacoffset ^= 8;
770 return 0x6808b0 + dacoffset;
771 } else {
df31ef4d 772 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 773 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
774 mlv);
775 return 0;
776 }
777 return pramdac_table[mlv];
778 }
779}
780
37383650 781static int
6ee73861
BS		 782init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
783 struct init_exec *iexec)
784{
785 /*
786 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
787 *
788 * offset (8 bit): opcode
789 * offset + 1 (16 bit): CRTC port
790 * offset + 3 (8 bit): CRTC index
791 * offset + 4 (8 bit): mask
792 * offset + 5 (8 bit): shift
793 * offset + 6 (8 bit): count
794 * offset + 7 (32 bit): register
795 * offset + 11 (32 bit): configuration 1
796 * ...
797 *
798 * Starting at offset + 11 there are "count" 32 bit values.
799 * To find out which value to use read index "CRTC index" on "CRTC
800 * port", AND this value with "mask" and then bit shift right "shift"
801 * bits. Read the appropriate value using this index and write to
802 * "register"
803 */
804
805 uint16_t crtcport = ROM16(bios->data[offset + 1]);
806 uint8_t crtcindex = bios->data[offset + 3];
807 uint8_t mask = bios->data[offset + 4];
808 uint8_t shift = bios->data[offset + 5];
809 uint8_t count = bios->data[offset + 6];
810 uint32_t reg = ROM32(bios->data[offset + 7]);
811 uint8_t config;
812 uint32_t configval;
37383650 813 int len = 11 + count * 4;
6ee73861
BS		 814
815 if (!iexec->execute)
37383650 816 return len;
6ee73861
BS		 817
818 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
819 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
820 offset, crtcport, crtcindex, mask, shift, count, reg);
821
822 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
823 if (config > count) {
824 NV_ERROR(bios->dev,
825 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
826 offset, config, count);
309b8c89 827 return len;
6ee73861
BS		 828 }
829
830 configval = ROM32(bios->data[offset + 11 + config * 4]);
831
832 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
833
834 bios_wr32(bios, reg, configval);
835
37383650 836 return len;
6ee73861
BS		 837}
838
37383650 839static int
6ee73861
BS		 840init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
841{
842 /*
843 * INIT_REPEAT opcode: 0x33 ('3')
844 *
845 * offset (8 bit): opcode
846 * offset + 1 (8 bit): count
847 *
848 * Execute script following this opcode up to INIT_REPEAT_END
849 * "count" times
850 */
851
852 uint8_t count = bios->data[offset + 1];
853 uint8_t i;
854
855 /* no iexec->execute check by design */
856
857 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
858 offset, count);
859
860 iexec->repeat = true;
861
862 /*
863 * count - 1, as the script block will execute once when we leave this
864 * opcode -- this is compatible with bios behaviour as:
865 * a) the block is always executed at least once, even if count == 0
866 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
867 * while we don't
868 */
869 for (i = 0; i < count - 1; i++)
870 parse_init_table(bios, offset + 2, iexec);
871
872 iexec->repeat = false;
873
37383650 874 return 2;
6ee73861
BS		 875}
876
37383650 877static int
6ee73861
BS		 878init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
879 struct init_exec *iexec)
880{
881 /*
882 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
883 *
884 * offset (8 bit): opcode
885 * offset + 1 (16 bit): CRTC port
886 * offset + 3 (8 bit): CRTC index
887 * offset + 4 (8 bit): mask
888 * offset + 5 (8 bit): shift
889 * offset + 6 (8 bit): IO flag condition index
890 * offset + 7 (8 bit): count
891 * offset + 8 (32 bit): register
892 * offset + 12 (16 bit): frequency 1
893 * ...
894 *
895 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
896 * Set PLL register "register" to coefficients for frequency n,
897 * selected by reading index "CRTC index" of "CRTC port" ANDed with
898 * "mask" and shifted right by "shift".
899 *
900 * If "IO flag condition index" > 0, and condition met, double
901 * frequency before setting it.
902 */
903
904 uint16_t crtcport = ROM16(bios->data[offset + 1]);
905 uint8_t crtcindex = bios->data[offset + 3];
906 uint8_t mask = bios->data[offset + 4];
907 uint8_t shift = bios->data[offset + 5];
908 int8_t io_flag_condition_idx = bios->data[offset + 6];
909 uint8_t count = bios->data[offset + 7];
910 uint32_t reg = ROM32(bios->data[offset + 8]);
911 uint8_t config;
912 uint16_t freq;
37383650 913 int len = 12 + count * 2;
6ee73861
BS		 914
915 if (!iexec->execute)
37383650 916 return len;
6ee73861
BS		 917
918 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
919 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
920 "Count: 0x%02X, Reg: 0x%08X\n",
921 offset, crtcport, crtcindex, mask, shift,
922 io_flag_condition_idx, count, reg);
923
924 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
925 if (config > count) {
926 NV_ERROR(bios->dev,
927 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
928 offset, config, count);
309b8c89 929 return len;
6ee73861
BS		 930 }
931
932 freq = ROM16(bios->data[offset + 12 + config * 2]);
933
934 if (io_flag_condition_idx > 0) {
935 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
936 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
937 "frequency doubled\n", offset);
938 freq *= 2;
939 } else
940 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
941 "frequency unchanged\n", offset);
942 }
943
944 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
945 offset, reg, config, freq);
946
947 setPLL(bios, reg, freq * 10);
948
37383650 949 return len;
6ee73861
BS		 950}
951
37383650 952static int
6ee73861
BS		 953init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
954{
955 /*
956 * INIT_END_REPEAT opcode: 0x36 ('6')
957 *
958 * offset (8 bit): opcode
959 *
960 * Marks the end of the block for INIT_REPEAT to repeat
961 */
962
963 /* no iexec->execute check by design */
964
965 /*
966 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
967 * we're not in repeat mode
968 */
969 if (iexec->repeat)
37383650 970 return 0;
6ee73861 971
37383650 972 return 1;
6ee73861
BS		 973}
974
37383650 975static int
6ee73861
BS		 976init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
977{
978 /*
979 * INIT_COPY opcode: 0x37 ('7')
980 *
981 * offset (8 bit): opcode
982 * offset + 1 (32 bit): register
983 * offset + 5 (8 bit): shift
984 * offset + 6 (8 bit): srcmask
985 * offset + 7 (16 bit): CRTC port
986 * offset + 9 (8 bit): CRTC index
987 * offset + 10 (8 bit): mask
988 *
989 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
990 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
991 * port
992 */
993
994 uint32_t reg = ROM32(bios->data[offset + 1]);
995 uint8_t shift = bios->data[offset + 5];
996 uint8_t srcmask = bios->data[offset + 6];
997 uint16_t crtcport = ROM16(bios->data[offset + 7]);
998 uint8_t crtcindex = bios->data[offset + 9];
999 uint8_t mask = bios->data[offset + 10];
1000 uint32_t data;
1001 uint8_t crtcdata;
1002
1003 if (!iexec->execute)
37383650 1004 return 11;
6ee73861
BS		 1005
1006 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1007 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1008 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1009
1010 data = bios_rd32(bios, reg);
1011
1012 if (shift < 0x80)
1013 data >>= shift;
1014 else
1015 data <<= (0x100 - shift);
1016
1017 data &= srcmask;
1018
1019 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1020 crtcdata |= (uint8_t)data;
1021 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1022
37383650 1023 return 11;
6ee73861
BS		 1024}
1025
37383650 1026static int
6ee73861
BS		 1027init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1028{
1029 /*
1030 * INIT_NOT opcode: 0x38 ('8')
1031 *
1032 * offset (8 bit): opcode
1033 *
1034 * Invert the current execute / no-execute condition (i.e. "else")
1035 */
1036 if (iexec->execute)
1037 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1038 else
1039 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1040
1041 iexec->execute = !iexec->execute;
37383650 1042 return 1;
6ee73861
BS		 1043}
1044
37383650 1045static int
6ee73861
BS		 1046init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1047 struct init_exec *iexec)
1048{
1049 /*
1050 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1051 *
1052 * offset (8 bit): opcode
1053 * offset + 1 (8 bit): condition number
1054 *
1055 * Check condition "condition number" in the IO flag condition table.
1056 * If condition not met skip subsequent opcodes until condition is
1057 * inverted (INIT_NOT), or we hit INIT_RESUME
1058 */
1059
1060 uint8_t cond = bios->data[offset + 1];
1061
1062 if (!iexec->execute)
37383650 1063 return 2;
6ee73861
BS		 1064
1065 if (io_flag_condition_met(bios, offset, cond))
1066 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1067 else {
1068 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1069 iexec->execute = false;
1070 }
1071
37383650 1072 return 2;
6ee73861
BS		 1073}
1074
25908b77
BS		 1075static int
1076init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1077{
1078 /*
1079 * INIT_DP_CONDITION opcode: 0x3A ('')
1080 *
1081 * offset (8 bit): opcode
1082 * offset + 1 (8 bit): "sub" opcode
1083 * offset + 2 (8 bit): unknown
1084 *
1085 */
1086
25908b77
BS		 1087 struct dcb_entry *dcb = bios->display.output;
1088 struct drm_device *dev = bios->dev;
1089 uint8_t cond = bios->data[offset + 1];
5f1800bd 1090 uint8_t *table, *entry;
25908b77
BS		 1091
1092 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1093
1094 if (!iexec->execute)
1095 return 3;
1096
5f1800bd
BS		 1097 table = nouveau_dp_bios_data(dev, dcb, &entry);
1098 if (!table)
309b8c89 1099 return 3;
25908b77
BS		 1100
1101 switch (cond) {
1102 case 0:
1103 {
1104 struct dcb_connector_table_entry *ent =
1105 &bios->dcb.connector.entry[dcb->connector];
1106
1107 if (ent->type != DCB_CONNECTOR_eDP)
1108 iexec->execute = false;
1109 }
1110 break;
1111 case 1:
1112 case 2:
5f1800bd 1113 if (!(entry[5] & cond))
25908b77
BS		 1114 iexec->execute = false;
1115 break;
1116 case 5:
1117 {
1118 struct nouveau_i2c_chan *auxch;
1119 int ret;
1120
1121 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
309b8c89
BS		 1122 if (!auxch) {
1123 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1124 return 3;
1125 }
25908b77
BS		 1126
1127 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
309b8c89
BS		 1128 if (ret) {
1129 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1130 return 3;
1131 }
25908b77 1132
64d202b4 1133 if (!(cond & 1))
25908b77
BS		 1134 iexec->execute = false;
1135 }
1136 break;
1137 default:
1138 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1139 break;
1140 }
1141
1142 if (iexec->execute)
1143 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1144 else
1145 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1146
1147 return 3;
1148}
1149
1150static int
1151init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1152{
1153 /*
1154 * INIT_3B opcode: 0x3B ('')
1155 *
1156 * offset (8 bit): opcode
1157 * offset + 1 (8 bit): crtc index
1158 *
1159 */
1160
1161 uint8_t or = ffs(bios->display.output->or) - 1;
1162 uint8_t index = bios->data[offset + 1];
1163 uint8_t data;
1164
1165 if (!iexec->execute)
1166 return 2;
1167
1168 data = bios_idxprt_rd(bios, 0x3d4, index);
1169 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1170 return 2;
1171}
1172
1173static int
1174init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1175{
1176 /*
1177 * INIT_3C opcode: 0x3C ('')
1178 *
1179 * offset (8 bit): opcode
1180 * offset + 1 (8 bit): crtc index
1181 *
1182 */
1183
1184 uint8_t or = ffs(bios->display.output->or) - 1;
1185 uint8_t index = bios->data[offset + 1];
1186 uint8_t data;
1187
1188 if (!iexec->execute)
1189 return 2;
1190
1191 data = bios_idxprt_rd(bios, 0x3d4, index);
1192 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1193 return 2;
1194}
1195
37383650 1196static int
6ee73861
BS		 1197init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1198 struct init_exec *iexec)
1199{
1200 /*
1201 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1202 *
1203 * offset (8 bit): opcode
1204 * offset + 1 (32 bit): control register
1205 * offset + 5 (32 bit): data register
1206 * offset + 9 (32 bit): mask
1207 * offset + 13 (32 bit): data
1208 * offset + 17 (8 bit): count
1209 * offset + 18 (8 bit): address 1
1210 * offset + 19 (8 bit): data 1
1211 * ...
1212 *
1213 * For each of "count" address and data pairs, write "data n" to
1214 * "data register", read the current value of "control register",
1215 * and write it back once ANDed with "mask", ORed with "data",
1216 * and ORed with "address n"
1217 */
1218
1219 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1220 uint32_t datareg = ROM32(bios->data[offset + 5]);
1221 uint32_t mask = ROM32(bios->data[offset + 9]);
1222 uint32_t data = ROM32(bios->data[offset + 13]);
1223 uint8_t count = bios->data[offset + 17];
37383650 1224 int len = 18 + count * 2;
6ee73861
BS		 1225 uint32_t value;
1226 int i;
1227
1228 if (!iexec->execute)
37383650 1229 return len;
6ee73861
BS		 1230
1231 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1232 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1233 offset, controlreg, datareg, mask, data, count);
1234
1235 for (i = 0; i < count; i++) {
1236 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1237 uint8_t instdata = bios->data[offset + 19 + i * 2];
1238
1239 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1240 offset, instaddress, instdata);
1241
1242 bios_wr32(bios, datareg, instdata);
1243 value = bios_rd32(bios, controlreg) & mask;
1244 value |= data;
1245 value |= instaddress;
1246 bios_wr32(bios, controlreg, value);
1247 }
1248
37383650 1249 return len;
6ee73861
BS		 1250}
1251
37383650 1252static int
6ee73861
BS		 1253init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1254 struct init_exec *iexec)
1255{
1256 /*
1257 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1258 *
1259 * offset (8 bit): opcode
1260 * offset + 1 (16 bit): CRTC port
1261 * offset + 3 (8 bit): CRTC index
1262 * offset + 4 (8 bit): mask
1263 * offset + 5 (8 bit): shift
1264 * offset + 6 (8 bit): count
1265 * offset + 7 (32 bit): register
1266 * offset + 11 (32 bit): frequency 1
1267 * ...
1268 *
1269 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1270 * Set PLL register "register" to coefficients for frequency n,
1271 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1272 * "mask" and shifted right by "shift".
1273 */
1274
1275 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1276 uint8_t crtcindex = bios->data[offset + 3];
1277 uint8_t mask = bios->data[offset + 4];
1278 uint8_t shift = bios->data[offset + 5];
1279 uint8_t count = bios->data[offset + 6];
1280 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1281 int len = 11 + count * 4;
6ee73861
BS		 1282 uint8_t config;
1283 uint32_t freq;
1284
1285 if (!iexec->execute)
37383650 1286 return len;
6ee73861
BS		 1287
1288 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1289 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1290 offset, crtcport, crtcindex, mask, shift, count, reg);
1291
1292 if (!reg)
37383650 1293 return len;
6ee73861
BS		 1294
1295 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1296 if (config > count) {
1297 NV_ERROR(bios->dev,
1298 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1299 offset, config, count);
309b8c89 1300 return len;
6ee73861
BS		 1301 }
1302
1303 freq = ROM32(bios->data[offset + 11 + config * 4]);
1304
1305 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1306 offset, reg, config, freq);
1307
1308 setPLL(bios, reg, freq);
1309
37383650 1310 return len;
6ee73861
BS		 1311}
1312
37383650 1313static int
6ee73861
BS		 1314init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1315{
1316 /*
1317 * INIT_PLL2 opcode: 0x4B ('K')
1318 *
1319 * offset (8 bit): opcode
1320 * offset + 1 (32 bit): register
1321 * offset + 5 (32 bit): freq
1322 *
1323 * Set PLL register "register" to coefficients for frequency "freq"
1324 */
1325
1326 uint32_t reg = ROM32(bios->data[offset + 1]);
1327 uint32_t freq = ROM32(bios->data[offset + 5]);
1328
1329 if (!iexec->execute)
37383650 1330 return 9;
6ee73861
BS		 1331
1332 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1333 offset, reg, freq);
1334
1335 setPLL(bios, reg, freq);
37383650 1336 return 9;
6ee73861
BS		 1337}
1338
37383650 1339static int
6ee73861
BS		 1340init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1341{
1342 /*
1343 * INIT_I2C_BYTE opcode: 0x4C ('L')
1344 *
1345 * offset (8 bit): opcode
1346 * offset + 1 (8 bit): DCB I2C table entry index
1347 * offset + 2 (8 bit): I2C slave address
1348 * offset + 3 (8 bit): count
1349 * offset + 4 (8 bit): I2C register 1
1350 * offset + 5 (8 bit): mask 1
1351 * offset + 6 (8 bit): data 1
1352 * ...
1353 *
1354 * For each of "count" registers given by "I2C register n" on the device
1355 * addressed by "I2C slave address" on the I2C bus given by
1356 * "DCB I2C table entry index", read the register, AND the result with
1357 * "mask n" and OR it with "data n" before writing it back to the device
1358 */
1359
309b8c89 1360 struct drm_device *dev = bios->dev;
6ee73861 1361 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1362 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1363 uint8_t count = bios->data[offset + 3];
1364 struct nouveau_i2c_chan *chan;
893887ed
BS		 1365 int len = 4 + count * 3;
1366 int ret, i;
6ee73861
BS		 1367
1368 if (!iexec->execute)
37383650 1369 return len;
6ee73861
BS		 1370
1371 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1372 "Count: 0x%02X\n",
1373 offset, i2c_index, i2c_address, count);
1374
309b8c89
BS		 1375 chan = init_i2c_device_find(dev, i2c_index);
1376 if (!chan) {
1377 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1378 return len;
1379 }
6ee73861
BS		 1380
1381 for (i = 0; i < count; i++) {
893887ed 1382 uint8_t reg = bios->data[offset + 4 + i * 3];
6ee73861
BS		 1383 uint8_t mask = bios->data[offset + 5 + i * 3];
1384 uint8_t data = bios->data[offset + 6 + i * 3];
893887ed 1385 union i2c_smbus_data val;
6ee73861 1386
893887ed
BS		 1387 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1388 I2C_SMBUS_READ, reg,
1389 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1390 if (ret < 0) {
1391 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1392 return len;
1393 }
6ee73861
BS		 1394
1395 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1396 "Mask: 0x%02X, Data: 0x%02X\n",
893887ed 1397 offset, reg, val.byte, mask, data);
6ee73861 1398
893887ed
BS		 1399 if (!bios->execute)
1400 continue;
6ee73861 1401
893887ed
BS		 1402 val.byte &= mask;
1403 val.byte |= data;
1404 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1405 I2C_SMBUS_WRITE, reg,
1406 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1407 if (ret < 0) {
1408 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1409 return len;
1410 }
6ee73861
BS		 1411 }
1412
37383650 1413 return len;
6ee73861
BS		 1414}
1415
37383650 1416static int
6ee73861
BS		 1417init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1418{
1419 /*
1420 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1421 *
1422 * offset (8 bit): opcode
1423 * offset + 1 (8 bit): DCB I2C table entry index
1424 * offset + 2 (8 bit): I2C slave address
1425 * offset + 3 (8 bit): count
1426 * offset + 4 (8 bit): I2C register 1
1427 * offset + 5 (8 bit): data 1
1428 * ...
1429 *
1430 * For each of "count" registers given by "I2C register n" on the device
1431 * addressed by "I2C slave address" on the I2C bus given by
1432 * "DCB I2C table entry index", set the register to "data n"
1433 */
1434
309b8c89 1435 struct drm_device *dev = bios->dev;
6ee73861 1436 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1437 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1438 uint8_t count = bios->data[offset + 3];
1439 struct nouveau_i2c_chan *chan;
893887ed
BS		 1440 int len = 4 + count * 2;
1441 int ret, i;
6ee73861
BS		 1442
1443 if (!iexec->execute)
37383650 1444 return len;
6ee73861
BS		 1445
1446 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1447 "Count: 0x%02X\n",
1448 offset, i2c_index, i2c_address, count);
1449
309b8c89
BS		 1450 chan = init_i2c_device_find(dev, i2c_index);
1451 if (!chan) {
1452 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1453 return len;
1454 }
6ee73861
BS		 1455
1456 for (i = 0; i < count; i++) {
893887ed
BS		 1457 uint8_t reg = bios->data[offset + 4 + i * 2];
1458 union i2c_smbus_data val;
1459
1460 val.byte = bios->data[offset + 5 + i * 2];
6ee73861
BS		 1461
1462 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
893887ed
BS		 1463 offset, reg, val.byte);
1464
1465 if (!bios->execute)
1466 continue;
1467
1468 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1469 I2C_SMBUS_WRITE, reg,
1470 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1471 if (ret < 0) {
1472 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1473 return len;
1474 }
6ee73861
BS		 1475 }
1476
37383650 1477 return len;
6ee73861
BS		 1478}
1479
37383650 1480static int
6ee73861
BS		 1481init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1482{
1483 /*
1484 * INIT_ZM_I2C opcode: 0x4E ('N')
1485 *
1486 * offset (8 bit): opcode
1487 * offset + 1 (8 bit): DCB I2C table entry index
1488 * offset + 2 (8 bit): I2C slave address
1489 * offset + 3 (8 bit): count
1490 * offset + 4 (8 bit): data 1
1491 * ...
1492 *
1493 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1494 * address" on the I2C bus given by "DCB I2C table entry index"
1495 */
1496
309b8c89 1497 struct drm_device *dev = bios->dev;
6ee73861 1498 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1499 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1500 uint8_t count = bios->data[offset + 3];
37383650 1501 int len = 4 + count;
6ee73861
BS		 1502 struct nouveau_i2c_chan *chan;
1503 struct i2c_msg msg;
1504 uint8_t data[256];
309b8c89 1505 int ret, i;
6ee73861
BS		 1506
1507 if (!iexec->execute)
37383650 1508 return len;
6ee73861
BS		 1509
1510 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1511 "Count: 0x%02X\n",
1512 offset, i2c_index, i2c_address, count);
1513
309b8c89
BS		 1514 chan = init_i2c_device_find(dev, i2c_index);
1515 if (!chan) {
1516 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1517 return len;
1518 }
6ee73861
BS		 1519
1520 for (i = 0; i < count; i++) {
1521 data[i] = bios->data[offset + 4 + i];
1522
1523 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1524 }
1525
1526 if (bios->execute) {
1527 msg.addr = i2c_address;
1528 msg.flags = 0;
1529 msg.len = count;
1530 msg.buf = data;
309b8c89
BS		 1531 ret = i2c_transfer(&chan->adapter, &msg, 1);
1532 if (ret != 1) {
1533 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1534 return len;
1535 }
6ee73861
BS		 1536 }
1537
37383650 1538 return len;
6ee73861
BS		 1539}
1540
37383650 1541static int
6ee73861
BS		 1542init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1543{
1544 /*
1545 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1546 *
1547 * offset (8 bit): opcode
1548 * offset + 1 (8 bit): magic lookup value
1549 * offset + 2 (8 bit): TMDS address
1550 * offset + 3 (8 bit): mask
1551 * offset + 4 (8 bit): data
1552 *
1553 * Read the data reg for TMDS address "TMDS address", AND it with mask
1554 * and OR it with data, then write it back
1555 * "magic lookup value" determines which TMDS base address register is
1556 * used -- see get_tmds_index_reg()
1557 */
1558
309b8c89 1559 struct drm_device *dev = bios->dev;
6ee73861
BS		 1560 uint8_t mlv = bios->data[offset + 1];
1561 uint32_t tmdsaddr = bios->data[offset + 2];
1562 uint8_t mask = bios->data[offset + 3];
1563 uint8_t data = bios->data[offset + 4];
1564 uint32_t reg, value;
1565
1566 if (!iexec->execute)
37383650 1567 return 5;
6ee73861
BS		 1568
1569 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1570 "Mask: 0x%02X, Data: 0x%02X\n",
1571 offset, mlv, tmdsaddr, mask, data);
1572
1573 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1574 if (!reg) {
1575 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1576 return 5;
1577 }
6ee73861
BS		 1578
1579 bios_wr32(bios, reg,
1580 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1581 value = (bios_rd32(bios, reg + 4) & mask) | data;
1582 bios_wr32(bios, reg + 4, value);
1583 bios_wr32(bios, reg, tmdsaddr);
1584
37383650 1585 return 5;
6ee73861
BS		 1586}
1587
37383650 1588static int
6ee73861
BS		 1589init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1590 struct init_exec *iexec)
1591{
1592 /*
1593 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1594 *
1595 * offset (8 bit): opcode
1596 * offset + 1 (8 bit): magic lookup value
1597 * offset + 2 (8 bit): count
1598 * offset + 3 (8 bit): addr 1
1599 * offset + 4 (8 bit): data 1
1600 * ...
1601 *
1602 * For each of "count" TMDS address and data pairs write "data n" to
1603 * "addr n". "magic lookup value" determines which TMDS base address
1604 * register is used -- see get_tmds_index_reg()
1605 */
1606
309b8c89 1607 struct drm_device *dev = bios->dev;
6ee73861
BS		 1608 uint8_t mlv = bios->data[offset + 1];
1609 uint8_t count = bios->data[offset + 2];
37383650 1610 int len = 3 + count * 2;
6ee73861
BS		 1611 uint32_t reg;
1612 int i;
1613
1614 if (!iexec->execute)
37383650 1615 return len;
6ee73861
BS		 1616
1617 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1618 offset, mlv, count);
1619
1620 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1621 if (!reg) {
1622 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1623 return len;
1624 }
6ee73861
BS		 1625
1626 for (i = 0; i < count; i++) {
1627 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1628 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1629
1630 bios_wr32(bios, reg + 4, tmdsdata);
1631 bios_wr32(bios, reg, tmdsaddr);
1632 }
1633
37383650 1634 return len;
6ee73861
BS		 1635}
1636
37383650 1637static int
6ee73861
BS		 1638init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1639 struct init_exec *iexec)
1640{
1641 /*
1642 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1643 *
1644 * offset (8 bit): opcode
1645 * offset + 1 (8 bit): CRTC index1
1646 * offset + 2 (8 bit): CRTC index2
1647 * offset + 3 (8 bit): baseaddr
1648 * offset + 4 (8 bit): count
1649 * offset + 5 (8 bit): data 1
1650 * ...
1651 *
1652 * For each of "count" address and data pairs, write "baseaddr + n" to
1653 * "CRTC index1" and "data n" to "CRTC index2"
1654 * Once complete, restore initial value read from "CRTC index1"
1655 */
1656 uint8_t crtcindex1 = bios->data[offset + 1];
1657 uint8_t crtcindex2 = bios->data[offset + 2];
1658 uint8_t baseaddr = bios->data[offset + 3];
1659 uint8_t count = bios->data[offset + 4];
37383650 1660 int len = 5 + count;
6ee73861
BS		 1661 uint8_t oldaddr, data;
1662 int i;
1663
1664 if (!iexec->execute)
37383650 1665 return len;
6ee73861
BS		 1666
1667 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1668 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1669 offset, crtcindex1, crtcindex2, baseaddr, count);
1670
1671 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1672
1673 for (i = 0; i < count; i++) {
1674 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1675 baseaddr + i);
1676 data = bios->data[offset + 5 + i];
1677 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1678 }
1679
1680 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1681
37383650 1682 return len;
6ee73861
BS		 1683}
1684
37383650 1685static int
6ee73861
BS		 1686init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1687{
1688 /*
1689 * INIT_CR opcode: 0x52 ('R')
1690 *
1691 * offset (8 bit): opcode
1692 * offset + 1 (8 bit): CRTC index
1693 * offset + 2 (8 bit): mask
1694 * offset + 3 (8 bit): data
1695 *
1696 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1697 * data back to "CRTC index"
1698 */
1699
1700 uint8_t crtcindex = bios->data[offset + 1];
1701 uint8_t mask = bios->data[offset + 2];
1702 uint8_t data = bios->data[offset + 3];
1703 uint8_t value;
1704
1705 if (!iexec->execute)
37383650 1706 return 4;
6ee73861
BS		 1707
1708 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1709 offset, crtcindex, mask, data);
1710
1711 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1712 value |= data;
1713 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1714
37383650 1715 return 4;
6ee73861
BS		 1716}
1717
37383650 1718static int
6ee73861
BS		 1719init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1720{
1721 /*
1722 * INIT_ZM_CR opcode: 0x53 ('S')
1723 *
1724 * offset (8 bit): opcode
1725 * offset + 1 (8 bit): CRTC index
1726 * offset + 2 (8 bit): value
1727 *
1728 * Assign "value" to CRTC register with index "CRTC index".
1729 */
1730
1731 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1732 uint8_t data = bios->data[offset + 2];
1733
1734 if (!iexec->execute)
37383650 1735 return 3;
6ee73861
BS		 1736
1737 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1738
37383650 1739 return 3;
6ee73861
BS		 1740}
1741
37383650 1742static int
6ee73861
BS		 1743init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1744{
1745 /*
1746 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1747 *
1748 * offset (8 bit): opcode
1749 * offset + 1 (8 bit): count
1750 * offset + 2 (8 bit): CRTC index 1
1751 * offset + 3 (8 bit): value 1
1752 * ...
1753 *
1754 * For "count", assign "value n" to CRTC register with index
1755 * "CRTC index n".
1756 */
1757
1758 uint8_t count = bios->data[offset + 1];
37383650 1759 int len = 2 + count * 2;
6ee73861
BS		 1760 int i;
1761
1762 if (!iexec->execute)
37383650 1763 return len;
6ee73861
BS		 1764
1765 for (i = 0; i < count; i++)
1766 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1767
37383650 1768 return len;
6ee73861
BS		 1769}
1770
37383650 1771static int
6ee73861
BS		 1772init_condition_time(struct nvbios *bios, uint16_t offset,
1773 struct init_exec *iexec)
1774{
1775 /*
1776 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1777 *
1778 * offset (8 bit): opcode
1779 * offset + 1 (8 bit): condition number
1780 * offset + 2 (8 bit): retries / 50
1781 *
1782 * Check condition "condition number" in the condition table.
1783 * Bios code then sleeps for 2ms if the condition is not met, and
1784 * repeats up to "retries" times, but on one C51 this has proved
1785 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1786 * this, and bail after "retries" times, or 2s, whichever is less.
1787 * If still not met after retries, clear execution flag for this table.
1788 */
1789
1790 uint8_t cond = bios->data[offset + 1];
1791 uint16_t retries = bios->data[offset + 2] * 50;
1792 unsigned cnt;
1793
1794 if (!iexec->execute)
37383650 1795 return 3;
6ee73861
BS		 1796
1797 if (retries > 100)
1798 retries = 100;
1799
1800 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1801 offset, cond, retries);
1802
1803 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1804 retries = 1;
1805
1806 for (cnt = 0; cnt < retries; cnt++) {
1807 if (bios_condition_met(bios, offset, cond)) {
1808 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1809 offset);
1810 break;
1811 } else {
1812 BIOSLOG(bios, "0x%04X: "
1813 "Condition not met, sleeping for 20ms\n",
1814 offset);
c7ca4d1b 1815 mdelay(20);
6ee73861
BS		 1816 }
1817 }
1818
1819 if (!bios_condition_met(bios, offset, cond)) {
1820 NV_WARN(bios->dev,
1821 "0x%04X: Condition still not met after %dms, "
1822 "skipping following opcodes\n", offset, 20 * retries);
1823 iexec->execute = false;
1824 }
1825
37383650 1826 return 3;
6ee73861
BS		 1827}
1828
e3a1924f
MK		 1829static int
1830init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1831{
1832 /*
1833 * INIT_LTIME opcode: 0x57 ('V')
1834 *
1835 * offset (8 bit): opcode
1836 * offset + 1 (16 bit): time
1837 *
e8a8b252 1838 * Sleep for "time" milliseconds.
e3a1924f
MK		 1839 */
1840
1841 unsigned time = ROM16(bios->data[offset + 1]);
1842
1843 if (!iexec->execute)
1844 return 3;
1845
e8a8b252 1846 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
e3a1924f
MK		 1847 offset, time);
1848
c7ca4d1b 1849 mdelay(time);
e3a1924f
MK		 1850
1851 return 3;
1852}
1853
37383650 1854static int
6ee73861
BS		 1855init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1856 struct init_exec *iexec)
1857{
1858 /*
1859 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1860 *
1861 * offset (8 bit): opcode
1862 * offset + 1 (32 bit): base register
1863 * offset + 5 (8 bit): count
1864 * offset + 6 (32 bit): value 1
1865 * ...
1866 *
1867 * Starting at offset + 6 there are "count" 32 bit values.
1868 * For "count" iterations set "base register" + 4 * current_iteration
1869 * to "value current_iteration"
1870 */
1871
1872 uint32_t basereg = ROM32(bios->data[offset + 1]);
1873 uint32_t count = bios->data[offset + 5];
37383650 1874 int len = 6 + count * 4;
6ee73861
BS		 1875 int i;
1876
1877 if (!iexec->execute)
37383650 1878 return len;
6ee73861
BS		 1879
1880 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1881 offset, basereg, count);
1882
1883 for (i = 0; i < count; i++) {
1884 uint32_t reg = basereg + i * 4;
1885 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1886
1887 bios_wr32(bios, reg, data);
1888 }
1889
37383650 1890 return len;
6ee73861
BS		 1891}
1892
37383650 1893static int
6ee73861
BS		 1894init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1895{
1896 /*
1897 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1898 *
1899 * offset (8 bit): opcode
1900 * offset + 1 (16 bit): subroutine offset (in bios)
1901 *
1902 * Calls a subroutine that will execute commands until INIT_DONE
1903 * is found.
1904 */
1905
1906 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1907
1908 if (!iexec->execute)
37383650 1909 return 3;
6ee73861
BS		 1910
1911 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1912 offset, sub_offset);
1913
1914 parse_init_table(bios, sub_offset, iexec);
1915
1916 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1917
37383650 1918 return 3;
6ee73861
BS		 1919}
1920
ec64a408
BS		 1921static int
1922init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1923{
1924 /*
1925 * INIT_JUMP opcode: 0x5C ('\')
1926 *
1927 * offset (8 bit): opcode
1928 * offset + 1 (16 bit): offset (in bios)
1929 *
1930 * Continue execution of init table from 'offset'
1931 */
1932
1933 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
1934
1935 if (!iexec->execute)
1936 return 3;
1937
1938 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
1939 return jmp_offset - offset;
1940}
1941
b715d640
MK		 1942static int
1943init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1944{
1945 /*
1946 * INIT_I2C_IF opcode: 0x5E ('^')
1947 *
1948 * offset (8 bit): opcode
1949 * offset + 1 (8 bit): DCB I2C table entry index
1950 * offset + 2 (8 bit): I2C slave address
1951 * offset + 3 (8 bit): I2C register
1952 * offset + 4 (8 bit): mask
1953 * offset + 5 (8 bit): data
1954 *
1955 * Read the register given by "I2C register" on the device addressed
1956 * by "I2C slave address" on the I2C bus given by "DCB I2C table
1957 * entry index". Compare the result AND "mask" to "data".
1958 * If they're not equal, skip subsequent opcodes until condition is
1959 * inverted (INIT_NOT), or we hit INIT_RESUME
1960 */
1961
1962 uint8_t i2c_index = bios->data[offset + 1];
1963 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1964 uint8_t reg = bios->data[offset + 3];
1965 uint8_t mask = bios->data[offset + 4];
1966 uint8_t data = bios->data[offset + 5];
1967 struct nouveau_i2c_chan *chan;
1968 union i2c_smbus_data val;
1969 int ret;
1970
1971 /* no execute check by design */
1972
1973 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
1974 offset, i2c_index, i2c_address);
1975
1976 chan = init_i2c_device_find(bios->dev, i2c_index);
1977 if (!chan)
1978 return -ENODEV;
1979
1980 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1981 I2C_SMBUS_READ, reg,
1982 I2C_SMBUS_BYTE_DATA, &val);
1983 if (ret < 0) {
1984 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
1985 "Mask: 0x%02X, Data: 0x%02X\n",
1986 offset, reg, mask, data);
1987 iexec->execute = 0;
1988 return 6;
1989 }
1990
1991 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1992 "Mask: 0x%02X, Data: 0x%02X\n",
1993 offset, reg, val.byte, mask, data);
1994
1995 iexec->execute = ((val.byte & mask) == data);
1996
1997 return 6;
1998}
1999
37383650 2000static int
6ee73861
BS		 2001init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2002{
2003 /*
2004 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2005 *
2006 * offset (8 bit): opcode
2007 * offset + 1 (32 bit): src reg
2008 * offset + 5 (8 bit): shift
2009 * offset + 6 (32 bit): src mask
2010 * offset + 10 (32 bit): xor
2011 * offset + 14 (32 bit): dst reg
2012 * offset + 18 (32 bit): dst mask
2013 *
2014 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2015 * "src mask", then XOR with "xor". Write this OR'd with
2016 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2017 */
2018
2019 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2020 uint8_t shift = bios->data[offset + 5];
2021 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2022 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2023 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2024 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2025 uint32_t srcvalue, dstvalue;
2026
2027 if (!iexec->execute)
37383650 2028 return 22;
6ee73861
BS		 2029
2030 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2031 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2032 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2033
2034 srcvalue = bios_rd32(bios, srcreg);
2035
2036 if (shift < 0x80)
2037 srcvalue >>= shift;
2038 else
2039 srcvalue <<= (0x100 - shift);
2040
2041 srcvalue = (srcvalue & srcmask) ^ xor;
2042
2043 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2044
2045 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2046
37383650 2047 return 22;
6ee73861
BS		 2048}
2049
37383650 2050static int
6ee73861
BS		 2051init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2052{
2053 /*
2054 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2055 *
2056 * offset (8 bit): opcode
2057 * offset + 1 (16 bit): CRTC port
2058 * offset + 3 (8 bit): CRTC index
2059 * offset + 4 (8 bit): data
2060 *
2061 * Write "data" to index "CRTC index" of "CRTC port"
2062 */
2063 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2064 uint8_t crtcindex = bios->data[offset + 3];
2065 uint8_t data = bios->data[offset + 4];
2066
2067 if (!iexec->execute)
37383650 2068 return 5;
6ee73861
BS		 2069
2070 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2071
37383650 2072 return 5;
6ee73861
BS		 2073}
2074
67eda20e
FJ		 2075static inline void
2076bios_md32(struct nvbios *bios, uint32_t reg,
2077 uint32_t mask, uint32_t val)
2078{
2079 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2080}
2081
2082static uint32_t
2083peek_fb(struct drm_device *dev, struct io_mapping *fb,
2084 uint32_t off)
2085{
2086 uint32_t val = 0;
2087
2088 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 2089 uint8_t __iomem *p =
3e4d3af5 2090 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 2091
0bf9b0e0 2092 val = ioread32(p + (off & ~PAGE_MASK));
67eda20e 2093
3e4d3af5 2094 io_mapping_unmap_atomic(p);
67eda20e
FJ		 2095 }
2096
2097 return val;
2098}
2099
2100static void
2101poke_fb(struct drm_device *dev, struct io_mapping *fb,
2102 uint32_t off, uint32_t val)
2103{
2104 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 2105 uint8_t __iomem *p =
3e4d3af5 2106 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 2107
0bf9b0e0 2108 iowrite32(val, p + (off & ~PAGE_MASK));
67eda20e
FJ		 2109 wmb();
2110
3e4d3af5 2111 io_mapping_unmap_atomic(p);
67eda20e
FJ		 2112 }
2113}
2114
2115static inline bool
2116read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2117 uint32_t off, uint32_t val)
2118{
2119 poke_fb(dev, fb, off, val);
2120 return val == peek_fb(dev, fb, off);
2121}
2122
2123static int
2124nv04_init_compute_mem(struct nvbios *bios)
2125{
2126 struct drm_device *dev = bios->dev;
2127 uint32_t patt = 0xdeadbeef;
2128 struct io_mapping *fb;
2129 int i;
2130
2131 /* Map the framebuffer aperture */
2132 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2133 pci_resource_len(dev->pdev, 1));
2134 if (!fb)
2135 return -ENOMEM;
2136
2137 /* Sequencer and refresh off */
2138 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2139 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2140
2141 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2142 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2143 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2144 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2145
2146 for (i = 0; i < 4; i++)
2147 poke_fb(dev, fb, 4 * i, patt);
2148
2149 poke_fb(dev, fb, 0x400000, patt + 1);
2150
2151 if (peek_fb(dev, fb, 0) == patt + 1) {
2152 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2153 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2154 bios_md32(bios, NV04_PFB_DEBUG_0,
2155 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2156
2157 for (i = 0; i < 4; i++)
2158 poke_fb(dev, fb, 4 * i, patt);
2159
2160 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2161 bios_md32(bios, NV04_PFB_BOOT_0,
2162 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2163 NV04_PFB_BOOT_0_RAM_AMOUNT,
2164 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2165
2166 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2167 (patt & 0xffff0000)) {
2168 bios_md32(bios, NV04_PFB_BOOT_0,
2169 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2170 NV04_PFB_BOOT_0_RAM_AMOUNT,
2171 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2172
0746b5da 2173 } else if (peek_fb(dev, fb, 0) != patt) {
67eda20e
FJ		 2174 if (read_back_fb(dev, fb, 0x800000, patt))
2175 bios_md32(bios, NV04_PFB_BOOT_0,
2176 NV04_PFB_BOOT_0_RAM_AMOUNT,
2177 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2178 else
2179 bios_md32(bios, NV04_PFB_BOOT_0,
2180 NV04_PFB_BOOT_0_RAM_AMOUNT,
2181 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2182
2183 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2184 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2185
2186 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2187 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2188 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2189
2190 }
2191
2192 /* Refresh on, sequencer on */
2193 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2194 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2195
2196 io_mapping_free(fb);
2197 return 0;
2198}
2199
2200static const uint8_t *
2201nv05_memory_config(struct nvbios *bios)
2202{
2203 /* Defaults for BIOSes lacking a memory config table */
2204 static const uint8_t default_config_tab[][2] = {
2205 { 0x24, 0x00 },
2206 { 0x28, 0x00 },
2207 { 0x24, 0x01 },
2208 { 0x1f, 0x00 },
2209 { 0x0f, 0x00 },
2210 { 0x17, 0x00 },
2211 { 0x06, 0x00 },
2212 { 0x00, 0x00 }
2213 };
2214 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2215 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2216
2217 if (bios->legacy.mem_init_tbl_ptr)
2218 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2219 else
2220 return default_config_tab[i];
2221}
2222
2223static int
2224nv05_init_compute_mem(struct nvbios *bios)
2225{
2226 struct drm_device *dev = bios->dev;
2227 const uint8_t *ramcfg = nv05_memory_config(bios);
2228 uint32_t patt = 0xdeadbeef;
2229 struct io_mapping *fb;
2230 int i, v;
2231
2232 /* Map the framebuffer aperture */
2233 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2234 pci_resource_len(dev->pdev, 1));
2235 if (!fb)
2236 return -ENOMEM;
2237
2238 /* Sequencer off */
2239 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2240
2241 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2242 goto out;
2243
2244 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2245
2246 /* If present load the hardcoded scrambling table */
2247 if (bios->legacy.mem_init_tbl_ptr) {
2248 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2249 bios->legacy.mem_init_tbl_ptr + 0x10];
2250
2251 for (i = 0; i < 8; i++)
2252 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2253 ROM32(scramble_tab[i]));
2254 }
2255
2256 /* Set memory type/width/length defaults depending on the straps */
2257 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2258
2259 if (ramcfg[1] & 0x80)
2260 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2261
2262 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2263 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2264
2265 /* Probe memory bus width */
2266 for (i = 0; i < 4; i++)
2267 poke_fb(dev, fb, 4 * i, patt);
2268
2269 if (peek_fb(dev, fb, 0xc) != patt)
2270 bios_md32(bios, NV04_PFB_BOOT_0,
2271 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2272
2273 /* Probe memory length */
2274 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2275
2276 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2277 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2278 !read_back_fb(dev, fb, 0, ++patt)))
2279 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2280 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2281
2282 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2283 !read_back_fb(dev, fb, 0x800000, ++patt))
2284 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2285 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2286
2287 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2288 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2289 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2290
2291out:
2292 /* Sequencer on */
2293 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2294
2295 io_mapping_free(fb);
2296 return 0;
2297}
2298
2299static int
2300nv10_init_compute_mem(struct nvbios *bios)
2301{
2302 struct drm_device *dev = bios->dev;
2303 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2304 const int mem_width[] = { 0x10, 0x00, 0x20 };
2305 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2306 uint32_t patt = 0xdeadbeef;
2307 struct io_mapping *fb;
2308 int i, j, k;
2309
2310 /* Map the framebuffer aperture */
2311 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2312 pci_resource_len(dev->pdev, 1));
2313 if (!fb)
2314 return -ENOMEM;
2315
2316 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2317
2318 /* Probe memory bus width */
2319 for (i = 0; i < mem_width_count; i++) {
2320 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2321
2322 for (j = 0; j < 4; j++) {
2323 for (k = 0; k < 4; k++)
2324 poke_fb(dev, fb, 0x1c, 0);
2325
2326 poke_fb(dev, fb, 0x1c, patt);
2327 poke_fb(dev, fb, 0x3c, 0);
2328
2329 if (peek_fb(dev, fb, 0x1c) == patt)
2330 goto mem_width_found;
2331 }
2332 }
2333
2334mem_width_found:
2335 patt <<= 1;
2336
2337 /* Probe amount of installed memory */
2338 for (i = 0; i < 4; i++) {
2339 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2340
2341 poke_fb(dev, fb, off, patt);
2342 poke_fb(dev, fb, 0, 0);
2343
2344 peek_fb(dev, fb, 0);
2345 peek_fb(dev, fb, 0);
2346 peek_fb(dev, fb, 0);
2347 peek_fb(dev, fb, 0);
2348
2349 if (peek_fb(dev, fb, off) == patt)
2350 goto amount_found;
2351 }
2352
2353 /* IC missing - disable the upper half memory space. */
2354 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2355
2356amount_found:
2357 io_mapping_free(fb);
2358 return 0;
2359}
2360
2361static int
2362nv20_init_compute_mem(struct nvbios *bios)
2363{
2364 struct drm_device *dev = bios->dev;
2365 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2366 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2367 uint32_t amount, off;
2368 struct io_mapping *fb;
2369
2370 /* Map the framebuffer aperture */
2371 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2372 pci_resource_len(dev->pdev, 1));
2373 if (!fb)
2374 return -ENOMEM;
2375
2376 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2377
2378 /* Allow full addressing */
2379 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2380
2381 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2382 for (off = amount; off > 0x2000000; off -= 0x2000000)
2383 poke_fb(dev, fb, off - 4, off);
2384
2385 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2386 if (amount != peek_fb(dev, fb, amount - 4))
2387 /* IC missing - disable the upper half memory space. */
2388 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2389
2390 io_mapping_free(fb);
2391 return 0;
2392}
2393
37383650 2394static int
6ee73861
BS		 2395init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2396{
2397 /*
2398 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2399 *
2400 * offset (8 bit): opcode
2401 *
67eda20e
FJ		 2402 * This opcode is meant to set the PFB memory config registers
2403 * appropriately so that we can correctly calculate how much VRAM it
2404 * has (on nv10 and better chipsets the amount of installed VRAM is
2405 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
6ee73861 2406 *
67eda20e
FJ		 2407 * The implementation of this opcode in general consists of several
2408 * parts:
6ee73861 2409 *
67eda20e
FJ		 2410 * 1) Determination of memory type and density. Only necessary for
2411 * really old chipsets, the memory type reported by the strap bits
2412 * (0x101000) is assumed to be accurate on nv05 and newer.
6ee73861 2413 *
67eda20e
FJ		 2414 * 2) Determination of the memory bus width. Usually done by a cunning
2415 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2416 * seeing whether the written values are read back correctly.
6ee73861 2417 *
67eda20e
FJ		 2418 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2419 * trust the straps.
6ee73861 2420 *
67eda20e
FJ		 2421 * 3) Determination of how many of the card's RAM pads have ICs
2422 * attached, usually done by a cunning combination of writes to an
2423 * offset slightly less than the maximum memory reported by
2424 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
6ee73861 2425 *
67eda20e
FJ		 2426 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2427 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2428 * card show nothing being done for this opcode. Why is it still listed
2429 * in the table?!
6ee73861
BS		 2430 */
2431
2432 /* no iexec->execute check by design */
2433
6ee73861 2434 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
67eda20e 2435 int ret;
6ee73861 2436
67eda20e
FJ		 2437 if (dev_priv->chipset >= 0x40 ||
2438 dev_priv->chipset == 0x1a ||
2439 dev_priv->chipset == 0x1f)
2440 ret = 0;
2441 else if (dev_priv->chipset >= 0x20 &&
2442 dev_priv->chipset != 0x34)
2443 ret = nv20_init_compute_mem(bios);
2444 else if (dev_priv->chipset >= 0x10)
2445 ret = nv10_init_compute_mem(bios);
2446 else if (dev_priv->chipset >= 0x5)
2447 ret = nv05_init_compute_mem(bios);
2448 else
2449 ret = nv04_init_compute_mem(bios);
6ee73861 2450
67eda20e
FJ		 2451 if (ret)
2452 return ret;
6ee73861 2453
37383650 2454 return 1;
6ee73861
BS		 2455}
2456
37383650 2457static int
6ee73861
BS		 2458init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2459{
2460 /*
2461 * INIT_RESET opcode: 0x65 ('e')
2462 *
2463 * offset (8 bit): opcode
2464 * offset + 1 (32 bit): register
2465 * offset + 5 (32 bit): value1
2466 * offset + 9 (32 bit): value2
2467 *
2468 * Assign "value1" to "register", then assign "value2" to "register"
2469 */
2470
2471 uint32_t reg = ROM32(bios->data[offset + 1]);
2472 uint32_t value1 = ROM32(bios->data[offset + 5]);
2473 uint32_t value2 = ROM32(bios->data[offset + 9]);
2474 uint32_t pci_nv_19, pci_nv_20;
2475
2476 /* no iexec->execute check by design */
2477
2478 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
190a4378
FJ		 2479 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2480
6ee73861
BS		 2481 bios_wr32(bios, reg, value1);
2482
2483 udelay(10);
2484
2485 bios_wr32(bios, reg, value2);
2486 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2487
2488 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2489 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2490 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2491
37383650 2492 return 13;
6ee73861
BS		 2493}
2494
37383650 2495static int
6ee73861
BS		 2496init_configure_mem(struct nvbios *bios, uint16_t offset,
2497 struct init_exec *iexec)
2498{
2499 /*
2500 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2501 *
2502 * offset (8 bit): opcode
2503 *
2504 * Equivalent to INIT_DONE on bios version 3 or greater.
2505 * For early bios versions, sets up the memory registers, using values
2506 * taken from the memory init table
2507 */
2508
2509 /* no iexec->execute check by design */
2510
2511 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2512 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2513 uint32_t reg, data;
2514
2515 if (bios->major_version > 2)
ae55321c 2516 return 0;
6ee73861
BS		 2517
2518 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2519 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2520
2521 if (bios->data[meminitoffs] & 1)
2522 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2523
2524 for (reg = ROM32(bios->data[seqtbloffs]);
2525 reg != 0xffffffff;
2526 reg = ROM32(bios->data[seqtbloffs += 4])) {
2527
2528 switch (reg) {
3c7066bc
FJ		 2529 case NV04_PFB_PRE:
2530 data = NV04_PFB_PRE_CMD_PRECHARGE;
6ee73861 2531 break;
3c7066bc
FJ		 2532 case NV04_PFB_PAD:
2533 data = NV04_PFB_PAD_CKE_NORMAL;
6ee73861 2534 break;
3c7066bc
FJ		 2535 case NV04_PFB_REF:
2536 data = NV04_PFB_REF_CMD_REFRESH;
6ee73861
BS		 2537 break;
2538 default:
2539 data = ROM32(bios->data[meminitdata]);
2540 meminitdata += 4;
2541 if (data == 0xffffffff)
2542 continue;
2543 }
2544
2545 bios_wr32(bios, reg, data);
2546 }
2547
37383650 2548 return 1;
6ee73861
BS		 2549}
2550
37383650 2551static int
6ee73861
BS		 2552init_configure_clk(struct nvbios *bios, uint16_t offset,
2553 struct init_exec *iexec)
2554{
2555 /*
2556 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2557 *
2558 * offset (8 bit): opcode
2559 *
2560 * Equivalent to INIT_DONE on bios version 3 or greater.
2561 * For early bios versions, sets up the NVClk and MClk PLLs, using
2562 * values taken from the memory init table
2563 */
2564
2565 /* no iexec->execute check by design */
2566
2567 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2568 int clock;
2569
2570 if (bios->major_version > 2)
ae55321c 2571 return 0;
6ee73861
BS		 2572
2573 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2574 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2575
2576 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2577 if (bios->data[meminitoffs] & 1) /* DDR */
2578 clock *= 2;
2579 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2580
37383650 2581 return 1;
6ee73861
BS		 2582}
2583
37383650 2584static int
6ee73861
BS		 2585init_configure_preinit(struct nvbios *bios, uint16_t offset,
2586 struct init_exec *iexec)
2587{
2588 /*
2589 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2590 *
2591 * offset (8 bit): opcode
2592 *
2593 * Equivalent to INIT_DONE on bios version 3 or greater.
2594 * For early bios versions, does early init, loading ram and crystal
2595 * configuration from straps into CR3C
2596 */
2597
2598 /* no iexec->execute check by design */
2599
2600 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
3c9b2534 2601 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
6ee73861
BS		 2602
2603 if (bios->major_version > 2)
ae55321c 2604 return 0;
6ee73861
BS		 2605
2606 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2607 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2608
37383650 2609 return 1;
6ee73861
BS		 2610}
2611
37383650 2612static int
6ee73861
BS		 2613init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2614{
2615 /*
2616 * INIT_IO opcode: 0x69 ('i')
2617 *
2618 * offset (8 bit): opcode
2619 * offset + 1 (16 bit): CRTC port
2620 * offset + 3 (8 bit): mask
2621 * offset + 4 (8 bit): data
2622 *
2623 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2624 */
2625
2626 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2627 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2628 uint8_t mask = bios->data[offset + 3];
2629 uint8_t data = bios->data[offset + 4];
2630
2631 if (!iexec->execute)
37383650 2632 return 5;
6ee73861
BS		 2633
2634 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2635 offset, crtcport, mask, data);
2636
2637 /*
2638 * I have no idea what this does, but NVIDIA do this magic sequence
2639 * in the places where this INIT_IO happens..
2640 */
2641 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2642 int i;
2643
2644 bios_wr32(bios, 0x614100, (bios_rd32(
2645 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2646
2647 bios_wr32(bios, 0x00e18c, bios_rd32(
2648 bios, 0x00e18c) | 0x00020000);
2649
2650 bios_wr32(bios, 0x614900, (bios_rd32(
2651 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2652
2653 bios_wr32(bios, 0x000200, bios_rd32(
2654 bios, 0x000200) & ~0x40000000);
2655
2656 mdelay(10);
2657
2658 bios_wr32(bios, 0x00e18c, bios_rd32(
2659 bios, 0x00e18c) & ~0x00020000);
2660
2661 bios_wr32(bios, 0x000200, bios_rd32(
2662 bios, 0x000200) | 0x40000000);
2663
2664 bios_wr32(bios, 0x614100, 0x00800018);
2665 bios_wr32(bios, 0x614900, 0x00800018);
2666
2667 mdelay(10);
2668
2669 bios_wr32(bios, 0x614100, 0x10000018);
2670 bios_wr32(bios, 0x614900, 0x10000018);
2671
2672 for (i = 0; i < 3; i++)
2673 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2674 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2675
2676 for (i = 0; i < 2; i++)
2677 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2678 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2679
2680 for (i = 0; i < 3; i++)
2681 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2682 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2683
2684 for (i = 0; i < 2; i++)
2685 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2686 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2687
2688 for (i = 0; i < 2; i++)
2689 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2690 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2691 return 5;
6ee73861
BS		 2692 }
2693
2694 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2695 data);
37383650 2696 return 5;
6ee73861
BS		 2697}
2698
37383650 2699static int
6ee73861
BS		 2700init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2701{
2702 /*
2703 * INIT_SUB opcode: 0x6B ('k')
2704 *
2705 * offset (8 bit): opcode
2706 * offset + 1 (8 bit): script number
2707 *
2708 * Execute script number "script number", as a subroutine
2709 */
2710
2711 uint8_t sub = bios->data[offset + 1];
2712
2713 if (!iexec->execute)
37383650 2714 return 2;
6ee73861
BS		 2715
2716 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2717
2718 parse_init_table(bios,
2719 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2720 iexec);
2721
2722 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2723
37383650 2724 return 2;
6ee73861
BS		 2725}
2726
37383650 2727static int
6ee73861
BS		 2728init_ram_condition(struct nvbios *bios, uint16_t offset,
2729 struct init_exec *iexec)
2730{
2731 /*
2732 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2733 *
2734 * offset (8 bit): opcode
2735 * offset + 1 (8 bit): mask
2736 * offset + 2 (8 bit): cmpval
2737 *
3c7066bc 2738 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
6ee73861
BS		 2739 * If condition not met skip subsequent opcodes until condition is
2740 * inverted (INIT_NOT), or we hit INIT_RESUME
2741 */
2742
2743 uint8_t mask = bios->data[offset + 1];
2744 uint8_t cmpval = bios->data[offset + 2];
2745 uint8_t data;
2746
2747 if (!iexec->execute)
37383650 2748 return 3;
6ee73861 2749
3c7066bc 2750 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
6ee73861
BS		 2751
2752 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2753 offset, data, cmpval);
2754
2755 if (data == cmpval)
2756 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2757 else {
2758 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2759 iexec->execute = false;
2760 }
2761
37383650 2762 return 3;
6ee73861
BS		 2763}
2764
37383650 2765static int
6ee73861
BS		 2766init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2767{
2768 /*
2769 * INIT_NV_REG opcode: 0x6E ('n')
2770 *
2771 * offset (8 bit): opcode
2772 * offset + 1 (32 bit): register
2773 * offset + 5 (32 bit): mask
2774 * offset + 9 (32 bit): data
2775 *
2776 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2777 */
2778
2779 uint32_t reg = ROM32(bios->data[offset + 1]);
2780 uint32_t mask = ROM32(bios->data[offset + 5]);
2781 uint32_t data = ROM32(bios->data[offset + 9]);
2782
2783 if (!iexec->execute)
37383650 2784 return 13;
6ee73861
BS		 2785
2786 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2787 offset, reg, mask, data);
2788
2789 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2790
37383650 2791 return 13;
6ee73861
BS		 2792}
2793
37383650 2794static int
6ee73861
BS		 2795init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2796{
2797 /*
2798 * INIT_MACRO opcode: 0x6F ('o')
2799 *
2800 * offset (8 bit): opcode
2801 * offset + 1 (8 bit): macro number
2802 *
2803 * Look up macro index "macro number" in the macro index table.
2804 * The macro index table entry has 1 byte for the index in the macro
2805 * table, and 1 byte for the number of times to repeat the macro.
2806 * The macro table entry has 4 bytes for the register address and
2807 * 4 bytes for the value to write to that register
2808 */
2809
2810 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2811 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2812 uint8_t macro_tbl_idx = bios->data[tmp];
2813 uint8_t count = bios->data[tmp + 1];
2814 uint32_t reg, data;
2815 int i;
2816
2817 if (!iexec->execute)
37383650 2818 return 2;
6ee73861
BS		 2819
2820 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2821 "Count: 0x%02X\n",
2822 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2823
2824 for (i = 0; i < count; i++) {
2825 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2826
2827 reg = ROM32(bios->data[macroentryptr]);
2828 data = ROM32(bios->data[macroentryptr + 4]);
2829
2830 bios_wr32(bios, reg, data);
2831 }
2832
37383650 2833 return 2;
6ee73861
BS		 2834}
2835
37383650 2836static int
6ee73861
BS		 2837init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2838{
2839 /*
2840 * INIT_DONE opcode: 0x71 ('q')
2841 *
2842 * offset (8 bit): opcode
2843 *
2844 * End the current script
2845 */
2846
2847 /* mild retval abuse to stop parsing this table */
37383650 2848 return 0;
6ee73861
BS		 2849}
2850
37383650 2851static int
6ee73861
BS		 2852init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2853{
2854 /*
2855 * INIT_RESUME opcode: 0x72 ('r')
2856 *
2857 * offset (8 bit): opcode
2858 *
2859 * End the current execute / no-execute condition
2860 */
2861
2862 if (iexec->execute)
37383650 2863 return 1;
6ee73861
BS		 2864
2865 iexec->execute = true;
2866 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2867
37383650 2868 return 1;
6ee73861
BS		 2869}
2870
37383650 2871static int
6ee73861
BS		 2872init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2873{
2874 /*
2875 * INIT_TIME opcode: 0x74 ('t')
2876 *
2877 * offset (8 bit): opcode
2878 * offset + 1 (16 bit): time
2879 *
2880 * Sleep for "time" microseconds.
2881 */
2882
2883 unsigned time = ROM16(bios->data[offset + 1]);
2884
2885 if (!iexec->execute)
37383650 2886 return 3;
6ee73861
BS		 2887
2888 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2889 offset, time);
2890
2891 if (time < 1000)
2892 udelay(time);
2893 else
c7ca4d1b 2894 mdelay((time + 900) / 1000);
6ee73861 2895
37383650 2896 return 3;
6ee73861
BS		 2897}
2898
37383650 2899static int
6ee73861
BS		 2900init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2901{
2902 /*
2903 * INIT_CONDITION opcode: 0x75 ('u')
2904 *
2905 * offset (8 bit): opcode
2906 * offset + 1 (8 bit): condition number
2907 *
2908 * Check condition "condition number" in the condition table.
2909 * If condition not met skip subsequent opcodes until condition is
2910 * inverted (INIT_NOT), or we hit INIT_RESUME
2911 */
2912
2913 uint8_t cond = bios->data[offset + 1];
2914
2915 if (!iexec->execute)
37383650 2916 return 2;
6ee73861
BS		 2917
2918 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2919
2920 if (bios_condition_met(bios, offset, cond))
2921 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2922 else {
2923 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2924 iexec->execute = false;
2925 }
2926
37383650 2927 return 2;
6ee73861
BS		 2928}
2929
37383650 2930static int
6ee73861
BS		 2931init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2932{
2933 /*
2934 * INIT_IO_CONDITION opcode: 0x76
2935 *
2936 * offset (8 bit): opcode
2937 * offset + 1 (8 bit): condition number
2938 *
2939 * Check condition "condition number" in the io condition table.
2940 * If condition not met skip subsequent opcodes until condition is
2941 * inverted (INIT_NOT), or we hit INIT_RESUME
2942 */
2943
2944 uint8_t cond = bios->data[offset + 1];
2945
2946 if (!iexec->execute)
37383650 2947 return 2;
6ee73861
BS		 2948
2949 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2950
2951 if (io_condition_met(bios, offset, cond))
2952 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2953 else {
2954 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2955 iexec->execute = false;
2956 }
2957
37383650 2958 return 2;
6ee73861
BS		 2959}
2960
37383650 2961static int
6ee73861
BS		 2962init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2963{
2964 /*
2965 * INIT_INDEX_IO opcode: 0x78 ('x')
2966 *
2967 * offset (8 bit): opcode
2968 * offset + 1 (16 bit): CRTC port
2969 * offset + 3 (8 bit): CRTC index
2970 * offset + 4 (8 bit): mask
2971 * offset + 5 (8 bit): data
2972 *
2973 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2974 * OR with "data", write-back
2975 */
2976
2977 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2978 uint8_t crtcindex = bios->data[offset + 3];
2979 uint8_t mask = bios->data[offset + 4];
2980 uint8_t data = bios->data[offset + 5];
2981 uint8_t value;
2982
2983 if (!iexec->execute)
37383650 2984 return 6;
6ee73861
BS		 2985
2986 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2987 "Data: 0x%02X\n",
2988 offset, crtcport, crtcindex, mask, data);
2989
2990 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2991 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2992
37383650 2993 return 6;
6ee73861
BS		 2994}
2995
37383650 2996static int
6ee73861
BS		 2997init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2998{
2999 /*
3000 * INIT_PLL opcode: 0x79 ('y')
3001 *
3002 * offset (8 bit): opcode
3003 * offset + 1 (32 bit): register
3004 * offset + 5 (16 bit): freq
3005 *
3006 * Set PLL register "register" to coefficients for frequency (10kHz)
3007 * "freq"
3008 */
3009
3010 uint32_t reg = ROM32(bios->data[offset + 1]);
3011 uint16_t freq = ROM16(bios->data[offset + 5]);
3012
3013 if (!iexec->execute)
37383650 3014 return 7;
6ee73861
BS		 3015
3016 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3017
3018 setPLL(bios, reg, freq * 10);
3019
37383650 3020 return 7;
6ee73861
BS		 3021}
3022
37383650 3023static int
6ee73861
BS		 3024init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3025{
3026 /*
3027 * INIT_ZM_REG opcode: 0x7A ('z')
3028 *
3029 * offset (8 bit): opcode
3030 * offset + 1 (32 bit): register
3031 * offset + 5 (32 bit): value
3032 *
3033 * Assign "value" to "register"
3034 */
3035
3036 uint32_t reg = ROM32(bios->data[offset + 1]);
3037 uint32_t value = ROM32(bios->data[offset + 5]);
3038
3039 if (!iexec->execute)
37383650 3040 return 9;
6ee73861
BS		 3041
3042 if (reg == 0x000200)
3043 value |= 1;
3044
3045 bios_wr32(bios, reg, value);
3046
37383650 3047 return 9;
6ee73861
BS		 3048}
3049
37383650 3050static int
6ee73861
BS		 3051init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3052 struct init_exec *iexec)
3053{
3054 /*
3055 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3056 *
3057 * offset (8 bit): opcode
3058 * offset + 1 (8 bit): PLL type
3059 * offset + 2 (32 bit): frequency 0
3060 *
3061 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3062 * ram_restrict_table_ptr. The value read from there is used to select
3063 * a frequency from the table starting at 'frequency 0' to be
3064 * programmed into the PLL corresponding to 'type'.
3065 *
3066 * The PLL limits table on cards using this opcode has a mapping of
3067 * 'type' to the relevant registers.
3068 */
3069
3070 struct drm_device *dev = bios->dev;
3071 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3072 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3073 uint8_t type = bios->data[offset + 1];
3074 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3075 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 3076 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 3077 int i;
3078
3079 if (!iexec->execute)
37383650 3080 return len;
6ee73861
BS		 3081
3082 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3083 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 3084 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 3085 }
3086
3087 entry = pll_limits + pll_limits[1];
3088 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3089 if (entry[0] == type) {
3090 uint32_t reg = ROM32(entry[3]);
3091
3092 BIOSLOG(bios, "0x%04X: "
3093 "Type %02x Reg 0x%08x Freq %dKHz\n",
3094 offset, type, reg, freq);
3095
3096 setPLL(bios, reg, freq);
37383650 3097 return len;
6ee73861
BS		 3098 }
3099 }
3100
3101 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 3102 return len;
6ee73861
BS		 3103}
3104
37383650 3105static int
6ee73861
BS		 3106init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3107{
3108 /*
3109 * INIT_8C opcode: 0x8C ('')
3110 *
3111 * NOP so far....
3112 *
3113 */
3114
37383650 3115 return 1;
6ee73861
BS		 3116}
3117
37383650 3118static int
6ee73861
BS		 3119init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3120{
3121 /*
3122 * INIT_8D opcode: 0x8D ('')
3123 *
3124 * NOP so far....
3125 *
3126 */
3127
37383650 3128 return 1;
6ee73861
BS		 3129}
3130
75139063
BS		 3131static void
3132init_gpio_unknv50(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3133{
3134 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
3135 u32 r, s, v;
3136
3137 /* Not a clue, needs de-magicing */
3138 r = nv50_gpio_ctl[gpio->line >> 4];
3139 s = (gpio->line & 0x0f);
3140 v = bios_rd32(bios, r) & ~(0x00010001 << s);
3141 switch ((gpio->entry & 0x06000000) >> 25) {
3142 case 1:
3143 v |= (0x00000001 << s);
3144 break;
3145 case 2:
3146 v |= (0x00010000 << s);
3147 break;
3148 default:
3149 break;
3150 }
3151
3152 bios_wr32(bios, r, v);
3153}
3154
3155static void
3156init_gpio_unknvd0(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3157{
3158 u32 v, i;
3159
3160 v = bios_rd32(bios, 0x00d610 + (gpio->line * 4));
3161 v &= 0xffffff00;
3162 v |= (gpio->entry & 0x00ff0000) >> 16;
3163 bios_wr32(bios, 0x00d610 + (gpio->line * 4), v);
3164
3165 i = (gpio->entry & 0x1f000000) >> 24;
3166 if (i) {
3167 v = bios_rd32(bios, 0x00d640 + ((i - 1) * 4));
3168 v &= 0xffffff00;
3169 v |= gpio->line;
3170 bios_wr32(bios, 0x00d640 + ((i - 1) * 4), v);
3171 }
3172}
3173
37383650 3174static int
6ee73861
BS		 3175init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3176{
3177 /*
3178 * INIT_GPIO opcode: 0x8E ('')
3179 *
3180 * offset (8 bit): opcode
3181 *
3182 * Loop over all entries in the DCB GPIO table, and initialise
3183 * each GPIO according to various values listed in each entry
3184 */
3185
2535d71c 3186 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
ee2e0131 3187 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
6ee73861
BS		 3188 int i;
3189
080feda5 3190 if (dev_priv->card_type < NV_50) {
2535d71c 3191 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
309b8c89 3192 return 1;
6ee73861
BS		 3193 }
3194
2535d71c
BS		 3195 if (!iexec->execute)
3196 return 1;
6ee73861 3197
2535d71c
BS		 3198 for (i = 0; i < bios->dcb.gpio.entries; i++) {
3199 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
6ee73861 3200
2535d71c 3201 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 3202
73db4bed
BS		 3203 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
3204 offset, gpio->tag, gpio->state_default);
6ee73861 3205
75139063
BS		 3206 if (!bios->execute)
3207 continue;
3208
3209 pgpio->set(bios->dev, gpio->tag, gpio->state_default);
3210 if (dev_priv->card_type < NV_D0)
3211 init_gpio_unknv50(bios, gpio);
3212 else
3213 init_gpio_unknvd0(bios, gpio);
6ee73861
BS		 3214 }
3215
37383650 3216 return 1;
6ee73861
BS		 3217}
3218
37383650 3219static int
6ee73861
BS		 3220init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3221 struct init_exec *iexec)
3222{
3223 /*
3224 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3225 *
3226 * offset (8 bit): opcode
3227 * offset + 1 (32 bit): reg
3228 * offset + 5 (8 bit): regincrement
3229 * offset + 6 (8 bit): count
3230 * offset + 7 (32 bit): value 1,1
3231 * ...
3232 *
3233 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3234 * ram_restrict_table_ptr. The value read from here is 'n', and
3235 * "value 1,n" gets written to "reg". This repeats "count" times and on
3236 * each iteration 'm', "reg" increases by "regincrement" and
3237 * "value m,n" is used. The extent of n is limited by a number read
3238 * from the 'M' BIT table, herein called "blocklen"
3239 */
3240
3241 uint32_t reg = ROM32(bios->data[offset + 1]);
3242 uint8_t regincrement = bios->data[offset + 5];
3243 uint8_t count = bios->data[offset + 6];
3244 uint32_t strap_ramcfg, data;
37383650
MK		 3245 /* previously set by 'M' BIT table */
3246 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3247 int len = 7 + count * blocklen;
6ee73861
BS		 3248 uint8_t index;
3249 int i;
3250
309b8c89 3251 /* critical! to know the length of the opcode */;
6ee73861
BS		 3252 if (!blocklen) {
3253 NV_ERROR(bios->dev,
3254 "0x%04X: Zero block length - has the M table "
3255 "been parsed?\n", offset);
9170a824 3256 return -EINVAL;
6ee73861
BS		 3257 }
3258
309b8c89
BS		 3259 if (!iexec->execute)
3260 return len;
3261
6ee73861
BS		 3262 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3263 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3264
3265 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3266 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3267 offset, reg, regincrement, count, strap_ramcfg, index);
3268
3269 for (i = 0; i < count; i++) {
3270 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3271
3272 bios_wr32(bios, reg, data);
3273
3274 reg += regincrement;
3275 }
3276
37383650 3277 return len;
6ee73861
BS		 3278}
3279
37383650 3280static int
6ee73861
BS		 3281init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3282{
3283 /*
3284 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3285 *
3286 * offset (8 bit): opcode
3287 * offset + 1 (32 bit): src reg
3288 * offset + 5 (32 bit): dst reg
3289 *
3290 * Put contents of "src reg" into "dst reg"
3291 */
3292
3293 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3294 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3295
3296 if (!iexec->execute)
37383650 3297 return 9;
6ee73861
BS		 3298
3299 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3300
37383650 3301 return 9;
6ee73861
BS		 3302}
3303
37383650 3304static int
6ee73861
BS		 3305init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3306 struct init_exec *iexec)
3307{
3308 /*
3309 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3310 *
3311 * offset (8 bit): opcode
3312 * offset + 1 (32 bit): dst reg
3313 * offset + 5 (8 bit): count
3314 * offset + 6 (32 bit): data 1
3315 * ...
3316 *
3317 * For each of "count" values write "data n" to "dst reg"
3318 */
3319
3320 uint32_t reg = ROM32(bios->data[offset + 1]);
3321 uint8_t count = bios->data[offset + 5];
37383650 3322 int len = 6 + count * 4;
6ee73861
BS		 3323 int i;
3324
3325 if (!iexec->execute)
37383650 3326 return len;
6ee73861
BS		 3327
3328 for (i = 0; i < count; i++) {
3329 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3330 bios_wr32(bios, reg, data);
3331 }
3332
37383650 3333 return len;
6ee73861
BS		 3334}
3335
37383650 3336static int
6ee73861
BS		 3337init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3338{
3339 /*
3340 * INIT_RESERVED opcode: 0x92 ('')
3341 *
3342 * offset (8 bit): opcode
3343 *
3344 * Seemingly does nothing
3345 */
3346
37383650 3347 return 1;
6ee73861
BS		 3348}
3349
37383650 3350static int
6ee73861
BS		 3351init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3352{
3353 /*
3354 * INIT_96 opcode: 0x96 ('')
3355 *
3356 * offset (8 bit): opcode
3357 * offset + 1 (32 bit): sreg
3358 * offset + 5 (8 bit): sshift
3359 * offset + 6 (8 bit): smask
3360 * offset + 7 (8 bit): index
3361 * offset + 8 (32 bit): reg
3362 * offset + 12 (32 bit): mask
3363 * offset + 16 (8 bit): shift
3364 *
3365 */
3366
3367 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3368 uint32_t reg = ROM32(bios->data[offset + 8]);
3369 uint32_t mask = ROM32(bios->data[offset + 12]);
3370 uint32_t val;
3371
3372 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3373 if (bios->data[offset + 5] < 0x80)
3374 val >>= bios->data[offset + 5];
3375 else
3376 val <<= (0x100 - bios->data[offset + 5]);
3377 val &= bios->data[offset + 6];
3378
3379 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3380 val <<= bios->data[offset + 16];
3381
3382 if (!iexec->execute)
37383650 3383 return 17;
6ee73861
BS		 3384
3385 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3386 return 17;
6ee73861
BS		 3387}
3388
37383650 3389static int
6ee73861
BS		 3390init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3391{
3392 /*
3393 * INIT_97 opcode: 0x97 ('')
3394 *
3395 * offset (8 bit): opcode
3396 * offset + 1 (32 bit): register
3397 * offset + 5 (32 bit): mask
3398 * offset + 9 (32 bit): value
3399 *
3400 * Adds "value" to "register" preserving the fields specified
3401 * by "mask"
3402 */
3403
3404 uint32_t reg = ROM32(bios->data[offset + 1]);
3405 uint32_t mask = ROM32(bios->data[offset + 5]);
3406 uint32_t add = ROM32(bios->data[offset + 9]);
3407 uint32_t val;
3408
3409 val = bios_rd32(bios, reg);
3410 val = (val & mask) | ((val + add) & ~mask);
3411
3412 if (!iexec->execute)
37383650 3413 return 13;
6ee73861
BS		 3414
3415 bios_wr32(bios, reg, val);
37383650 3416 return 13;
6ee73861
BS		 3417}
3418
37383650 3419static int
6ee73861
BS		 3420init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3421{
3422 /*
3423 * INIT_AUXCH opcode: 0x98 ('')
3424 *
3425 * offset (8 bit): opcode
3426 * offset + 1 (32 bit): address
3427 * offset + 5 (8 bit): count
3428 * offset + 6 (8 bit): mask 0
3429 * offset + 7 (8 bit): data 0
3430 * ...
3431 *
3432 */
3433
3434 struct drm_device *dev = bios->dev;
3435 struct nouveau_i2c_chan *auxch;
3436 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3437 uint8_t count = bios->data[offset + 5];
3438 int len = 6 + count * 2;
6ee73861
BS		 3439 int ret, i;
3440
3441 if (!bios->display.output) {
3442 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
309b8c89 3443 return len;
6ee73861
BS		 3444 }
3445
3446 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3447 if (!auxch) {
3448 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3449 bios->display.output->i2c_index);
309b8c89 3450 return len;
6ee73861
BS		 3451 }
3452
3453 if (!iexec->execute)
37383650 3454 return len;
6ee73861
BS		 3455
3456 offset += 6;
37383650 3457 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3458 uint8_t data;
3459
3460 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3461 if (ret) {
3462 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
309b8c89 3463 return len;
6ee73861
BS		 3464 }
3465
3466 data &= bios->data[offset + 0];
3467 data |= bios->data[offset + 1];
3468
3469 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3470 if (ret) {
3471 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3472 return len;
6ee73861
BS		 3473 }
3474 }
3475
37383650 3476 return len;
6ee73861
BS		 3477}
3478
37383650 3479static int
6ee73861
BS		 3480init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3481{
3482 /*
3483 * INIT_ZM_AUXCH opcode: 0x99 ('')
3484 *
3485 * offset (8 bit): opcode
3486 * offset + 1 (32 bit): address
3487 * offset + 5 (8 bit): count
3488 * offset + 6 (8 bit): data 0
3489 * ...
3490 *
3491 */
3492
3493 struct drm_device *dev = bios->dev;
3494 struct nouveau_i2c_chan *auxch;
3495 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3496 uint8_t count = bios->data[offset + 5];
3497 int len = 6 + count;
6ee73861
BS		 3498 int ret, i;
3499
3500 if (!bios->display.output) {
3501 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
309b8c89 3502 return len;
6ee73861
BS		 3503 }
3504
3505 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3506 if (!auxch) {
3507 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3508 bios->display.output->i2c_index);
309b8c89 3509 return len;
6ee73861
BS		 3510 }
3511
3512 if (!iexec->execute)
37383650 3513 return len;
6ee73861
BS		 3514
3515 offset += 6;
37383650 3516 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3517 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3518 if (ret) {
3519 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3520 return len;
6ee73861
BS		 3521 }
3522 }
3523
37383650 3524 return len;
6ee73861
BS		 3525}
3526
b715d640
MK		 3527static int
3528init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3529{
3530 /*
3531 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3532 *
3533 * offset (8 bit): opcode
3534 * offset + 1 (8 bit): DCB I2C table entry index
3535 * offset + 2 (8 bit): I2C slave address
3536 * offset + 3 (16 bit): I2C register
3537 * offset + 5 (8 bit): mask
3538 * offset + 6 (8 bit): data
3539 *
3540 * Read the register given by "I2C register" on the device addressed
3541 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3542 * entry index". Compare the result AND "mask" to "data".
3543 * If they're not equal, skip subsequent opcodes until condition is
3544 * inverted (INIT_NOT), or we hit INIT_RESUME
3545 */
3546
3547 uint8_t i2c_index = bios->data[offset + 1];
3548 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3549 uint8_t reglo = bios->data[offset + 3];
3550 uint8_t reghi = bios->data[offset + 4];
3551 uint8_t mask = bios->data[offset + 5];
3552 uint8_t data = bios->data[offset + 6];
3553 struct nouveau_i2c_chan *chan;
3554 uint8_t buf0[2] = { reghi, reglo };
3555 uint8_t buf1[1];
3556 struct i2c_msg msg[2] = {
3557 { i2c_address, 0, 1, buf0 },
3558 { i2c_address, I2C_M_RD, 1, buf1 },
3559 };
3560 int ret;
3561
3562 /* no execute check by design */
3563
3564 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3565 offset, i2c_index, i2c_address);
3566
3567 chan = init_i2c_device_find(bios->dev, i2c_index);
3568 if (!chan)
3569 return -ENODEV;
3570
3571
3572 ret = i2c_transfer(&chan->adapter, msg, 2);
3573 if (ret < 0) {
3574 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3575 "Mask: 0x%02X, Data: 0x%02X\n",
3576 offset, reghi, reglo, mask, data);
3577 iexec->execute = 0;
3578 return 7;
3579 }
3580
3581 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3582 "Mask: 0x%02X, Data: 0x%02X\n",
3583 offset, reghi, reglo, buf1[0], mask, data);
3584
3585 iexec->execute = ((buf1[0] & mask) == data);
3586
3587 return 7;
3588}
3589
6ee73861
BS		 3590static struct init_tbl_entry itbl_entry[] = {
3591 /* command name , id , length , offset , mult , command handler */
3592 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3593 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3594 { "INIT_REPEAT" , 0x33, init_repeat },
3595 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3596 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3597 { "INIT_COPY" , 0x37, init_copy },
3598 { "INIT_NOT" , 0x38, init_not },
3599 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3600 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3601 { "INIT_OP_3B" , 0x3B, init_op_3b },
3602 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3603 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3604 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3605 { "INIT_PLL2" , 0x4B, init_pll2 },
3606 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3607 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3608 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3609 { "INIT_TMDS" , 0x4F, init_tmds },
3610 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3611 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3612 { "INIT_CR" , 0x52, init_cr },
3613 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3614 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3615 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
e3a1924f 3616 { "INIT_LTIME" , 0x57, init_ltime },
37383650 3617 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3618 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650 3619 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
ec64a408 3620 { "INIT_JUMP" , 0x5C, init_jump },
b715d640 3621 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
37383650
MK		 3622 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3623 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3624 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3625 { "INIT_RESET" , 0x65, init_reset },
3626 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3627 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3628 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3629 { "INIT_IO" , 0x69, init_io },
3630 { "INIT_SUB" , 0x6B, init_sub },
3631 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3632 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3633 { "INIT_MACRO" , 0x6F, init_macro },
3634 { "INIT_DONE" , 0x71, init_done },
3635 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3636 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3637 { "INIT_TIME" , 0x74, init_time },
3638 { "INIT_CONDITION" , 0x75, init_condition },
3639 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3640 { "INIT_INDEX_IO" , 0x78, init_index_io },
3641 { "INIT_PLL" , 0x79, init_pll },
3642 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3643 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3644 { "INIT_8C" , 0x8C, init_8c },
3645 { "INIT_8D" , 0x8D, init_8d },
3646 { "INIT_GPIO" , 0x8E, init_gpio },
3647 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3648 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3649 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3650 { "INIT_RESERVED" , 0x92, init_reserved },
3651 { "INIT_96" , 0x96, init_96 },
3652 { "INIT_97" , 0x97, init_97 },
3653 { "INIT_AUXCH" , 0x98, init_auxch },
3654 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
b715d640 3655 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
37383650 3656 { NULL , 0 , NULL }
6ee73861
BS		 3657};
3658
6ee73861
BS		 3659#define MAX_TABLE_OPS 1000
3660
3661static int
ec64a408 3662parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
6ee73861
BS		 3663{
3664 /*
3665 * Parses all commands in an init table.
3666 *
3667 * We start out executing all commands found in the init table. Some
3668 * opcodes may change the status of iexec->execute to SKIP, which will
3669 * cause the following opcodes to perform no operation until the value
3670 * is changed back to EXECUTE.
3671 */
3672
92b96187 3673 int count = 0, i, ret;
6ee73861
BS		 3674 uint8_t id;
3675
a8e415d3
BS		 3676 /* catch NULL script pointers */
3677 if (offset == 0)
3678 return 0;
3679
6ee73861
BS		 3680 /*
3681 * Loop until INIT_DONE causes us to break out of the loop
3682 * (or until offset > bios length just in case... )
3683 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3684 */
3685 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3686 id = bios->data[offset];
3687
3688 /* Find matching id in itbl_entry */
3689 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3690 ;
3691
92b96187 3692 if (!itbl_entry[i].name) {
6ee73861
BS		 3693 NV_ERROR(bios->dev,
3694 "0x%04X: Init table command not found: "
3695 "0x%02X\n", offset, id);
3696 return -ENOENT;
3697 }
92b96187
BS		 3698
3699 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3700 itbl_entry[i].id, itbl_entry[i].name);
3701
3702 /* execute eventual command handler */
3703 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3704 if (ret < 0) {
3705 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3706 "table opcode: %s %d\n", offset,
3707 itbl_entry[i].name, ret);
3708 }
3709
3710 if (ret <= 0)
3711 break;
3712
3713 /*
3714 * Add the offset of the current command including all data
3715 * of that command. The offset will then be pointing on the
3716 * next op code.
3717 */
3718 offset += ret;
6ee73861
BS		 3719 }
3720
3721 if (offset >= bios->length)
3722 NV_WARN(bios->dev,
3723 "Offset 0x%04X greater than known bios image length. "
3724 "Corrupt image?\n", offset);
3725 if (count >= MAX_TABLE_OPS)
3726 NV_WARN(bios->dev,
3727 "More than %d opcodes to a table is unlikely, "
3728 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3729
3730 return 0;
3731}
3732
3733static void
3734parse_init_tables(struct nvbios *bios)
3735{
3736 /* Loops and calls parse_init_table() for each present table. */
3737
3738 int i = 0;
3739 uint16_t table;
3740 struct init_exec iexec = {true, false};
3741
3742 if (bios->old_style_init) {
3743 if (bios->init_script_tbls_ptr)
3744 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3745 if (bios->extra_init_script_tbl_ptr)
3746 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3747
3748 return;
3749 }
3750
3751 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3752 NV_INFO(bios->dev,
3753 "Parsing VBIOS init table %d at offset 0x%04X\n",
3754 i / 2, table);
3755 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3756
3757 parse_init_table(bios, table, &iexec);
3758 i += 2;
3759 }
3760}
3761
3762static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3763{
3764 int compare_record_len, i = 0;
3765 uint16_t compareclk, scriptptr = 0;
3766
3767 if (bios->major_version < 5) /* pre BIT */
3768 compare_record_len = 3;
3769 else
3770 compare_record_len = 4;
3771
3772 do {
3773 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3774 if (pxclk >= compareclk * 10) {
3775 if (bios->major_version < 5) {
3776 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3777 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3778 } else
3779 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3780 break;
3781 }
3782 i++;
3783 } while (compareclk);
3784
3785 return scriptptr;
3786}
3787
3788static void
3789run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3790 struct dcb_entry *dcbent, int head, bool dl)
3791{
3792 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3793 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3794 struct init_exec iexec = {true, false};
3795
3796 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3797 scriptptr);
3798 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3799 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3800 /* note: if dcb entries have been merged, index may be misleading */
3801 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3802 parse_init_table(bios, scriptptr, &iexec);
3803
3804 nv04_dfp_bind_head(dev, dcbent, head, dl);
3805}
3806
3807static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3808{
3809 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3810 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3811 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3812 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3813
3814 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3815 return -EINVAL;
3816
3817 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3818
3819 if (script == LVDS_PANEL_OFF) {
3820 /* off-on delay in ms */
c7ca4d1b 3821 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
6ee73861
BS		 3822 }
3823#ifdef __powerpc__
3824 /* Powerbook specific quirks */
d31e078d
FJ		 3825 if (script == LVDS_RESET &&
3826 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3827 dev->pci_device == 0x0329))
3828 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
6ee73861
BS		 3829#endif
3830
3831 return 0;
3832}
3833
3834static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3835{
3836 /*
3837 * The BIT LVDS table's header has the information to setup the
3838 * necessary registers. Following the standard 4 byte header are:
3839 * A bitmask byte and a dual-link transition pxclk value for use in
3840 * selecting the init script when not using straps; 4 script pointers
3841 * for panel power, selected by output and on/off; and 8 table pointers
3842 * for panel init, the needed one determined by output, and bits in the
3843 * conf byte. These tables are similar to the TMDS tables, consisting
3844 * of a list of pxclks and script pointers.
3845 */
3846 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3847 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3848 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3849 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3850
3851 /*
3852 * For now we assume version 3.0 table - g80 support will need some
3853 * changes
3854 */
3855
3856 switch (script) {
3857 case LVDS_INIT:
3858 return -ENOSYS;
3859 case LVDS_BACKLIGHT_ON:
3860 case LVDS_PANEL_ON:
3861 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3862 break;
3863 case LVDS_BACKLIGHT_OFF:
3864 case LVDS_PANEL_OFF:
3865 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3866 break;
3867 case LVDS_RESET:
f3bbb9cc
BS		 3868 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3869 if (dcbent->or == 4)
3870 clktable += 8;
3871
6ee73861
BS		 3872 if (dcbent->lvdsconf.use_straps_for_mode) {
3873 if (bios->fp.dual_link)
f3bbb9cc
BS		 3874 clktable += 4;
3875 if (bios->fp.if_is_24bit)
3876 clktable += 2;
6ee73861
BS		 3877 } else {
3878 /* using EDID */
f3bbb9cc 3879 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3880
3881 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3882 clktable += 4;
3883 cmpval_24bit <<= 1;
6ee73861 3884 }
f3bbb9cc
BS		 3885
3886 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3887 clktable += 2;
6ee73861
BS		 3888 }
3889
f3bbb9cc 3890 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3891 if (!clktable) {
3892 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3893 return -ENOENT;
3894 }
3895 scriptptr = clkcmptable(bios, clktable, pxclk);
3896 }
3897
3898 if (!scriptptr) {
3899 NV_ERROR(dev, "LVDS output init script not found\n");
3900 return -ENOENT;
3901 }
3902 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3903
3904 return 0;
3905}
3906
3907int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3908{
3909 /*
3910 * LVDS operations are multiplexed in an effort to present a single API
3911 * which works with two vastly differing underlying structures.
3912 * This acts as the demux
3913 */
3914
3915 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3916 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3917 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3918 uint32_t sel_clk_binding, sel_clk;
3919 int ret;
3920
3921 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3922 (lvds_ver >= 0x30 && script == LVDS_INIT))
3923 return 0;
3924
3925 if (!bios->fp.lvds_init_run) {
3926 bios->fp.lvds_init_run = true;
3927 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3928 }
3929
3930 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3931 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3932 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3933 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3934
3935 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3936
3937 /* don't let script change pll->head binding */
3938 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3939
3940 if (lvds_ver < 0x30)
3941 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3942 else
3943 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3944
3945 bios->fp.last_script_invoc = (script << 1 | head);
3946
3947 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3948 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3949 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3950 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3951
3952 return ret;
3953}
3954
3955struct lvdstableheader {
3956 uint8_t lvds_ver, headerlen, recordlen;
3957};
3958
3959static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3960{
3961 /*
3962 * BMP version (0xa) LVDS table has a simple header of version and
3963 * record length. The BIT LVDS table has the typical BIT table header:
3964 * version byte, header length byte, record length byte, and a byte for
3965 * the maximum number of records that can be held in the table.
3966 */
3967
3968 uint8_t lvds_ver, headerlen, recordlen;
3969
3970 memset(lth, 0, sizeof(struct lvdstableheader));
3971
3972 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3973 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3974 return -EINVAL;
3975 }
3976
3977 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3978
3979 switch (lvds_ver) {
3980 case 0x0a: /* pre NV40 */
3981 headerlen = 2;
3982 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3983 break;
3984 case 0x30: /* NV4x */
3985 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3986 if (headerlen < 0x1f) {
3987 NV_ERROR(dev, "LVDS table header not understood\n");
3988 return -EINVAL;
3989 }
3990 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3991 break;
3992 case 0x40: /* G80/G90 */
3993 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3994 if (headerlen < 0x7) {
3995 NV_ERROR(dev, "LVDS table header not understood\n");
3996 return -EINVAL;
3997 }
3998 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3999 break;
4000 default:
4001 NV_ERROR(dev,
4002 "LVDS table revision %d.%d not currently supported\n",
4003 lvds_ver >> 4, lvds_ver & 0xf);
4004 return -ENOSYS;
4005 }
4006
4007 lth->lvds_ver = lvds_ver;
4008 lth->headerlen = headerlen;
4009 lth->recordlen = recordlen;
4010
4011 return 0;
4012}
4013
4014static int
4015get_fp_strap(struct drm_device *dev, struct nvbios *bios)
4016{
4017 struct drm_nouveau_private *dev_priv = dev->dev_private;
4018
4019 /*
4020 * The fp strap is normally dictated by the "User Strap" in
4021 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
4022 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
4023 * by the PCI subsystem ID during POST, but not before the previous user
4024 * strap has been committed to CR58 for CR57=0xf on head A, which may be
4025 * read and used instead
4026 */
4027
4028 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
4029 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
4030
4031 if (dev_priv->card_type >= NV_50)
4032 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
4033 else
4034 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4035}
4036
4037static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4038{
4039 uint8_t *fptable;
4040 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4041 int ret, ofs, fpstrapping;
4042 struct lvdstableheader lth;
4043
4044 if (bios->fp.fptablepointer == 0x0) {
4045 /* Apple cards don't have the fp table; the laptops use DDC */
4046 /* The table is also missing on some x86 IGPs */
4047#ifndef __powerpc__
4048 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4049#endif
04a39c57 4050 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 4051 return 0;
4052 }
4053
4054 fptable = &bios->data[bios->fp.fptablepointer];
4055 fptable_ver = fptable[0];
4056
4057 switch (fptable_ver) {
4058 /*
4059 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4060 * version field, and miss one of the spread spectrum/PWM bytes.
4061 * This could affect early GF2Go parts (not seen any appropriate ROMs
4062 * though). Here we assume that a version of 0x05 matches this case
4063 * (combining with a BMP version check would be better), as the
4064 * common case for the panel type field is 0x0005, and that is in
4065 * fact what we are reading the first byte of.
4066 */
4067 case 0x05: /* some NV10, 11, 15, 16 */
4068 recordlen = 42;
4069 ofs = -1;
4070 break;
4071 case 0x10: /* some NV15/16, and NV11+ */
4072 recordlen = 44;
4073 ofs = 0;
4074 break;
4075 case 0x20: /* NV40+ */
4076 headerlen = fptable[1];
4077 recordlen = fptable[2];
4078 fpentries = fptable[3];
4079 /*
4080 * fptable[4] is the minimum
4081 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4082 */
04a39c57 4083 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 4084 ofs = -7;
4085 break;
4086 default:
4087 NV_ERROR(dev,
4088 "FP table revision %d.%d not currently supported\n",
4089 fptable_ver >> 4, fptable_ver & 0xf);
4090 return -ENOSYS;
4091 }
4092
4093 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4094 return 0;
4095
4096 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4097 if (ret)
4098 return ret;
4099
4100 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4101 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4102 lth.headerlen + 1;
4103 bios->fp.xlatwidth = lth.recordlen;
4104 }
4105 if (bios->fp.fpxlatetableptr == 0x0) {
4106 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4107 return -EINVAL;
4108 }
4109
4110 fpstrapping = get_fp_strap(dev, bios);
4111
4112 fpindex = bios->data[bios->fp.fpxlatetableptr +
4113 fpstrapping * bios->fp.xlatwidth];
4114
4115 if (fpindex > fpentries) {
4116 NV_ERROR(dev, "Bad flat panel table index\n");
4117 return -ENOENT;
4118 }
4119
4120 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4121 if (lth.lvds_ver > 0x10)
04a39c57 4122 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 4123
4124 /*
4125 * If either the strap or xlated fpindex value are 0xf there is no
4126 * panel using a strap-derived bios mode present. this condition
4127 * includes, but is different from, the DDC panel indicator above
4128 */
4129 if (fpstrapping == 0xf || fpindex == 0xf)
4130 return 0;
4131
4132 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4133 recordlen * fpindex + ofs;
4134
4135 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4136 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4137 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4138 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4139
4140 return 0;
4141}
4142
4143bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4144{
4145 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4146 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4147 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4148
4149 if (!mode) /* just checking whether we can produce a mode */
4150 return bios->fp.mode_ptr;
4151
4152 memset(mode, 0, sizeof(struct drm_display_mode));
4153 /*
4154 * For version 1.0 (version in byte 0):
4155 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4156 * single/dual link, and type (TFT etc.)
4157 * bytes 3-6 are bits per colour in RGBX
4158 */
4159 mode->clock = ROM16(mode_entry[7]) * 10;
4160 /* bytes 9-10 is HActive */
4161 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4162 /*
4163 * bytes 13-14 is HValid Start
4164 * bytes 15-16 is HValid End
4165 */
4166 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4167 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4168 mode->htotal = ROM16(mode_entry[21]) + 1;
4169 /* bytes 23-24, 27-30 similarly, but vertical */
4170 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4171 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4172 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4173 mode->vtotal = ROM16(mode_entry[35]) + 1;
4174 mode->flags |= (mode_entry[37] & 0x10) ?
4175 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4176 mode->flags |= (mode_entry[37] & 0x1) ?
4177 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4178 /*
4179 * bytes 38-39 relate to spread spectrum settings
4180 * bytes 40-43 are something to do with PWM
4181 */
4182
4183 mode->status = MODE_OK;
4184 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4185 drm_mode_set_name(mode);
4186 return bios->fp.mode_ptr;
4187}
4188
4189int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4190{
4191 /*
4192 * The LVDS table header is (mostly) described in
4193 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4194 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4195 * straps are not being used for the panel, this specifies the frequency
4196 * at which modes should be set up in the dual link style.
4197 *
4198 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 4199 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 4200 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4201 * numbers for use by INIT_SUB which controlled panel init and power,
4202 * and finally a dword of ms to sleep between power off and on
4203 * operations.
4204 *
4205 * In the BIT versions, the table following the header serves as an
4206 * integrated config and xlat table: the records in the table are
4207 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4208 * two bytes - the first as a config byte, the second for indexing the
4209 * fp mode table pointed to by the BIT 'D' table
4210 *
4211 * DDC is not used until after card init, so selecting the correct table
4212 * entry and setting the dual link flag for EDID equipped panels,
4213 * requiring tests against the native-mode pixel clock, cannot be done
4214 * until later, when this function should be called with non-zero pxclk
4215 */
4216 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4217 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4218 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4219 struct lvdstableheader lth;
4220 uint16_t lvdsofs;
04a39c57 4221 int ret, chip_version = bios->chip_version;
6ee73861
BS		 4222
4223 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4224 if (ret)
4225 return ret;
4226
4227 switch (lth.lvds_ver) {
4228 case 0x0a: /* pre NV40 */
4229 lvdsmanufacturerindex = bios->data[
4230 bios->fp.fpxlatemanufacturertableptr +
4231 fpstrapping];
4232
4233 /* we're done if this isn't the EDID panel case */
4234 if (!pxclk)
4235 break;
4236
4237 if (chip_version < 0x25) {
4238 /* nv17 behaviour
4239 *
4240 * It seems the old style lvds script pointer is reused
4241 * to select 18/24 bit colour depth for EDID panels.
4242 */
4243 lvdsmanufacturerindex =
4244 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4245 2 : 0;
4246 if (pxclk >= bios->fp.duallink_transition_clk)
4247 lvdsmanufacturerindex++;
4248 } else if (chip_version < 0x30) {
4249 /* nv28 behaviour (off-chip encoder)
4250 *
4251 * nv28 does a complex dance of first using byte 121 of
4252 * the EDID to choose the lvdsmanufacturerindex, then
4253 * later attempting to match the EDID manufacturer and
4254 * product IDs in a table (signature 'pidt' (panel id
4255 * table?)), setting an lvdsmanufacturerindex of 0 and
4256 * an fp strap of the match index (or 0xf if none)
4257 */
4258 lvdsmanufacturerindex = 0;
4259 } else {
4260 /* nv31, nv34 behaviour */
4261 lvdsmanufacturerindex = 0;
4262 if (pxclk >= bios->fp.duallink_transition_clk)
4263 lvdsmanufacturerindex = 2;
4264 if (pxclk >= 140000)
4265 lvdsmanufacturerindex = 3;
4266 }
4267
4268 /*
4269 * nvidia set the high nibble of (cr57=f, cr58) to
4270 * lvdsmanufacturerindex in this case; we don't
4271 */
4272 break;
4273 case 0x30: /* NV4x */
4274 case 0x40: /* G80/G90 */
4275 lvdsmanufacturerindex = fpstrapping;
4276 break;
4277 default:
4278 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4279 return -ENOSYS;
4280 }
4281
4282 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4283 switch (lth.lvds_ver) {
4284 case 0x0a:
4285 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4286 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4287 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4288 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4289 *if_is_24bit = bios->data[lvdsofs] & 16;
4290 break;
4291 case 0x30:
f3bbb9cc 4292 case 0x40:
6ee73861
BS		 4293 /*
4294 * No sign of the "power off for reset" or "reset for panel
4295 * on" bits, but it's safer to assume we should
4296 */
4297 bios->fp.power_off_for_reset = true;
4298 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 4299
6ee73861
BS		 4300 /*
4301 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 4302 * over-written, and if_is_24bit isn't used
6ee73861
BS		 4303 */
4304 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 4305 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4306 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4307 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4308 break;
4309 }
4310
2eb92c80
BS		 4311 /* Dell Latitude D620 reports a too-high value for the dual-link
4312 * transition freq, causing us to program the panel incorrectly.
4313 *
4314 * It doesn't appear the VBIOS actually uses its transition freq
4315 * (90000kHz), instead it uses the "Number of LVDS channels" field
4316 * out of the panel ID structure (http://www.spwg.org/).
4317 *
4318 * For the moment, a quirk will do :)
4319 */
acae116c 4320 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
2eb92c80 4321 bios->fp.duallink_transition_clk = 80000;
2eb92c80 4322
6ee73861
BS		 4323 /* set dual_link flag for EDID case */
4324 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4325 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4326
4327 *dl = bios->fp.dual_link;
4328
4329 return 0;
4330}
4331
721b0821
BS		 4332/* BIT 'U'/'d' table encoder subtables have hashes matching them to
4333 * a particular set of encoders.
4334 *
4335 * This function returns true if a particular DCB entry matches.
4336 */
4337bool
4338bios_encoder_match(struct dcb_entry *dcb, u32 hash)
6ee73861 4339{
721b0821
BS		 4340 if ((hash & 0x000000f0) != (dcb->location << 4))
4341 return false;
4342 if ((hash & 0x0000000f) != dcb->type)
4343 return false;
4344 if (!(hash & (dcb->or << 16)))
4345 return false;
4346
4347 switch (dcb->type) {
1eb38100
BS		 4348 case OUTPUT_TMDS:
4349 case OUTPUT_LVDS:
4350 case OUTPUT_DP:
721b0821
BS		 4351 if (hash & 0x00c00000) {
4352 if (!(hash & (dcb->sorconf.link << 22)))
4353 return false;
1eb38100 4354 }
721b0821
BS		 4355 default:
4356 return true;
6ee73861 4357 }
6ee73861
BS		 4358}
4359
6ee73861 4360int
02e4f587
BS		 4361nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4362 struct dcb_entry *dcbent, int crtc)
6ee73861
BS		 4363{
4364 /*
4365 * The display script table is located by the BIT 'U' table.
4366 *
4367 * It contains an array of pointers to various tables describing
4368 * a particular output type. The first 32-bits of the output
4369 * tables contains similar information to a DCB entry, and is
4370 * used to decide whether that particular table is suitable for
4371 * the output you want to access.
4372 *
4373 * The "record header length" field here seems to indicate the
4374 * offset of the first configuration entry in the output tables.
4375 * This is 10 on most cards I've seen, but 12 has been witnessed
4376 * on DP cards, and there's another script pointer within the
4377 * header.
4378 *
4379 * offset + 0 ( 8 bits): version
4380 * offset + 1 ( 8 bits): header length
4381 * offset + 2 ( 8 bits): record length
4382 * offset + 3 ( 8 bits): number of records
4383 * offset + 4 ( 8 bits): record header length
4384 * offset + 5 (16 bits): pointer to first output script table
4385 */
4386
4387 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4388 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4389 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4390 uint8_t *otable = NULL;
4391 uint16_t script;
721b0821 4392 int i;
6ee73861
BS		 4393
4394 if (!bios->display.script_table_ptr) {
4395 NV_ERROR(dev, "No pointer to output script table\n");
4396 return 1;
4397 }
4398
4399 /*
4400 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4401 * so until they are, we really don't need to care.
4402 */
4403 if (table[0] < 0x20)
4404 return 1;
4405
4406 if (table[0] != 0x20 && table[0] != 0x21) {
4407 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4408 table[0]);
4409 return 1;
4410 }
4411
4412 /*
4413 * The output script tables describing a particular output type
4414 * look as follows:
4415 *
4416 * offset + 0 (32 bits): output this table matches (hash of DCB)
4417 * offset + 4 ( 8 bits): unknown
4418 * offset + 5 ( 8 bits): number of configurations
4419 * offset + 6 (16 bits): pointer to some script
4420 * offset + 8 (16 bits): pointer to some script
4421 *
4422 * headerlen == 10
4423 * offset + 10 : configuration 0
4424 *
4425 * headerlen == 12
4426 * offset + 10 : pointer to some script
4427 * offset + 12 : configuration 0
4428 *
4429 * Each config entry is as follows:
4430 *
4431 * offset + 0 (16 bits): unknown, assumed to be a match value
4432 * offset + 2 (16 bits): pointer to script table (clock set?)
4433 * offset + 4 (16 bits): pointer to script table (reset?)
4434 *
4435 * There doesn't appear to be a count value to say how many
4436 * entries exist in each script table, instead, a 0 value in
4437 * the first 16-bit word seems to indicate both the end of the
4438 * list and the default entry. The second 16-bit word in the
4439 * script tables is a pointer to the script to execute.
4440 */
4441
ef2bb506 4442 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861 4443 dcbent->type, dcbent->location, dcbent->or);
721b0821 4444 for (i = 0; i < table[3]; i++) {
f9f9f536 4445 otable = ROMPTR(dev, table[table[1] + (i * table[2])]);
721b0821
BS		 4446 if (otable && bios_encoder_match(dcbent, ROM32(otable[0])))
4447 break;
4448 }
4449
6ee73861 4450 if (!otable) {
54bf67de 4451 NV_DEBUG_KMS(dev, "failed to match any output table\n");
6ee73861
BS		 4452 return 1;
4453 }
4454
02e4f587 4455 if (pclk < -2 || pclk > 0) {
6ee73861
BS		 4456 /* Try to find matching script table entry */
4457 for (i = 0; i < otable[5]; i++) {
02e4f587 4458 if (ROM16(otable[table[4] + i*6]) == type)
6ee73861
BS		 4459 break;
4460 }
4461
4462 if (i == otable[5]) {
4463 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4464 "using first\n",
02e4f587 4465 type, dcbent->type, dcbent->or);
6ee73861
BS		 4466 i = 0;
4467 }
4468 }
4469
02e4f587 4470 if (pclk == 0) {
6ee73861
BS		 4471 script = ROM16(otable[6]);
4472 if (!script) {
ef2bb506 4473 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4474 return 1;
4475 }
4476
45a68a07 4477 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
02e4f587 4478 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4479 } else
02e4f587 4480 if (pclk == -1) {
6ee73861
BS		 4481 script = ROM16(otable[8]);
4482 if (!script) {
ef2bb506 4483 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4484 return 1;
4485 }
4486
45a68a07 4487 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
02e4f587 4488 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4489 } else
02e4f587 4490 if (pclk == -2) {
6ee73861
BS		 4491 if (table[4] >= 12)
4492 script = ROM16(otable[10]);
4493 else
4494 script = 0;
4495 if (!script) {
ef2bb506 4496 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4497 return 1;
4498 }
4499
45a68a07 4500 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
02e4f587 4501 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4502 } else
02e4f587 4503 if (pclk > 0) {
6ee73861
BS		 4504 script = ROM16(otable[table[4] + i*6 + 2]);
4505 if (script)
02e4f587 4506 script = clkcmptable(bios, script, pclk);
6ee73861 4507 if (!script) {
54bf67de 4508 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
6ee73861
BS		 4509 return 1;
4510 }
4511
45a68a07 4512 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
02e4f587 4513 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4514 } else
02e4f587 4515 if (pclk < 0) {
6ee73861
BS		 4516 script = ROM16(otable[table[4] + i*6 + 4]);
4517 if (script)
02e4f587 4518 script = clkcmptable(bios, script, -pclk);
6ee73861 4519 if (!script) {
ef2bb506 4520 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4521 return 1;
4522 }
4523
45a68a07 4524 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
02e4f587 4525 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861
BS		 4526 }
4527
4528 return 0;
4529}
4530
4531
4532int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4533{
4534 /*
4535 * the pxclk parameter is in kHz
4536 *
4537 * This runs the TMDS regs setting code found on BIT bios cards
4538 *
4539 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4540 * ffs(or) == 3, use the second.
4541 */
4542
4543 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4544 struct nvbios *bios = &dev_priv->vbios;
4545 int cv = bios->chip_version;
6ee73861
BS		 4546 uint16_t clktable = 0, scriptptr;
4547 uint32_t sel_clk_binding, sel_clk;
4548
4549 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4550 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4551 dcbent->location != DCB_LOC_ON_CHIP)
4552 return 0;
4553
4554 switch (ffs(dcbent->or)) {
4555 case 1:
4556 clktable = bios->tmds.output0_script_ptr;
4557 break;
4558 case 2:
4559 case 3:
4560 clktable = bios->tmds.output1_script_ptr;
4561 break;
4562 }
4563
4564 if (!clktable) {
4565 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4566 return -EINVAL;
4567 }
4568
4569 scriptptr = clkcmptable(bios, clktable, pxclk);
4570
4571 if (!scriptptr) {
4572 NV_ERROR(dev, "TMDS output init script not found\n");
4573 return -ENOENT;
4574 }
4575
4576 /* don't let script change pll->head binding */
4577 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4578 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4579 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4580 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4581
4582 return 0;
4583}
4584
855a95e4
BS		 4585struct pll_mapping {
4586 u8 type;
4587 u32 reg;
4588};
4589
4590static struct pll_mapping nv04_pll_mapping[] = {
4591 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4592 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4593 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4594 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4595 {}
4596};
4597
4598static struct pll_mapping nv40_pll_mapping[] = {
4599 { PLL_CORE , 0x004000 },
4600 { PLL_MEMORY, 0x004020 },
4601 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4602 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4603 {}
4604};
4605
4606static struct pll_mapping nv50_pll_mapping[] = {
4607 { PLL_CORE , 0x004028 },
4608 { PLL_SHADER, 0x004020 },
4609 { PLL_UNK03 , 0x004000 },
4610 { PLL_MEMORY, 0x004008 },
4611 { PLL_UNK40 , 0x00e810 },
4612 { PLL_UNK41 , 0x00e818 },
4613 { PLL_UNK42 , 0x00e824 },
4614 { PLL_VPLL0 , 0x614100 },
4615 { PLL_VPLL1 , 0x614900 },
4616 {}
4617};
4618
4619static struct pll_mapping nv84_pll_mapping[] = {
4620 { PLL_CORE , 0x004028 },
4621 { PLL_SHADER, 0x004020 },
4622 { PLL_MEMORY, 0x004008 },
d4cca9e1 4623 { PLL_VDEC , 0x004030 },
855a95e4
BS		 4624 { PLL_UNK41 , 0x00e818 },
4625 { PLL_VPLL0 , 0x614100 },
4626 { PLL_VPLL1 , 0x614900 },
4627 {}
4628};
4629
4630u32
4631get_pll_register(struct drm_device *dev, enum pll_types type)
4632{
4633 struct drm_nouveau_private *dev_priv = dev->dev_private;
4634 struct nvbios *bios = &dev_priv->vbios;
4635 struct pll_mapping *map;
4636 int i;
4637
4638 if (dev_priv->card_type < NV_40)
4639 map = nv04_pll_mapping;
4640 else
4641 if (dev_priv->card_type < NV_50)
4642 map = nv40_pll_mapping;
4643 else {
4644 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4645
56edd964 4646 if (plim[0] >= 0x30) {
855a95e4
BS		 4647 u8 *entry = plim + plim[1];
4648 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4649 if (entry[0] == type)
4650 return ROM32(entry[3]);
4651 }
4652
4653 return 0;
4654 }
4655
4656 if (dev_priv->chipset == 0x50)
4657 map = nv50_pll_mapping;
4658 else
4659 map = nv84_pll_mapping;
4660 }
4661
4662 while (map->reg) {
4663 if (map->type == type)
4664 return map->reg;
4665 map++;
4666 }
4667
4668 return 0;
4669}
4670
6ee73861
BS		 4671int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4672{
4673 /*
4674 * PLL limits table
4675 *
4676 * Version 0x10: NV30, NV31
4677 * One byte header (version), one record of 24 bytes
4678 * Version 0x11: NV36 - Not implemented
4679 * Seems to have same record style as 0x10, but 3 records rather than 1
4680 * Version 0x20: Found on Geforce 6 cards
4681 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4682 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4683 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4684 * length in general, some (integrated) have an extra configuration byte
4685 * Version 0x30: Found on Geforce 8, separates the register mapping
4686 * from the limits tables.
4687 */
4688
4689 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4690 struct nvbios *bios = &dev_priv->vbios;
4691 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4692 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4693 uint32_t crystal_strap_mask, crystal_straps;
4694
4695 if (!bios->pll_limit_tbl_ptr) {
4696 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4697 cv >= 0x40) {
4698 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4699 return -EINVAL;
4700 }
4701 } else
4702 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4703
4704 crystal_strap_mask = 1 << 6;
4705 /* open coded dev->twoHeads test */
4706 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4707 crystal_strap_mask |= 1 << 22;
4708 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4709 crystal_strap_mask;
4710
4711 switch (pll_lim_ver) {
4712 /*
4713 * We use version 0 to indicate a pre limit table bios (single stage
4714 * pll) and load the hard coded limits instead.
4715 */
4716 case 0:
4717 break;
4718 case 0x10:
4719 case 0x11:
4720 /*
4721 * Strictly v0x11 has 3 entries, but the last two don't seem
4722 * to get used.
4723 */
4724 headerlen = 1;
4725 recordlen = 0x18;
4726 entries = 1;
4727 pllindex = 0;
4728 break;
4729 case 0x20:
4730 case 0x21:
4731 case 0x30:
4732 case 0x40:
4733 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4734 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4735 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4736 break;
4737 default:
4738 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4739 "supported\n", pll_lim_ver);
4740 return -ENOSYS;
4741 }
4742
4743 /* initialize all members to zero */
4744 memset(pll_lim, 0, sizeof(struct pll_lims));
4745
855a95e4
BS		 4746 /* if we were passed a type rather than a register, figure
4747 * out the register and store it
4748 */
4749 if (limit_match > PLL_MAX)
4750 pll_lim->reg = limit_match;
6f876986 4751 else {
855a95e4 4752 pll_lim->reg = get_pll_register(dev, limit_match);
6f876986
BS		 4753 if (!pll_lim->reg)
4754 return -ENOENT;
4755 }
855a95e4 4756
6ee73861
BS		 4757 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4758 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4759
4760 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4761 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4762 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4763 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4764 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4765 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4766 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4767
4768 /* these values taken from nv30/31/36 */
4769 pll_lim->vco1.min_n = 0x1;
4770 if (cv == 0x36)
4771 pll_lim->vco1.min_n = 0x5;
4772 pll_lim->vco1.max_n = 0xff;
4773 pll_lim->vco1.min_m = 0x1;
4774 pll_lim->vco1.max_m = 0xd;
4775 pll_lim->vco2.min_n = 0x4;
4776 /*
4777 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4778 * table version (apart from nv35)), N2 is compared to
4779 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4780 * save a comparison
4781 */
4782 pll_lim->vco2.max_n = 0x28;
4783 if (cv == 0x30 || cv == 0x35)
4784 /* only 5 bits available for N2 on nv30/35 */
4785 pll_lim->vco2.max_n = 0x1f;
4786 pll_lim->vco2.min_m = 0x1;
4787 pll_lim->vco2.max_m = 0x4;
4788 pll_lim->max_log2p = 0x7;
4789 pll_lim->max_usable_log2p = 0x6;
4790 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4791 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
6ee73861
BS		 4792 uint8_t *pll_rec;
4793 int i;
4794
4795 /*
4796 * First entry is default match, if nothing better. warn if
4797 * reg field nonzero
4798 */
4799 if (ROM32(bios->data[plloffs]))
4800 NV_WARN(dev, "Default PLL limit entry has non-zero "
4801 "register field\n");
4802
6ee73861 4803 for (i = 1; i < entries; i++)
855a95e4 4804 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
6ee73861
BS		 4805 pllindex = i;
4806 break;
4807 }
4808
eadc69cc
EV		 4809 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4810 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4811 "limits table", pll_lim->reg);
4812 return -ENOENT;
4813 }
4814
6ee73861
BS		 4815 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4816
4817 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
855a95e4 4818 pllindex ? pll_lim->reg : 0);
6ee73861
BS		 4819
4820 /*
4821 * Frequencies are stored in tables in MHz, kHz are more
4822 * useful, so we convert.
4823 */
4824
4825 /* What output frequencies can each VCO generate? */
4826 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4827 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4828 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4829 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4830
4831 /* What input frequencies they accept (past the m-divider)? */
4832 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4833 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4834 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4835 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4836
4837 /* What values are accepted as multiplier and divider? */
4838 pll_lim->vco1.min_n = pll_rec[20];
4839 pll_lim->vco1.max_n = pll_rec[21];
4840 pll_lim->vco1.min_m = pll_rec[22];
4841 pll_lim->vco1.max_m = pll_rec[23];
4842 pll_lim->vco2.min_n = pll_rec[24];
4843 pll_lim->vco2.max_n = pll_rec[25];
4844 pll_lim->vco2.min_m = pll_rec[26];
4845 pll_lim->vco2.max_m = pll_rec[27];
4846
4847 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4848 if (pll_lim->max_log2p > 0x7)
4849 /* pll decoding in nv_hw.c assumes never > 7 */
4850 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4851 pll_lim->max_log2p);
4852 if (cv < 0x60)
4853 pll_lim->max_usable_log2p = 0x6;
4854 pll_lim->log2p_bias = pll_rec[30];
4855
4856 if (recordlen > 0x22)
4857 pll_lim->refclk = ROM32(pll_rec[31]);
4858
4859 if (recordlen > 0x23 && pll_rec[35])
4860 NV_WARN(dev,
4861 "Bits set in PLL configuration byte (%x)\n",
4862 pll_rec[35]);
4863
4864 /* C51 special not seen elsewhere */
4865 if (cv == 0x51 && !pll_lim->refclk) {
4866 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4867
855a95e4
BS		 4868 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4869 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
6ee73861
BS		 4870 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4871 pll_lim->refclk = 200000;
4872 else
4873 pll_lim->refclk = 25000;
4874 }
4875 }
4876 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4877 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4878 uint8_t *record = NULL;
4879 int i;
4880
4881 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
855a95e4 4882 pll_lim->reg);
6ee73861
BS		 4883
4884 for (i = 0; i < entries; i++, entry += recordlen) {
855a95e4 4885 if (ROM32(entry[3]) == pll_lim->reg) {
6ee73861
BS		 4886 record = &bios->data[ROM16(entry[1])];
4887 break;
4888 }
4889 }
4890
4891 if (!record) {
4892 NV_ERROR(dev, "Register 0x%08x not found in PLL "
855a95e4 4893 "limits table", pll_lim->reg);
6ee73861
BS		 4894 return -ENOENT;
4895 }
4896
4897 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4898 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4899 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4900 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4901 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4902 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4903 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4904 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4905 pll_lim->vco1.min_n = record[16];
4906 pll_lim->vco1.max_n = record[17];
4907 pll_lim->vco1.min_m = record[18];
4908 pll_lim->vco1.max_m = record[19];
4909 pll_lim->vco2.min_n = record[20];
4910 pll_lim->vco2.max_n = record[21];
4911 pll_lim->vco2.min_m = record[22];
4912 pll_lim->vco2.max_m = record[23];
4913 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4914 pll_lim->log2p_bias = record[27];
4915 pll_lim->refclk = ROM32(record[28]);
4916 } else if (pll_lim_ver) { /* ver 0x40 */
4917 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4918 uint8_t *record = NULL;
4919 int i;
4920
4921 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
855a95e4 4922 pll_lim->reg);
6ee73861
BS		 4923
4924 for (i = 0; i < entries; i++, entry += recordlen) {
855a95e4 4925 if (ROM32(entry[3]) == pll_lim->reg) {
6ee73861
BS		 4926 record = &bios->data[ROM16(entry[1])];
4927 break;
4928 }
4929 }
4930
4931 if (!record) {
4932 NV_ERROR(dev, "Register 0x%08x not found in PLL "
855a95e4 4933 "limits table", pll_lim->reg);
6ee73861
BS		 4934 return -ENOENT;
4935 }
4936
4937 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4938 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4939 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4940 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4941 pll_lim->vco1.min_m = record[8];
4942 pll_lim->vco1.max_m = record[9];
4943 pll_lim->vco1.min_n = record[10];
4944 pll_lim->vco1.max_n = record[11];
4945 pll_lim->min_p = record[12];
4946 pll_lim->max_p = record[13];
ce521846 4947 pll_lim->refclk = ROM16(entry[9]) * 1000;
6ee73861
BS		 4948 }
4949
4950 /*
4951 * By now any valid limit table ought to have set a max frequency for
4952 * vco1, so if it's zero it's either a pre limit table bios, or one
4953 * with an empty limit table (seen on nv18)
4954 */
4955 if (!pll_lim->vco1.maxfreq) {
4956 pll_lim->vco1.minfreq = bios->fminvco;
4957 pll_lim->vco1.maxfreq = bios->fmaxvco;
4958 pll_lim->vco1.min_inputfreq = 0;
4959 pll_lim->vco1.max_inputfreq = INT_MAX;
4960 pll_lim->vco1.min_n = 0x1;
4961 pll_lim->vco1.max_n = 0xff;
4962 pll_lim->vco1.min_m = 0x1;
4963 if (crystal_straps == 0) {
4964 /* nv05 does this, nv11 doesn't, nv10 unknown */
4965 if (cv < 0x11)
4966 pll_lim->vco1.min_m = 0x7;
4967 pll_lim->vco1.max_m = 0xd;
4968 } else {
4969 if (cv < 0x11)
4970 pll_lim->vco1.min_m = 0x8;
4971 pll_lim->vco1.max_m = 0xe;
4972 }
4973 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4974 pll_lim->max_log2p = 4;
4975 else
4976 pll_lim->max_log2p = 5;
4977 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4978 }
4979
4980 if (!pll_lim->refclk)
4981 switch (crystal_straps) {
4982 case 0:
4983 pll_lim->refclk = 13500;
4984 break;
4985 case (1 << 6):
4986 pll_lim->refclk = 14318;
4987 break;
4988 case (1 << 22):
4989 pll_lim->refclk = 27000;
4990 break;
4991 case (1 << 22 | 1 << 6):
4992 pll_lim->refclk = 25000;
4993 break;
4994 }
4995
4c389f00
BS		 4996 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4997 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4998 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4999 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
5000 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
5001 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
5002 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
5003 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
5004 if (pll_lim->vco2.maxfreq) {
5005 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
5006 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
5007 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
5008 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
5009 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
5010 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
5011 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
5012 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
5013 }
5014 if (!pll_lim->max_p) {
5015 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
5016 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
5017 } else {
5018 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
5019 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
5020 }
5021 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 5022
5023 return 0;
5024}
5025
5026static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
5027{
5028 /*
5029 * offset + 0 (8 bits): Micro version
5030 * offset + 1 (8 bits): Minor version
5031 * offset + 2 (8 bits): Chip version
5032 * offset + 3 (8 bits): Major version
5033 */
5034
5035 bios->major_version = bios->data[offset + 3];
04a39c57 5036 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 5037 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
5038 bios->data[offset + 3], bios->data[offset + 2],
5039 bios->data[offset + 1], bios->data[offset]);
5040}
5041
5042static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
5043{
5044 /*
5045 * Parses the init table segment for pointers used in script execution.
5046 *
5047 * offset + 0 (16 bits): init script tables pointer
5048 * offset + 2 (16 bits): macro index table pointer
5049 * offset + 4 (16 bits): macro table pointer
5050 * offset + 6 (16 bits): condition table pointer
5051 * offset + 8 (16 bits): io condition table pointer
5052 * offset + 10 (16 bits): io flag condition table pointer
5053 * offset + 12 (16 bits): init function table pointer
5054 */
5055
5056 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5057 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5058 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5059 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5060 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5061 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5062 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5063}
5064
5065static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5066{
5067 /*
5068 * Parses the load detect values for g80 cards.
5069 *
5070 * offset + 0 (16 bits): loadval table pointer
5071 */
5072
5073 uint16_t load_table_ptr;
5074 uint8_t version, headerlen, entrylen, num_entries;
5075
5076 if (bitentry->length != 3) {
5077 NV_ERROR(dev, "Do not understand BIT A table\n");
5078 return -EINVAL;
5079 }
5080
5081 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5082
5083 if (load_table_ptr == 0x0) {
1562ffde 5084 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
6ee73861
BS		 5085 return -EINVAL;
5086 }
5087
5088 version = bios->data[load_table_ptr];
5089
5090 if (version != 0x10) {
5091 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5092 version >> 4, version & 0xF);
5093 return -ENOSYS;
5094 }
5095
5096 headerlen = bios->data[load_table_ptr + 1];
5097 entrylen = bios->data[load_table_ptr + 2];
5098 num_entries = bios->data[load_table_ptr + 3];
5099
5100 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5101 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5102 return -EINVAL;
5103 }
5104
5105 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 5106 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 5107
5108 return 0;
5109}
5110
5111static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5112{
5113 /*
5114 * offset + 8 (16 bits): PLL limits table pointer
5115 *
5116 * There's more in here, but that's unknown.
5117 */
5118
5119 if (bitentry->length < 10) {
5120 NV_ERROR(dev, "Do not understand BIT C table\n");
5121 return -EINVAL;
5122 }
5123
5124 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5125
5126 return 0;
5127}
5128
5129static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5130{
5131 /*
5132 * Parses the flat panel table segment that the bit entry points to.
5133 * Starting at bitentry->offset:
5134 *
5135 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5136 * records beginning with a freq.
5137 * offset + 2 (16 bits): mode table pointer
5138 */
5139
5140 if (bitentry->length != 4) {
5141 NV_ERROR(dev, "Do not understand BIT display table\n");
5142 return -EINVAL;
5143 }
5144
5145 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5146
5147 return 0;
5148}
5149
5150static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5151{
5152 /*
5153 * Parses the init table segment that the bit entry points to.
5154 *
5155 * See parse_script_table_pointers for layout
5156 */
5157
5158 if (bitentry->length < 14) {
5159 NV_ERROR(dev, "Do not understand init table\n");
5160 return -EINVAL;
5161 }
5162
5163 parse_script_table_pointers(bios, bitentry->offset);
5164
5165 if (bitentry->length >= 16)
5166 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5167 if (bitentry->length >= 18)
5168 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5169
5170 return 0;
5171}
5172
5173static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5174{
5175 /*
5176 * BIT 'i' (info?) table
5177 *
5178 * offset + 0 (32 bits): BIOS version dword (as in B table)
5179 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5180 * offset + 13 (16 bits): pointer to table containing DAC load
5181 * detection comparison values
5182 *
5183 * There's other things in the table, purpose unknown
5184 */
5185
5186 uint16_t daccmpoffset;
5187 uint8_t dacver, dacheaderlen;
5188
5189 if (bitentry->length < 6) {
5190 NV_ERROR(dev, "BIT i table too short for needed information\n");
5191 return -EINVAL;
5192 }
5193
5194 parse_bios_version(dev, bios, bitentry->offset);
5195
5196 /*
5197 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5198 * Quadro identity crisis), other bits possibly as for BMP feature byte
5199 */
5200 bios->feature_byte = bios->data[bitentry->offset + 5];
5201 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5202
5203 if (bitentry->length < 15) {
5204 NV_WARN(dev, "BIT i table not long enough for DAC load "
5205 "detection comparison table\n");
5206 return -EINVAL;
5207 }
5208
5209 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5210
5211 /* doesn't exist on g80 */
5212 if (!daccmpoffset)
5213 return 0;
5214
5215 /*
5216 * The first value in the table, following the header, is the
5217 * comparison value, the second entry is a comparison value for
5218 * TV load detection.
5219 */
5220
5221 dacver = bios->data[daccmpoffset];
5222 dacheaderlen = bios->data[daccmpoffset + 1];
5223
5224 if (dacver != 0x00 && dacver != 0x10) {
5225 NV_WARN(dev, "DAC load detection comparison table version "
5226 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5227 return -ENOSYS;
5228 }
5229
04a39c57
BS		 5230 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5231 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 5232
5233 return 0;
5234}
5235
5236static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5237{
5238 /*
5239 * Parses the LVDS table segment that the bit entry points to.
5240 * Starting at bitentry->offset:
5241 *
5242 * offset + 0 (16 bits): LVDS strap xlate table pointer
5243 */
5244
5245 if (bitentry->length != 2) {
5246 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5247 return -EINVAL;
5248 }
5249
5250 /*
5251 * No idea if it's still called the LVDS manufacturer table, but
5252 * the concept's close enough.
5253 */
5254 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5255
5256 return 0;
5257}
5258
5259static int
5260parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5261 struct bit_entry *bitentry)
5262{
5263 /*
5264 * offset + 2 (8 bits): number of options in an
5265 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5266 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5267 * restrict option selection
5268 *
5269 * There's a bunch of bits in this table other than the RAM restrict
5270 * stuff that we don't use - their use currently unknown
5271 */
5272
6ee73861
BS		 5273 /*
5274 * Older bios versions don't have a sufficiently long table for
5275 * what we want
5276 */
5277 if (bitentry->length < 0x5)
5278 return 0;
5279
4709bff0 5280 if (bitentry->version < 2) {
37383650
MK		 5281 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5282 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 5283 } else {
37383650
MK		 5284 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5285 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 5286 }
5287
6ee73861
BS		 5288 return 0;
5289}
5290
5291static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5292{
5293 /*
5294 * Parses the pointer to the TMDS table
5295 *
5296 * Starting at bitentry->offset:
5297 *
5298 * offset + 0 (16 bits): TMDS table pointer
5299 *
5300 * The TMDS table is typically found just before the DCB table, with a
5301 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5302 * length?)
5303 *
5304 * At offset +7 is a pointer to a script, which I don't know how to
5305 * run yet.
5306 * At offset +9 is a pointer to another script, likewise
5307 * Offset +11 has a pointer to a table where the first word is a pxclk
5308 * frequency and the second word a pointer to a script, which should be
5309 * run if the comparison pxclk frequency is less than the pxclk desired.
5310 * This repeats for decreasing comparison frequencies
5311 * Offset +13 has a pointer to a similar table
5312 * The selection of table (and possibly +7/+9 script) is dictated by
5313 * "or" from the DCB.
5314 */
5315
5316 uint16_t tmdstableptr, script1, script2;
5317
5318 if (bitentry->length != 2) {
5319 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5320 return -EINVAL;
5321 }
5322
5323 tmdstableptr = ROM16(bios->data[bitentry->offset]);
98720bf4 5324 if (!tmdstableptr) {
6ee73861
BS		 5325 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5326 return -EINVAL;
5327 }
5328
98720bf4
BS		 5329 NV_INFO(dev, "TMDS table version %d.%d\n",
5330 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5331
6ee73861 5332 /* nv50+ has v2.0, but we don't parse it atm */
98720bf4 5333 if (bios->data[tmdstableptr] != 0x11)
6ee73861 5334 return -ENOSYS;
6ee73861
BS		 5335
5336 /*
5337 * These two scripts are odd: they don't seem to get run even when
5338 * they are not stubbed.
5339 */
5340 script1 = ROM16(bios->data[tmdstableptr + 7]);
5341 script2 = ROM16(bios->data[tmdstableptr + 9]);
5342 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5343 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5344
5345 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5346 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5347
5348 return 0;
5349}
5350
5351static int
5352parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5353 struct bit_entry *bitentry)
5354{
5355 /*
5356 * Parses the pointer to the G80 output script tables
5357 *
5358 * Starting at bitentry->offset:
5359 *
5360 * offset + 0 (16 bits): output script table pointer
5361 */
5362
5363 uint16_t outputscripttableptr;
5364
5365 if (bitentry->length != 3) {
5366 NV_ERROR(dev, "Do not understand BIT U table\n");
5367 return -EINVAL;
5368 }
5369
5370 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5371 bios->display.script_table_ptr = outputscripttableptr;
5372 return 0;
5373}
5374
6ee73861
BS		 5375struct bit_table {
5376 const char id;
5377 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5378};
5379
5380#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5381
4709bff0
BS		 5382int
5383bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5384{
5385 struct drm_nouveau_private *dev_priv = dev->dev_private;
5386 struct nvbios *bios = &dev_priv->vbios;
5387 u8 entries, *entry;
5388
5389 entries = bios->data[bios->offset + 10];
5390 entry = &bios->data[bios->offset + 12];
5391 while (entries--) {
5392 if (entry[0] == id) {
5393 bit->id = entry[0];
5394 bit->version = entry[1];
5395 bit->length = ROM16(entry[2]);
5396 bit->offset = ROM16(entry[4]);
f9f9f536 5397 bit->data = ROMPTR(dev, entry[4]);
4709bff0
BS		 5398 return 0;
5399 }
5400
5401 entry += bios->data[bios->offset + 9];
5402 }
5403
5404 return -ENOENT;
5405}
5406
6ee73861
BS		 5407static int
5408parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5409 struct bit_table *table)
5410{
5411 struct drm_device *dev = bios->dev;
6ee73861
BS		 5412 struct bit_entry bitentry;
5413
4709bff0 5414 if (bit_table(dev, table->id, &bitentry) == 0)
6ee73861 5415 return table->parse_fn(dev, bios, &bitentry);
6ee73861
BS		 5416
5417 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5418 return -ENOSYS;
5419}
5420
5421static int
5422parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5423{
5424 int ret;
5425
5426 /*
5427 * The only restriction on parsing order currently is having 'i' first
5428 * for use of bios->*_version or bios->feature_byte while parsing;
5429 * functions shouldn't be actually *doing* anything apart from pulling
5430 * data from the image into the bios struct, thus no interdependencies
5431 */
5432 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5433 if (ret) /* info? */
5434 return ret;
5435 if (bios->major_version >= 0x60) /* g80+ */
5436 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5437 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5438 if (ret)
5439 return ret;
5440 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5441 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5442 if (ret)
5443 return ret;
5444 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5445 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5446 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5447 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
6ee73861
BS		 5448
5449 return 0;
5450}
5451
5452static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5453{
5454 /*
5455 * Parses the BMP structure for useful things, but does not act on them
5456 *
5457 * offset + 5: BMP major version
5458 * offset + 6: BMP minor version
5459 * offset + 9: BMP feature byte
5460 * offset + 10: BCD encoded BIOS version
5461 *
5462 * offset + 18: init script table pointer (for bios versions < 5.10h)
5463 * offset + 20: extra init script table pointer (for bios
5464 * versions < 5.10h)
5465 *
5466 * offset + 24: memory init table pointer (used on early bios versions)
5467 * offset + 26: SDR memory sequencing setup data table
5468 * offset + 28: DDR memory sequencing setup data table
5469 *
5470 * offset + 54: index of I2C CRTC pair to use for CRT output
5471 * offset + 55: index of I2C CRTC pair to use for TV output
5472 * offset + 56: index of I2C CRTC pair to use for flat panel output
5473 * offset + 58: write CRTC index for I2C pair 0
5474 * offset + 59: read CRTC index for I2C pair 0
5475 * offset + 60: write CRTC index for I2C pair 1
5476 * offset + 61: read CRTC index for I2C pair 1
5477 *
5478 * offset + 67: maximum internal PLL frequency (single stage PLL)
5479 * offset + 71: minimum internal PLL frequency (single stage PLL)
5480 *
5481 * offset + 75: script table pointers, as described in
5482 * parse_script_table_pointers
5483 *
5484 * offset + 89: TMDS single link output A table pointer
5485 * offset + 91: TMDS single link output B table pointer
5486 * offset + 95: LVDS single link output A table pointer
5487 * offset + 105: flat panel timings table pointer
5488 * offset + 107: flat panel strapping translation table pointer
5489 * offset + 117: LVDS manufacturer panel config table pointer
5490 * offset + 119: LVDS manufacturer strapping translation table pointer
5491 *
5492 * offset + 142: PLL limits table pointer
5493 *
5494 * offset + 156: minimum pixel clock for LVDS dual link
5495 */
5496
5497 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5498 uint16_t bmplength;
5499 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5500
5501 /* load needed defaults in case we can't parse this info */
04a39c57 5502 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 5503 bios->fmaxvco = 256000;
5504 bios->fminvco = 128000;
5505 bios->fp.duallink_transition_clk = 90000;
5506
5507 bmp_version_major = bmp[5];
5508 bmp_version_minor = bmp[6];
5509
5510 NV_TRACE(dev, "BMP version %d.%d\n",
5511 bmp_version_major, bmp_version_minor);
5512
5513 /*
5514 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5515 * pointer on early versions
5516 */
5517 if (bmp_version_major < 5)
5518 *(uint16_t *)&bios->data[0x36] = 0;
5519
5520 /*
5521 * Seems that the minor version was 1 for all major versions prior
5522 * to 5. Version 6 could theoretically exist, but I suspect BIT
5523 * happened instead.
5524 */
5525 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5526 NV_ERROR(dev, "You have an unsupported BMP version. "
5527 "Please send in your bios\n");
5528 return -ENOSYS;
5529 }
5530
5531 if (bmp_version_major == 0)
5532 /* nothing that's currently useful in this version */
5533 return 0;
5534 else if (bmp_version_major == 1)
5535 bmplength = 44; /* exact for 1.01 */
5536 else if (bmp_version_major == 2)
5537 bmplength = 48; /* exact for 2.01 */
5538 else if (bmp_version_major == 3)
5539 bmplength = 54;
5540 /* guessed - mem init tables added in this version */
5541 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5542 /* don't know if 5.0 exists... */
5543 bmplength = 62;
5544 /* guessed - BMP I2C indices added in version 4*/
5545 else if (bmp_version_minor < 0x6)
5546 bmplength = 67; /* exact for 5.01 */
5547 else if (bmp_version_minor < 0x10)
5548 bmplength = 75; /* exact for 5.06 */
5549 else if (bmp_version_minor == 0x10)
5550 bmplength = 89; /* exact for 5.10h */
5551 else if (bmp_version_minor < 0x14)
5552 bmplength = 118; /* exact for 5.11h */
5553 else if (bmp_version_minor < 0x24)
5554 /*
5555 * Not sure of version where pll limits came in;
5556 * certainly exist by 0x24 though.
5557 */
5558 /* length not exact: this is long enough to get lvds members */
5559 bmplength = 123;
5560 else if (bmp_version_minor < 0x27)
5561 /*
5562 * Length not exact: this is long enough to get pll limit
5563 * member
5564 */
5565 bmplength = 144;
5566 else
5567 /*
5568 * Length not exact: this is long enough to get dual link
5569 * transition clock.
5570 */
5571 bmplength = 158;
5572
5573 /* checksum */
5574 if (nv_cksum(bmp, 8)) {
5575 NV_ERROR(dev, "Bad BMP checksum\n");
5576 return -EINVAL;
5577 }
5578
5579 /*
5580 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5581 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5582 * (not nv10gl), bit 5 that the flat panel tables are present, and
5583 * bit 6 a tv bios.
5584 */
5585 bios->feature_byte = bmp[9];
5586
5587 parse_bios_version(dev, bios, offset + 10);
5588
5589 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5590 bios->old_style_init = true;
5591 legacy_scripts_offset = 18;
5592 if (bmp_version_major < 2)
5593 legacy_scripts_offset -= 4;
5594 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5595 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5596
5597 if (bmp_version_major > 2) { /* appears in BMP 3 */
5598 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5599 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5600 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5601 }
5602
5603 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5604 if (bmplength > 61)
5605 legacy_i2c_offset = offset + 54;
5606 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5607 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5608 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
6ee73861
BS		 5609
5610 if (bmplength > 74) {
5611 bios->fmaxvco = ROM32(bmp[67]);
5612 bios->fminvco = ROM32(bmp[71]);
5613 }
5614 if (bmplength > 88)
5615 parse_script_table_pointers(bios, offset + 75);
5616 if (bmplength > 94) {
5617 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5618 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5619 /*
5620 * Never observed in use with lvds scripts, but is reused for
5621 * 18/24 bit panel interface default for EDID equipped panels
5622 * (if_is_24bit not set directly to avoid any oscillation).
5623 */
5624 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5625 }
5626 if (bmplength > 108) {
5627 bios->fp.fptablepointer = ROM16(bmp[105]);
5628 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5629 bios->fp.xlatwidth = 1;
5630 }
5631 if (bmplength > 120) {
5632 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5633 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5634 }
5635 if (bmplength > 143)
5636 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5637
5638 if (bmplength > 157)
5639 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5640
5641 return 0;
5642}
5643
5644static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5645{
5646 int i, j;
5647
5648 for (i = 0; i <= (n - len); i++) {
5649 for (j = 0; j < len; j++)
5650 if (data[i + j] != str[j])
5651 break;
5652 if (j == len)
5653 return i;
5654 }
5655
5656 return 0;
5657}
5658
6ee73861
BS		 5659static struct dcb_gpio_entry *
5660new_gpio_entry(struct nvbios *bios)
5661{
e49f70f7 5662 struct drm_device *dev = bios->dev;
7f245b20 5663 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861 5664
e49f70f7
BS		 5665 if (gpio->entries >= DCB_MAX_NUM_GPIO_ENTRIES) {
5666 NV_ERROR(dev, "exceeded maximum number of gpio entries!!\n");
5667 return NULL;
5668 }
5669
6ee73861
BS		 5670 return &gpio->entry[gpio->entries++];
5671}
5672
5673struct dcb_gpio_entry *
5674nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5675{
5676 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5677 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5678 int i;
5679
7f245b20
BS		 5680 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5681 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5682 continue;
5683
7f245b20 5684 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5685 }
5686
5687 return NULL;
5688}
5689
6ee73861
BS		 5690static void
5691parse_dcb_gpio_table(struct nvbios *bios)
5692{
5693 struct drm_device *dev = bios->dev;
e49f70f7
BS		 5694 struct dcb_gpio_entry *e;
5695 u8 headerlen, entries, recordlen;
5696 u8 *dcb, *gpio = NULL, *entry;
6ee73861
BS		 5697 int i;
5698
f9f9f536 5699 dcb = ROMPTR(dev, bios->data[0x36]);
e49f70f7 5700 if (dcb[0] >= 0x30) {
f9f9f536 5701 gpio = ROMPTR(dev, dcb[10]);
e49f70f7
BS		 5702 if (!gpio)
5703 goto no_table;
6ee73861 5704
e49f70f7
BS		 5705 headerlen = gpio[1];
5706 entries = gpio[2];
5707 recordlen = gpio[3];
5708 } else
5e6a7443 5709 if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) {
f9f9f536 5710 gpio = ROMPTR(dev, dcb[-15]);
e49f70f7
BS		 5711 if (!gpio)
5712 goto no_table;
5713
5714 headerlen = 3;
5715 entries = gpio[2];
5716 recordlen = gpio[1];
5e6a7443
FJ		 5717 } else
5718 if (dcb[0] >= 0x22) {
5719 /* No GPIO table present, parse the TVDAC GPIO data. */
5720 uint8_t *tvdac_gpio = &dcb[-5];
6ee73861 5721
5e6a7443
FJ		 5722 if (tvdac_gpio[0] & 1) {
5723 e = new_gpio_entry(bios);
5724 e->tag = DCB_GPIO_TVDAC0;
5725 e->line = tvdac_gpio[1] >> 4;
85a2a365
BS		 5726 e->state[0] = !!(tvdac_gpio[0] & 2);
5727 e->state[1] = !e->state[0];
6ee73861
BS		 5728 }
5729
5e6a7443 5730 goto no_table;
e49f70f7
BS		 5731 } else {
5732 NV_DEBUG(dev, "no/unknown gpio table on DCB 0x%02x\n", dcb[0]);
5733 goto no_table;
5734 }
6ee73861 5735
e49f70f7
BS		 5736 entry = gpio + headerlen;
5737 for (i = 0; i < entries; i++, entry += recordlen) {
5738 e = new_gpio_entry(bios);
5739 if (!e)
5740 break;
6ee73861 5741
e49f70f7
BS		 5742 if (gpio[0] < 0x40) {
5743 e->entry = ROM16(entry[0]);
5744 e->tag = (e->entry & 0x07e0) >> 5;
5745 if (e->tag == 0x3f) {
5746 bios->dcb.gpio.entries--;
5747 continue;
5748 }
20d66daf 5749
e49f70f7 5750 e->line = (e->entry & 0x001f);
85a2a365
BS		 5751 e->state[0] = ((e->entry & 0xf800) >> 11) != 4;
5752 e->state[1] = !e->state[0];
e49f70f7
BS		 5753 } else {
5754 e->entry = ROM32(entry[0]);
5755 e->tag = (e->entry & 0x0000ff00) >> 8;
5756 if (e->tag == 0xff) {
5757 bios->dcb.gpio.entries--;
5758 continue;
5759 }
20d66daf 5760
e49f70f7 5761 e->line = (e->entry & 0x0000001f) >> 0;
d7f8172c
BS		 5762 if (gpio[0] == 0x40) {
5763 e->state_default = (e->entry & 0x01000000) >> 24;
5764 e->state[0] = (e->entry & 0x18000000) >> 27;
5765 e->state[1] = (e->entry & 0x60000000) >> 29;
5766 } else {
5767 e->state_default = (e->entry & 0x00000080) >> 7;
5768 e->state[0] = (entry[4] >> 4) & 3;
5769 e->state[1] = (entry[4] >> 6) & 3;
5770 }
20d66daf 5771 }
6ee73861
BS		 5772 }
5773
e49f70f7
BS		 5774no_table:
5775 /* Apple iMac G4 NV18 */
5776 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) {
5777 e = new_gpio_entry(bios);
5778 if (e) {
5779 e->tag = DCB_GPIO_TVDAC0;
5780 e->line = 4;
5781 }
6ee73861 5782 }
6ee73861
BS		 5783}
5784
5785struct dcb_connector_table_entry *
5786nouveau_bios_connector_entry(struct drm_device *dev, int index)
5787{
5788 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5789 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5790 struct dcb_connector_table_entry *cte;
5791
7f245b20 5792 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5793 return NULL;
5794
7f245b20 5795 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5796 if (cte->type == 0xff)
5797 return NULL;
5798
5799 return cte;
5800}
5801
f66fa771
BS		 5802static enum dcb_connector_type
5803divine_connector_type(struct nvbios *bios, int index)
5804{
5805 struct dcb_table *dcb = &bios->dcb;
5806 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5807 int i;
5808
5809 for (i = 0; i < dcb->entries; i++) {
5810 if (dcb->entry[i].connector == index)
5811 encoders |= (1 << dcb->entry[i].type);
5812 }
5813
5814 if (encoders & (1 << OUTPUT_DP)) {
5815 if (encoders & (1 << OUTPUT_TMDS))
5816 type = DCB_CONNECTOR_DP;
5817 else
5818 type = DCB_CONNECTOR_eDP;
5819 } else
5820 if (encoders & (1 << OUTPUT_TMDS)) {
5821 if (encoders & (1 << OUTPUT_ANALOG))
5822 type = DCB_CONNECTOR_DVI_I;
5823 else
5824 type = DCB_CONNECTOR_DVI_D;
5825 } else
5826 if (encoders & (1 << OUTPUT_ANALOG)) {
5827 type = DCB_CONNECTOR_VGA;
5828 } else
5829 if (encoders & (1 << OUTPUT_LVDS)) {
5830 type = DCB_CONNECTOR_LVDS;
5831 } else
5832 if (encoders & (1 << OUTPUT_TV)) {
5833 type = DCB_CONNECTOR_TV_0;
5834 }
5835
5836 return type;
5837}
5838
53c44c3a
BS		 5839static void
5840apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5841{
5842 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5843 struct drm_device *dev = bios->dev;
5844
5845 /* Gigabyte NX85T */
acae116c 5846 if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) {
53c44c3a
BS		 5847 if (cte->type == DCB_CONNECTOR_HDMI_1)
5848 cte->type = DCB_CONNECTOR_DVI_I;
5849 }
f0d07d6e
EV		 5850
5851 /* Gigabyte GV-NX86T512H */
5852 if (nv_match_device(dev, 0x0402, 0x1458, 0x3455)) {
5853 if (cte->type == DCB_CONNECTOR_HDMI_1)
5854 cte->type = DCB_CONNECTOR_DVI_I;
5855 }
53c44c3a
BS		 5856}
5857
a589e87f
BS		 5858static const u8 hpd_gpio[16] = {
5859 0xff, 0x07, 0x08, 0xff, 0xff, 0x51, 0x52, 0xff,
5860 0xff, 0xff, 0xff, 0xff, 0xff, 0x5e, 0x5f, 0x60,
5861};
5862
6ee73861
BS		 5863static void
5864parse_dcb_connector_table(struct nvbios *bios)
5865{
5866 struct drm_device *dev = bios->dev;
7f245b20 5867 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5868 struct dcb_connector_table_entry *cte;
7f245b20 5869 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5870 uint8_t *entry;
5871 int i;
5872
7f245b20 5873 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5874 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5875 return;
5876 }
5877
5878 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5879 conntab[0], conntab[1], conntab[2], conntab[3]);
5880 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5881 (conntab[3] != 2 && conntab[3] != 4)) {
5882 NV_ERROR(dev, " Unknown! Please report.\n");
5883 return;
5884 }
5885
5886 ct->entries = conntab[2];
5887
5888 entry = conntab + conntab[1];
5889 cte = &ct->entry[0];
5890 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 5891 cte->index = i;
6ee73861
BS		 5892 if (conntab[3] == 2)
5893 cte->entry = ROM16(entry[0]);
5894 else
5895 cte->entry = ROM32(entry[0]);
f66fa771 5896
6ee73861 5897 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 5898 cte->index2 = (cte->entry & 0x00000f00) >> 8;
a589e87f
BS		 5899
5900 cte->gpio_tag = ffs((cte->entry & 0x07033000) >> 12);
5901 cte->gpio_tag = hpd_gpio[cte->gpio_tag];
6ee73861
BS		 5902
5903 if (cte->type == 0xff)
5904 continue;
5905
53c44c3a
BS		 5906 apply_dcb_connector_quirks(bios, i);
5907
6ee73861
BS		 5908 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
5909 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 5910
5911 /* check for known types, fallback to guessing the type
5912 * from attached encoders if we hit an unknown.
5913 */
5914 switch (cte->type) {
5915 case DCB_CONNECTOR_VGA:
5916 case DCB_CONNECTOR_TV_0:
5917 case DCB_CONNECTOR_TV_1:
5918 case DCB_CONNECTOR_TV_3:
5919 case DCB_CONNECTOR_DVI_I:
5920 case DCB_CONNECTOR_DVI_D:
5921 case DCB_CONNECTOR_LVDS:
8c3f6bb9 5922 case DCB_CONNECTOR_LVDS_SPWG:
f66fa771
BS		 5923 case DCB_CONNECTOR_DP:
5924 case DCB_CONNECTOR_eDP:
5925 case DCB_CONNECTOR_HDMI_0:
5926 case DCB_CONNECTOR_HDMI_1:
5927 break;
5928 default:
5929 cte->type = divine_connector_type(bios, cte->index);
da647d5b 5930 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 5931 break;
5932 }
5933
da647d5b
BS		 5934 if (nouveau_override_conntype) {
5935 int type = divine_connector_type(bios, cte->index);
5936 if (type != cte->type)
5937 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
5938 }
5939
6ee73861
BS		 5940 }
5941}
5942
6b5a81a2
BS		 5943void *
5944dcb_table(struct drm_device *dev)
5945{
5946 struct drm_nouveau_private *dev_priv = dev->dev_private;
5947 u8 *dcb = NULL;
5948
5949 if (dev_priv->card_type > NV_04)
5950 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]);
5951 if (!dcb) {
5952 NV_WARNONCE(dev, "No DCB data found in VBIOS\n");
5953 return NULL;
5954 }
5955
5956 if (dcb[0] >= 0x41) {
5957 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]);
5958 return NULL;
5959 } else
5960 if (dcb[0] >= 0x30) {
5961 if (ROM32(dcb[6]) == 0x4edcbdcb)
5962 return dcb;
5963 } else
5964 if (dcb[0] >= 0x20) {
5965 if (ROM32(dcb[4]) == 0x4edcbdcb)
5966 return dcb;
5967 } else
5968 if (dcb[0] >= 0x15) {
5969 if (!memcmp(&dcb[-7], "DEV_REC", 7))
5970 return dcb;
5971 } else {
5972 /*
5973 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but
5974 * always has the same single (crt) entry, even when tv-out
5975 * present, so the conclusion is this version cannot really
5976 * be used.
5977 *
5978 * v1.2 tables (some NV6/10, and NV15+) normally have the
5979 * same 5 entries, which are not specific to the card and so
5980 * no use.
5981 *
5982 * v1.2 does have an I2C table that read_dcb_i2c_table can
5983 * handle, but cards exist (nv11 in #14821) with a bad i2c
5984 * table pointer, so use the indices parsed in
5985 * parse_bmp_structure.
5986 *
5987 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5988 */
5989 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n");
5990 return NULL;
5991 }
5992
5993 NV_WARNONCE(dev, "DCB header validation failed\n");
5994 return NULL;
5995}
5996
5997u8 *
5998dcb_outp(struct drm_device *dev, u8 idx)
5999{
6000 u8 *dcb = dcb_table(dev);
6001 if (dcb && dcb[0] >= 0x30) {
6002 if (idx < dcb[2])
6003 return dcb + dcb[1] + (idx * dcb[3]);
6004 } else
6005 if (dcb && dcb[0] >= 0x20) {
6006 u8 *i2c = ROMPTR(dev, dcb[2]);
6007 u8 *ent = dcb + 8 + (idx * 8);
6008 if (i2c && ent < i2c)
6009 return ent;
6010 } else
6011 if (dcb && dcb[0] >= 0x15) {
6012 u8 *i2c = ROMPTR(dev, dcb[2]);
6013 u8 *ent = dcb + 4 + (idx * 10);
6014 if (i2c && ent < i2c)
6015 return ent;
6016 }
6017
6018 return NULL;
6019}
6020
6021int
6022dcb_outp_foreach(struct drm_device *dev, void *data,
6023 int (*exec)(struct drm_device *, void *, int idx, u8 *outp))
6024{
6025 int ret, idx = -1;
6026 u8 *outp = NULL;
6027 while ((outp = dcb_outp(dev, ++idx))) {
6028 if (ROM32(outp[0]) == 0x00000000)
6029 break; /* seen on an NV11 with DCB v1.5 */
6030 if (ROM32(outp[0]) == 0xffffffff)
6031 break; /* seen on an NV17 with DCB v2.0 */
6032
6033 if ((outp[0] & 0x0f) == OUTPUT_UNUSED)
6034 continue;
6035 if ((outp[0] & 0x0f) == OUTPUT_EOL)
6036 break;
6037
6038 ret = exec(dev, data, idx, outp);
6039 if (ret)
6040 return ret;
6041 }
6042
6043 return 0;
6044}
6045
7f245b20 6046static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 6047{
6048 struct dcb_entry *entry = &dcb->entry[dcb->entries];
6049
6050 memset(entry, 0, sizeof(struct dcb_entry));
6051 entry->index = dcb->entries++;
6052
6053 return entry;
6054}
6055
2e5702af
FJ		 6056static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
6057 int heads, int or)
6ee73861
BS		 6058{
6059 struct dcb_entry *entry = new_dcb_entry(dcb);
6060
2e5702af 6061 entry->type = type;
6ee73861
BS		 6062 entry->i2c_index = i2c;
6063 entry->heads = heads;
2e5702af
FJ		 6064 if (type != OUTPUT_ANALOG)
6065 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
6066 entry->or = or;
6ee73861
BS		 6067}
6068
6069static bool
7f245b20 6070parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6071 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6072{
6073 entry->type = conn & 0xf;
6074 entry->i2c_index = (conn >> 4) & 0xf;
6075 entry->heads = (conn >> 8) & 0xf;
7f245b20 6076 if (dcb->version >= 0x40)
6ee73861
BS		 6077 entry->connector = (conn >> 12) & 0xf;
6078 entry->bus = (conn >> 16) & 0xf;
6079 entry->location = (conn >> 20) & 0x3;
6080 entry->or = (conn >> 24) & 0xf;
6ee73861
BS		 6081
6082 switch (entry->type) {
6083 case OUTPUT_ANALOG:
6084 /*
6085 * Although the rest of a CRT conf dword is usually
6086 * zeros, mac biosen have stuff there so we must mask
6087 */
7f245b20 6088 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 6089 (conf & 0xffff) * 10 :
6090 (conf & 0xff) * 10000;
6091 break;
6092 case OUTPUT_LVDS:
6093 {
6094 uint32_t mask;
6095 if (conf & 0x1)
6096 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 6097 if (dcb->version < 0x22) {
6ee73861
BS		 6098 mask = ~0xd;
6099 /*
6100 * The laptop in bug 14567 lies and claims to not use
6101 * straps when it does, so assume all DCB 2.0 laptops
6102 * use straps, until a broken EDID using one is produced
6103 */
6104 entry->lvdsconf.use_straps_for_mode = true;
6105 /*
6106 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
6107 * mean the same thing (probably wrong, but might work)
6108 */
6109 if (conf & 0x4 || conf & 0x8)
6110 entry->lvdsconf.use_power_scripts = true;
6111 } else {
a6ed76d7
BS		 6112 mask = ~0x7;
6113 if (conf & 0x2)
6114 entry->lvdsconf.use_acpi_for_edid = true;
6ee73861
BS		 6115 if (conf & 0x4)
6116 entry->lvdsconf.use_power_scripts = true;
c5875470 6117 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6ee73861
BS		 6118 }
6119 if (conf & mask) {
6120 /*
6121 * Until we even try to use these on G8x, it's
6122 * useless reporting unknown bits. They all are.
6123 */
7f245b20 6124 if (dcb->version >= 0x40)
6ee73861
BS		 6125 break;
6126
6127 NV_ERROR(dev, "Unknown LVDS configuration bits, "
6128 "please report\n");
6129 }
6130 break;
6131 }
6132 case OUTPUT_TV:
6133 {
7f245b20 6134 if (dcb->version >= 0x30)
6ee73861
BS		 6135 entry->tvconf.has_component_output = conf & (0x8 << 4);
6136 else
6137 entry->tvconf.has_component_output = false;
6138
6139 break;
6140 }
6141 case OUTPUT_DP:
6142 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
75a1fccf
BS		 6143 switch ((conf & 0x00e00000) >> 21) {
6144 case 0:
6145 entry->dpconf.link_bw = 162000;
6146 break;
6147 default:
6148 entry->dpconf.link_bw = 270000;
6149 break;
6150 }
6ee73861
BS		 6151 switch ((conf & 0x0f000000) >> 24) {
6152 case 0xf:
6153 entry->dpconf.link_nr = 4;
6154 break;
6155 case 0x3:
6156 entry->dpconf.link_nr = 2;
6157 break;
6158 default:
6159 entry->dpconf.link_nr = 1;
6160 break;
6161 }
6162 break;
6163 case OUTPUT_TMDS:
27d50fcc
FJ		 6164 if (dcb->version >= 0x40)
6165 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
4a9f822f
FJ		 6166 else if (dcb->version >= 0x30)
6167 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
27d50fcc
FJ		 6168 else if (dcb->version >= 0x22)
6169 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
4a9f822f 6170
6ee73861 6171 break;
44a1246f 6172 case OUTPUT_EOL:
6ee73861 6173 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 6174 dcb->entries--;
6ee73861 6175 return false;
e7cc51c5
BS		 6176 default:
6177 break;
6ee73861
BS		 6178 }
6179
23484874
BS		 6180 if (dcb->version < 0x40) {
6181 /* Normal entries consist of a single bit, but dual link has
6182 * the next most significant bit set too
6183 */
6184 entry->duallink_possible =
6185 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
6186 } else {
6187 entry->duallink_possible = (entry->sorconf.link == 3);
6188 }
6189
6ee73861
BS		 6190 /* unsure what DCB version introduces this, 3.0? */
6191 if (conf & 0x100000)
6192 entry->i2c_upper_default = true;
6193
6194 return true;
6195}
6196
6197static bool
7f245b20 6198parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6199 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6200{
b0d2de86
BS		 6201 switch (conn & 0x0000000f) {
6202 case 0:
6203 entry->type = OUTPUT_ANALOG;
6204 break;
6205 case 1:
6206 entry->type = OUTPUT_TV;
6207 break;
6208 case 2:
b0d2de86 6209 case 4:
fba67528 6210 if (conn & 0x10)
b0d2de86 6211 entry->type = OUTPUT_LVDS;
fba67528
FJ		 6212 else
6213 entry->type = OUTPUT_TMDS;
6214 break;
6215 case 3:
6216 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 6217 break;
6218 default:
6219 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
6220 return false;
6ee73861 6221 }
b0d2de86
BS		 6222
6223 entry->i2c_index = (conn & 0x0003c000) >> 14;
6224 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
6225 entry->or = entry->heads; /* same as heads, hopefully safe enough */
6226 entry->location = (conn & 0x01e00000) >> 21;
6227 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 6228 entry->duallink_possible = false;
6229
6230 switch (entry->type) {
6231 case OUTPUT_ANALOG:
6232 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
6233 break;
b0d2de86
BS		 6234 case OUTPUT_TV:
6235 entry->tvconf.has_component_output = false;
6ee73861 6236 break;
b0d2de86 6237 case OUTPUT_LVDS:
77b1d5dc 6238 if ((conn & 0x00003f00) >> 8 != 0x10)
b0d2de86
BS		 6239 entry->lvdsconf.use_straps_for_mode = true;
6240 entry->lvdsconf.use_power_scripts = true;
6241 break;
6242 default:
6ee73861
BS		 6243 break;
6244 }
6245
6246 return true;
6247}
6248
6ee73861 6249static
7f245b20 6250void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 6251{
6252 /*
6253 * DCB v2.0 lists each output combination separately.
6254 * Here we merge compatible entries to have fewer outputs, with
6255 * more options
6256 */
6257
6258 int i, newentries = 0;
6259
6260 for (i = 0; i < dcb->entries; i++) {
6261 struct dcb_entry *ient = &dcb->entry[i];
6262 int j;
6263
6264 for (j = i + 1; j < dcb->entries; j++) {
6265 struct dcb_entry *jent = &dcb->entry[j];
6266
6267 if (jent->type == 100) /* already merged entry */
6268 continue;
6269
6270 /* merge heads field when all other fields the same */
6271 if (jent->i2c_index == ient->i2c_index &&
6272 jent->type == ient->type &&
6273 jent->location == ient->location &&
6274 jent->or == ient->or) {
6275 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
6276 i, j);
6277 ient->heads |= jent->heads;
6278 jent->type = 100; /* dummy value */
6279 }
6280 }
6281 }
6282
6283 /* Compact entries merged into others out of dcb */
6284 for (i = 0; i < dcb->entries; i++) {
6285 if (dcb->entry[i].type == 100)
6286 continue;
6287
6288 if (newentries != i) {
6289 dcb->entry[newentries] = dcb->entry[i];
6290 dcb->entry[newentries].index = newentries;
6291 }
6292 newentries++;
6293 }
6294
6295 dcb->entries = newentries;
6296}
6297
df4cf1b7
BS		 6298static bool
6299apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6300{
670820c0
FJ		 6301 struct drm_nouveau_private *dev_priv = dev->dev_private;
6302 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6303
df4cf1b7
BS		 6304 /* Dell Precision M6300
6305 * DCB entry 2: 02025312 00000010
6306 * DCB entry 3: 02026312 00000020
6307 *
6308 * Identical, except apparently a different connector on a
6309 * different SOR link. Not a clue how we're supposed to know
6310 * which one is in use if it even shares an i2c line...
6311 *
6312 * Ignore the connector on the second SOR link to prevent
6313 * nasty problems until this is sorted (assuming it's not a
6314 * VBIOS bug).
6315 */
acae116c 6316 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
df4cf1b7
BS		 6317 if (*conn == 0x02026312 && *conf == 0x00000020)
6318 return false;
6319 }
6320
670820c0
FJ		 6321 /* GeForce3 Ti 200
6322 *
6323 * DCB reports an LVDS output that should be TMDS:
6324 * DCB entry 1: f2005014 ffffffff
6325 */
6326 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
6327 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
6328 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
6329 return false;
6330 }
6331 }
6332
c0929b49
BS		 6333 /* XFX GT-240X-YA
6334 *
6335 * So many things wrong here, replace the entire encoder table..
6336 */
6337 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6338 if (idx == 0) {
6339 *conn = 0x02001300; /* VGA, connector 1 */
6340 *conf = 0x00000028;
6341 } else
6342 if (idx == 1) {
6343 *conn = 0x01010312; /* DVI, connector 0 */
6344 *conf = 0x00020030;
6345 } else
6346 if (idx == 2) {
6347 *conn = 0x01010310; /* VGA, connector 0 */
6348 *conf = 0x00000028;
6349 } else
6350 if (idx == 3) {
6351 *conn = 0x02022362; /* HDMI, connector 2 */
6352 *conf = 0x00020010;
6353 } else {
6354 *conn = 0x0000000e; /* EOL */
6355 *conf = 0x00000000;
6356 }
6357 }
6358
e540afc3
BS		 6359 /* Some other twisted XFX board (rhbz#694914)
6360 *
6361 * The DVI/VGA encoder combo that's supposed to represent the
6362 * DVI-I connector actually point at two different ones, and
6363 * the HDMI connector ends up paired with the VGA instead.
6364 *
6365 * Connector table is missing anything for VGA at all, pointing it
6366 * an invalid conntab entry 2 so we figure it out ourself.
6367 */
6368 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
6369 if (idx == 0) {
6370 *conn = 0x02002300; /* VGA, connector 2 */
6371 *conf = 0x00000028;
6372 } else
6373 if (idx == 1) {
6374 *conn = 0x01010312; /* DVI, connector 0 */
6375 *conf = 0x00020030;
6376 } else
6377 if (idx == 2) {
6378 *conn = 0x04020310; /* VGA, connector 0 */
6379 *conf = 0x00000028;
6380 } else
6381 if (idx == 3) {
6382 *conn = 0x02021322; /* HDMI, connector 1 */
6383 *conf = 0x00020010;
6384 } else {
6385 *conn = 0x0000000e; /* EOL */
6386 *conf = 0x00000000;
6387 }
6388 }
6389
df4cf1b7
BS		 6390 return true;
6391}
6392
2e5702af
FJ		 6393static void
6394fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6395{
6396 struct dcb_table *dcb = &bios->dcb;
6397 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6398
6399#ifdef __powerpc__
6400 /* Apple iMac G4 NV17 */
6401 if (of_machine_is_compatible("PowerMac4,5")) {
6402 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6403 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6404 return;
6405 }
6406#endif
6407
6408 /* Make up some sane defaults */
0f8067c7
BS		 6409 fabricate_dcb_output(dcb, OUTPUT_ANALOG,
6410 bios->legacy.i2c_indices.crt, 1, 1);
2e5702af
FJ		 6411
6412 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
0f8067c7
BS		 6413 fabricate_dcb_output(dcb, OUTPUT_TV,
6414 bios->legacy.i2c_indices.tv,
2e5702af
FJ		 6415 all_heads, 0);
6416
6417 else if (bios->tmds.output0_script_ptr ||
6418 bios->tmds.output1_script_ptr)
0f8067c7
BS		 6419 fabricate_dcb_output(dcb, OUTPUT_TMDS,
6420 bios->legacy.i2c_indices.panel,
2e5702af
FJ		 6421 all_heads, 1);
6422}
6423
ed42f824 6424static int
6b5a81a2 6425parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
6ee73861 6426{
ed42f824 6427 struct drm_nouveau_private *dev_priv = dev->dev_private;
6b5a81a2
BS		 6428 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6429 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]);
6430 u32 conn = ROM32(outp[0]);
6431 bool ret;
6ee73861 6432
6b5a81a2
BS		 6433 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) {
6434 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861 6435
6b5a81a2 6436 NV_TRACEWARN(dev, "DCB entry %02d: %08x %08x\n", idx, conn, conf);
6ee73861 6437
6b5a81a2
BS		 6438 if (dcb->version >= 0x20)
6439 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6440 else
6441 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6442 if (!ret)
6443 return 1; /* stop parsing */
6b5a81a2 6444 }
6ee73861 6445
6b5a81a2
BS		 6446 return 0;
6447}
6ee73861 6448
6b5a81a2
BS		 6449static int
6450parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6451{
6452 struct dcb_table *dcb = &bios->dcb;
6b5a81a2
BS		 6453 u8 *dcbt;
6454
6455 dcbt = dcb_table(dev);
6456 if (!dcbt) {
6457 /* handle pre-DCB boards */
6458 if (bios->type == NVBIOS_BMP) {
6459 fabricate_dcb_encoder_table(dev, bios);
6460 return 0;
6ee73861
BS		 6461 }
6462
6b5a81a2
BS		 6463 return -EINVAL;
6464 }
6ee73861 6465
6b5a81a2 6466 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf);
6ee73861 6467
6b5a81a2
BS		 6468 dcb->version = dcbt[0];
6469 if (dcb->version >= 0x30) {
6b5a81a2
BS		 6470 dcb->gpio_table_ptr = ROM16(dcbt[10]);
6471 dcb->connector_table_ptr = ROM16(dcbt[20]);
6ee73861
BS		 6472 }
6473
6b5a81a2 6474 dcb_outp_foreach(dev, NULL, parse_dcb_entry);
6ee73861
BS		 6475
6476 /*
6477 * apart for v2.1+ not being known for requiring merging, this
6478 * guarantees dcbent->index is the index of the entry in the rom image
6479 */
7f245b20 6480 if (dcb->version < 0x21)
6ee73861
BS		 6481 merge_like_dcb_entries(dev, dcb);
6482
54abb5dd
BS		 6483 if (!dcb->entries)
6484 return -ENXIO;
6485
6486 parse_dcb_gpio_table(bios);
6487 parse_dcb_connector_table(bios);
6488 return 0;
6ee73861
BS		 6489}
6490
6491static void
6492fixup_legacy_connector(struct nvbios *bios)
6493{
7f245b20 6494 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 6495 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 6496
6497 /*
6498 * DCB 3.0 also has the table in most cases, but there are some cards
6499 * where the table is filled with stub entries, and the DCB entriy
6500 * indices are all 0. We don't need the connector indices on pre-G80
6501 * chips (yet?) so limit the use to DCB 4.0 and above.
6502 */
7f245b20 6503 if (dcb->version >= 0x40)
6ee73861
BS		 6504 return;
6505
dc5bc4ed
BS		 6506 dcb->connector.entries = 0;
6507
6ee73861
BS		 6508 /*
6509 * No known connector info before v3.0, so make it up. the rule here
6510 * is: anything on the same i2c bus is considered to be on the same
6511 * connector. any output without an associated i2c bus is assigned
6512 * its own unique connector index.
6513 */
6514 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 6515 /*
6516 * Ignore the I2C index for on-chip TV-out, as there
6517 * are cards with bogus values (nv31m in bug 23212),
6518 * and it's otherwise useless.
6519 */
6520 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 6521 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 6522 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 6523 i2c = dcb->entry[i].i2c_index;
6524
6525 if (i2c_conn[i2c]) {
6526 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 6527 continue;
6528 }
6529
dc5bc4ed
BS		 6530 dcb->entry[i].connector = dcb->connector.entries++;
6531 if (i2c != 0xf)
6532 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 6533 }
6534
dc5bc4ed
BS		 6535 /* Fake the connector table as well as just connector indices */
6536 for (i = 0; i < dcb->connector.entries; i++) {
6537 dcb->connector.entry[i].index = i;
6538 dcb->connector.entry[i].type = divine_connector_type(bios, i);
6539 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 6540 }
6541}
6542
6ee73861
BS		 6543static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6544{
6545 /*
6546 * The header following the "HWSQ" signature has the number of entries,
6547 * and the entry size
6548 *
6549 * An entry consists of a dword to write to the sequencer control reg
6550 * (0x00001304), followed by the ucode bytes, written sequentially,
6551 * starting at reg 0x00001400
6552 */
6553
6554 uint8_t bytes_to_write;
6555 uint16_t hwsq_entry_offset;
6556 int i;
6557
6558 if (bios->data[hwsq_offset] <= entry) {
6559 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6560 "requested entry\n");
6561 return -ENOENT;
6562 }
6563
6564 bytes_to_write = bios->data[hwsq_offset + 1];
6565
6566 if (bytes_to_write != 36) {
6567 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6568 return -EINVAL;
6569 }
6570
6571 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6572
6573 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6574
6575 /* set sequencer control */
6576 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6577 bytes_to_write -= 4;
6578
6579 /* write ucode */
6580 for (i = 0; i < bytes_to_write; i += 4)
6581 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6582
6583 /* twiddle NV_PBUS_DEBUG_4 */
6584 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6585
6586 return 0;
6587}
6588
6589static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6590 struct nvbios *bios)
6591{
6592 /*
6593 * BMP based cards, from NV17, need a microcode loading to correctly
6594 * control the GPIO etc for LVDS panels
6595 *
6596 * BIT based cards seem to do this directly in the init scripts
6597 *
6598 * The microcode entries are found by the "HWSQ" signature.
6599 */
6600
6601 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6602 const int sz = sizeof(hwsq_signature);
6603 int hwsq_offset;
6604
6605 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6606 if (!hwsq_offset)
6607 return 0;
6608
6609 /* always use entry 0? */
6610 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6611}
6612
6613uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6614{
6615 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6616 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6617 const uint8_t edid_sig[] = {
6618 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6619 uint16_t offset = 0;
6620 uint16_t newoffset;
6621 int searchlen = NV_PROM_SIZE;
6622
6623 if (bios->fp.edid)
6624 return bios->fp.edid;
6625
6626 while (searchlen) {
6627 newoffset = findstr(&bios->data[offset], searchlen,
6628 edid_sig, 8);
6629 if (!newoffset)
6630 return NULL;
6631 offset += newoffset;
6632 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6633 break;
6634
6635 searchlen -= offset;
6636 offset++;
6637 }
6638
6639 NV_TRACE(dev, "Found EDID in BIOS\n");
6640
6641 return bios->fp.edid = &bios->data[offset];
6642}
6643
6644void
6645nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
02e4f587 6646 struct dcb_entry *dcbent, int crtc)
6ee73861
BS		 6647{
6648 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6649 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6650 struct init_exec iexec = { true, false };
6651
c7ca4d1b 6652 spin_lock_bh(&bios->lock);
6ee73861 6653 bios->display.output = dcbent;
02e4f587 6654 bios->display.crtc = crtc;
6ee73861
BS		 6655 parse_init_table(bios, table, &iexec);
6656 bios->display.output = NULL;
c7ca4d1b 6657 spin_unlock_bh(&bios->lock);
6ee73861
BS		 6658}
6659
59ef9742
BS		 6660void
6661nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
6662{
6663 struct drm_nouveau_private *dev_priv = dev->dev_private;
6664 struct nvbios *bios = &dev_priv->vbios;
6665 struct init_exec iexec = { true, false };
6666
6667 parse_init_table(bios, table, &iexec);
6668}
6669
6ee73861
BS		 6670static bool NVInitVBIOS(struct drm_device *dev)
6671{
6672 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6673 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6674
6675 memset(bios, 0, sizeof(struct nvbios));
c7ca4d1b 6676 spin_lock_init(&bios->lock);
6ee73861
BS		 6677 bios->dev = dev;
6678
6679 if (!NVShadowVBIOS(dev, bios->data))
6680 return false;
6681
6682 bios->length = NV_PROM_SIZE;
6683 return true;
6684}
6685
6686static int nouveau_parse_vbios_struct(struct drm_device *dev)
6687{
6688 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6689 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6690 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6691 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6692 int offset;
6693
6694 offset = findstr(bios->data, bios->length,
6695 bit_signature, sizeof(bit_signature));
6696 if (offset) {
6697 NV_TRACE(dev, "BIT BIOS found\n");
4709bff0
BS		 6698 bios->type = NVBIOS_BIT;
6699 bios->offset = offset;
6ee73861
BS		 6700 return parse_bit_structure(bios, offset + 6);
6701 }
6702
6703 offset = findstr(bios->data, bios->length,
6704 bmp_signature, sizeof(bmp_signature));
6705 if (offset) {
6706 NV_TRACE(dev, "BMP BIOS found\n");
4709bff0
BS		 6707 bios->type = NVBIOS_BMP;
6708 bios->offset = offset;
6ee73861
BS		 6709 return parse_bmp_structure(dev, bios, offset);
6710 }
6711
6712 NV_ERROR(dev, "No known BIOS signature found\n");
6713 return -ENODEV;
6714}
6715
6716int
6717nouveau_run_vbios_init(struct drm_device *dev)
6718{
6719 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6720 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6721 int i, ret = 0;
6722
946fd35f
FJ		 6723 /* Reset the BIOS head to 0. */
6724 bios->state.crtchead = 0;
6ee73861
BS		 6725
6726 if (bios->major_version < 5) /* BMP only */
6727 load_nv17_hw_sequencer_ucode(dev, bios);
6728
6729 if (bios->execute) {
6730 bios->fp.last_script_invoc = 0;
6731 bios->fp.lvds_init_run = false;
6732 }
6733
6734 parse_init_tables(bios);
6735
6736 /*
6737 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6738 * parser will run this right after the init tables, the binary
6739 * driver appears to run it at some point later.
6740 */
6741 if (bios->some_script_ptr) {
6742 struct init_exec iexec = {true, false};
6743
6744 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6745 bios->some_script_ptr);
6746 parse_init_table(bios, bios->some_script_ptr, &iexec);
6747 }
6748
6749 if (dev_priv->card_type >= NV_50) {
7f245b20 6750 for (i = 0; i < bios->dcb.entries; i++) {
02e4f587
BS		 6751 nouveau_bios_run_display_table(dev, 0, 0,
6752 &bios->dcb.entry[i], -1);
6ee73861
BS		 6753 }
6754 }
6755
6ee73861
BS		 6756 return ret;
6757}
6758
d13102c6
BS		 6759static bool
6760nouveau_bios_posted(struct drm_device *dev)
6761{
6762 struct drm_nouveau_private *dev_priv = dev->dev_private;
d13102c6
BS		 6763 unsigned htotal;
6764
c1b60ece 6765 if (dev_priv->card_type >= NV_50) {
d13102c6
BS		 6766 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6767 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6768 return false;
6769 return true;
6770 }
6771
d13102c6
BS		 6772 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6773 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6774 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6775 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6776 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
03cd06ca 6777
d13102c6
BS		 6778 return (htotal != 0);
6779}
6780
6ee73861
BS		 6781int
6782nouveau_bios_init(struct drm_device *dev)
6783{
6784 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6785 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6786 int ret;
6787
6ee73861
BS		 6788 if (!NVInitVBIOS(dev))
6789 return -ENODEV;
6790
6791 ret = nouveau_parse_vbios_struct(dev);
6792 if (ret)
6793 return ret;
6794
486a45c2
BS		 6795 ret = nouveau_i2c_init(dev);
6796 if (ret)
6797 return ret;
6798
2e5702af 6799 ret = parse_dcb_table(dev, bios);
6ee73861
BS		 6800 if (ret)
6801 return ret;
6802
6ee73861
BS		 6803 fixup_legacy_connector(bios);
6804
6805 if (!bios->major_version) /* we don't run version 0 bios */
6806 return 0;
6807
6ee73861
BS		 6808 /* init script execution disabled */
6809 bios->execute = false;
6810
6811 /* ... unless card isn't POSTed already */
d13102c6 6812 if (!nouveau_bios_posted(dev)) {
67eda20e
FJ		 6813 NV_INFO(dev, "Adaptor not initialised, "
6814 "running VBIOS init tables.\n");
6ee73861
BS		 6815 bios->execute = true;
6816 }
0cba1b76
MK		 6817 if (nouveau_force_post)
6818 bios->execute = true;
6ee73861 6819
6ee73861 6820 ret = nouveau_run_vbios_init(dev);
04a39c57 6821 if (ret)
6ee73861 6822 return ret;
6ee73861
BS		 6823
6824 /* feature_byte on BMP is poor, but init always sets CR4B */
6ee73861
BS		 6825 if (bios->major_version < 5)
6826 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6827
6828 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6829 if (bios->is_mobile || bios->major_version >= 5)
6830 ret = parse_fp_mode_table(dev, bios);
6ee73861
BS		 6831
6832 /* allow subsequent scripts to execute */
6833 bios->execute = true;
6834
6835 return 0;
6836}
6837
6838void
6839nouveau_bios_takedown(struct drm_device *dev)
6840{
486a45c2 6841 nouveau_i2c_fini(dev);
6ee73861 6842}
Linux kernel - Deliverables
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