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drm/nouveau: Use semaphores to handle inter-channel sync in hardware.
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include "drmP.h"
31
32#include "nouveau_drm.h"
33#include "nouveau_drv.h"
34#include "nouveau_dma.h"
35
a510604d 36#include <linux/log2.h>
5a0e3ad6 37#include <linux/slab.h>
a510604d 38
6ee73861
BS		 39static void
40nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
41{
42 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
a0af9add 43 struct drm_device *dev = dev_priv->dev;
6ee73861
BS		 44 struct nouveau_bo *nvbo = nouveau_bo(bo);
45
6ee73861
BS		 46 if (unlikely(nvbo->gem))
47 DRM_ERROR("bo %p still attached to GEM object\n", bo);
48
a0af9add
FJ		 49 if (nvbo->tile)
50 nv10_mem_expire_tiling(dev, nvbo->tile, NULL);
51
6ee73861
BS		 52 kfree(nvbo);
53}
54
a0af9add
FJ		 55static void
56nouveau_bo_fixup_align(struct drm_device *dev,
57 uint32_t tile_mode, uint32_t tile_flags,
58 int *align, int *size)
59{
60 struct drm_nouveau_private *dev_priv = dev->dev_private;
61
62 /*
63 * Some of the tile_flags have a periodic structure of N*4096 bytes,
eb1dba0e
MM		 64 * align to to that as well as the page size. Align the size to the
65 * appropriate boundaries. This does imply that sizes are rounded up
66 * 3-7 pages, so be aware of this and do not waste memory by allocating
67 * many small buffers.
a0af9add
FJ		 68 */
69 if (dev_priv->card_type == NV_50) {
a76fb4e8 70 uint32_t block_size = dev_priv->vram_size >> 15;
a510604d
MM		 71 int i;
72
a0af9add
FJ		 73 switch (tile_flags) {
74 case 0x1800:
75 case 0x2800:
76 case 0x4800:
77 case 0x7a00:
a510604d 78 if (is_power_of_2(block_size)) {
a510604d
MM		 79 for (i = 1; i < 10; i++) {
80 *align = 12 * i * block_size;
81 if (!(*align % 65536))
82 break;
83 }
a0af9add 84 } else {
a510604d
MM		 85 for (i = 1; i < 10; i++) {
86 *align = 8 * i * block_size;
87 if (!(*align % 65536))
88 break;
89 }
a0af9add 90 }
eb1dba0e 91 *size = roundup(*size, *align);
a0af9add
FJ		 92 break;
93 default:
94 break;
95 }
96
97 } else {
98 if (tile_mode) {
99 if (dev_priv->chipset >= 0x40) {
100 *align = 65536;
101 *size = roundup(*size, 64 * tile_mode);
102
103 } else if (dev_priv->chipset >= 0x30) {
104 *align = 32768;
105 *size = roundup(*size, 64 * tile_mode);
106
107 } else if (dev_priv->chipset >= 0x20) {
108 *align = 16384;
109 *size = roundup(*size, 64 * tile_mode);
110
111 } else if (dev_priv->chipset >= 0x10) {
112 *align = 16384;
113 *size = roundup(*size, 32 * tile_mode);
114 }
115 }
116 }
117
1c7059e4
MM		 118 /* ALIGN works only on powers of two. */
119 *size = roundup(*size, PAGE_SIZE);
a0af9add
FJ		 120
121 if (dev_priv->card_type == NV_50) {
1c7059e4 122 *size = roundup(*size, 65536);
a0af9add
FJ		 123 *align = max(65536, *align);
124 }
125}
126
6ee73861
BS		 127int
128nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan,
129 int size, int align, uint32_t flags, uint32_t tile_mode,
130 uint32_t tile_flags, bool no_vm, bool mappable,
131 struct nouveau_bo **pnvbo)
132{
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 struct nouveau_bo *nvbo;
8dea4a19 135 int ret = 0;
6ee73861
BS		 136
137 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
138 if (!nvbo)
139 return -ENOMEM;
140 INIT_LIST_HEAD(&nvbo->head);
141 INIT_LIST_HEAD(&nvbo->entry);
142 nvbo->mappable = mappable;
143 nvbo->no_vm = no_vm;
144 nvbo->tile_mode = tile_mode;
145 nvbo->tile_flags = tile_flags;
146
a0af9add 147 nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size);
6ee73861
BS		 148 align >>= PAGE_SHIFT;
149
78ad0f7b 150 nouveau_bo_placement_set(nvbo, flags, 0);
6ee73861
BS		 151
152 nvbo->channel = chan;
6ee73861
BS		 153 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
154 ttm_bo_type_device, &nvbo->placement, align, 0,
155 false, NULL, size, nouveau_bo_del_ttm);
6ee73861
BS		 156 if (ret) {
157 /* ttm will call nouveau_bo_del_ttm if it fails.. */
158 return ret;
159 }
90af89b9 160 nvbo->channel = NULL;
6ee73861 161
6ee73861
BS		 162 *pnvbo = nvbo;
163 return 0;
164}
165
78ad0f7b
FJ		 166static void
167set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
168{
169 *n = 0;
170
171 if (type & TTM_PL_FLAG_VRAM)
172 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
173 if (type & TTM_PL_FLAG_TT)
174 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
175 if (type & TTM_PL_FLAG_SYSTEM)
176 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
177}
178
6ee73861 179void
78ad0f7b 180nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
6ee73861 181{
78ad0f7b
FJ		 182 struct ttm_placement *pl = &nvbo->placement;
183 uint32_t flags = TTM_PL_MASK_CACHING |
184 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
185
186 pl->placement = nvbo->placements;
187 set_placement_list(nvbo->placements, &pl->num_placement,
188 type, flags);
189
190 pl->busy_placement = nvbo->busy_placements;
191 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
192 type | busy, flags);
6ee73861
BS		 193}
194
195int
196nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
197{
198 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
199 struct ttm_buffer_object *bo = &nvbo->bo;
78ad0f7b 200 int ret;
6ee73861
BS		 201
202 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
203 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
204 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
205 1 << bo->mem.mem_type, memtype);
206 return -EINVAL;
207 }
208
209 if (nvbo->pin_refcnt++)
210 return 0;
211
212 ret = ttm_bo_reserve(bo, false, false, false, 0);
213 if (ret)
214 goto out;
215
78ad0f7b 216 nouveau_bo_placement_set(nvbo, memtype, 0);
6ee73861 217
9d87fa21 218 ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
6ee73861
BS		 219 if (ret == 0) {
220 switch (bo->mem.mem_type) {
221 case TTM_PL_VRAM:
222 dev_priv->fb_aper_free -= bo->mem.size;
223 break;
224 case TTM_PL_TT:
225 dev_priv->gart_info.aper_free -= bo->mem.size;
226 break;
227 default:
228 break;
229 }
230 }
231 ttm_bo_unreserve(bo);
232out:
233 if (unlikely(ret))
234 nvbo->pin_refcnt--;
235 return ret;
236}
237
238int
239nouveau_bo_unpin(struct nouveau_bo *nvbo)
240{
241 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
242 struct ttm_buffer_object *bo = &nvbo->bo;
78ad0f7b 243 int ret;
6ee73861
BS		 244
245 if (--nvbo->pin_refcnt)
246 return 0;
247
248 ret = ttm_bo_reserve(bo, false, false, false, 0);
249 if (ret)
250 return ret;
251
78ad0f7b 252 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
6ee73861 253
9d87fa21 254 ret = ttm_bo_validate(bo, &nvbo->placement, false, false, false);
6ee73861
BS		 255 if (ret == 0) {
256 switch (bo->mem.mem_type) {
257 case TTM_PL_VRAM:
258 dev_priv->fb_aper_free += bo->mem.size;
259 break;
260 case TTM_PL_TT:
261 dev_priv->gart_info.aper_free += bo->mem.size;
262 break;
263 default:
264 break;
265 }
266 }
267
268 ttm_bo_unreserve(bo);
269 return ret;
270}
271
272int
273nouveau_bo_map(struct nouveau_bo *nvbo)
274{
275 int ret;
276
277 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
278 if (ret)
279 return ret;
280
281 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
282 ttm_bo_unreserve(&nvbo->bo);
283 return ret;
284}
285
286void
287nouveau_bo_unmap(struct nouveau_bo *nvbo)
288{
9d59e8a1
BS		 289 if (nvbo)
290 ttm_bo_kunmap(&nvbo->kmap);
6ee73861
BS		 291}
292
293u16
294nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
295{
296 bool is_iomem;
297 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
298 mem = &mem[index];
299 if (is_iomem)
300 return ioread16_native((void __force __iomem *)mem);
301 else
302 return *mem;
303}
304
305void
306nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
307{
308 bool is_iomem;
309 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
310 mem = &mem[index];
311 if (is_iomem)
312 iowrite16_native(val, (void __force __iomem *)mem);
313 else
314 *mem = val;
315}
316
317u32
318nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
319{
320 bool is_iomem;
321 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
322 mem = &mem[index];
323 if (is_iomem)
324 return ioread32_native((void __force __iomem *)mem);
325 else
326 return *mem;
327}
328
329void
330nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
331{
332 bool is_iomem;
333 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
334 mem = &mem[index];
335 if (is_iomem)
336 iowrite32_native(val, (void __force __iomem *)mem);
337 else
338 *mem = val;
339}
340
341static struct ttm_backend *
342nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev)
343{
344 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
345 struct drm_device *dev = dev_priv->dev;
346
347 switch (dev_priv->gart_info.type) {
b694dfb2 348#if __OS_HAS_AGP
6ee73861
BS		 349 case NOUVEAU_GART_AGP:
350 return ttm_agp_backend_init(bdev, dev->agp->bridge);
b694dfb2 351#endif
6ee73861
BS		 352 case NOUVEAU_GART_SGDMA:
353 return nouveau_sgdma_init_ttm(dev);
354 default:
355 NV_ERROR(dev, "Unknown GART type %d\n",
356 dev_priv->gart_info.type);
357 break;
358 }
359
360 return NULL;
361}
362
363static int
364nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
365{
366 /* We'll do this from user space. */
367 return 0;
368}
369
370static int
371nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
372 struct ttm_mem_type_manager *man)
373{
374 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
375 struct drm_device *dev = dev_priv->dev;
376
377 switch (type) {
378 case TTM_PL_SYSTEM:
379 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
380 man->available_caching = TTM_PL_MASK_CACHING;
381 man->default_caching = TTM_PL_FLAG_CACHED;
382 break;
383 case TTM_PL_VRAM:
384 man->flags = TTM_MEMTYPE_FLAG_FIXED |
f32f02fd 385 TTM_MEMTYPE_FLAG_MAPPABLE;
6ee73861
BS		 386 man->available_caching = TTM_PL_FLAG_UNCACHED |
387 TTM_PL_FLAG_WC;
388 man->default_caching = TTM_PL_FLAG_WC;
fbd2895e
BS		 389 if (dev_priv->card_type == NV_50)
390 man->gpu_offset = 0x40000000;
391 else
392 man->gpu_offset = 0;
6ee73861
BS		 393 break;
394 case TTM_PL_TT:
395 switch (dev_priv->gart_info.type) {
396 case NOUVEAU_GART_AGP:
f32f02fd 397 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
6ee73861
BS		 398 man->available_caching = TTM_PL_FLAG_UNCACHED;
399 man->default_caching = TTM_PL_FLAG_UNCACHED;
400 break;
401 case NOUVEAU_GART_SGDMA:
402 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
403 TTM_MEMTYPE_FLAG_CMA;
404 man->available_caching = TTM_PL_MASK_CACHING;
405 man->default_caching = TTM_PL_FLAG_CACHED;
406 break;
407 default:
408 NV_ERROR(dev, "Unknown GART type: %d\n",
409 dev_priv->gart_info.type);
410 return -EINVAL;
411 }
6ee73861
BS		 412 man->gpu_offset = dev_priv->vm_gart_base;
413 break;
414 default:
415 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
416 return -EINVAL;
417 }
418 return 0;
419}
420
421static void
422nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
423{
424 struct nouveau_bo *nvbo = nouveau_bo(bo);
425
426 switch (bo->mem.mem_type) {
22fbd538 427 case TTM_PL_VRAM:
78ad0f7b
FJ		 428 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
429 TTM_PL_FLAG_SYSTEM);
22fbd538 430 break;
6ee73861 431 default:
78ad0f7b 432 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
6ee73861
BS		 433 break;
434 }
22fbd538
FJ		 435
436 *pl = nvbo->placement;
6ee73861
BS		 437}
438
439
440/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
441 * TTM_PL_{VRAM,TT} directly.
442 */
a0af9add 443
6ee73861
BS		 444static int
445nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
9d87fa21
JG		 446 struct nouveau_bo *nvbo, bool evict,
447 bool no_wait_reserve, bool no_wait_gpu,
6ee73861
BS		 448 struct ttm_mem_reg *new_mem)
449{
450 struct nouveau_fence *fence = NULL;
451 int ret;
452
453 ret = nouveau_fence_new(chan, &fence, true);
454 if (ret)
455 return ret;
456
457 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL,
311ab694
FJ		 458 evict || (nvbo->channel &&
459 nvbo->channel != chan),
460 no_wait_reserve, no_wait_gpu, new_mem);
6ee73861
BS		 461 nouveau_fence_unref((void *)&fence);
462 return ret;
463}
464
465static inline uint32_t
f1ab0cc9
BS		 466nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
467 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
6ee73861 468{
f1ab0cc9
BS		 469 struct nouveau_bo *nvbo = nouveau_bo(bo);
470
471 if (nvbo->no_vm) {
6ee73861
BS		 472 if (mem->mem_type == TTM_PL_TT)
473 return NvDmaGART;
474 return NvDmaVRAM;
475 }
476
477 if (mem->mem_type == TTM_PL_TT)
478 return chan->gart_handle;
479 return chan->vram_handle;
480}
481
482static int
f1ab0cc9
BS		 483nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
484 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
6ee73861 485{
6ee73861 486 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
f1ab0cc9
BS		 487 struct nouveau_bo *nvbo = nouveau_bo(bo);
488 u64 length = (new_mem->num_pages << PAGE_SHIFT);
489 u64 src_offset, dst_offset;
6ee73861
BS		 490 int ret;
491
6ee73861
BS		 492 src_offset = old_mem->mm_node->start << PAGE_SHIFT;
493 dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
f1ab0cc9
BS		 494 if (!nvbo->no_vm) {
495 if (old_mem->mem_type == TTM_PL_VRAM)
6ee73861 496 src_offset += dev_priv->vm_vram_base;
6ee73861 497 else
f1ab0cc9
BS		 498 src_offset += dev_priv->vm_gart_base;
499
500 if (new_mem->mem_type == TTM_PL_VRAM)
6ee73861 501 dst_offset += dev_priv->vm_vram_base;
f1ab0cc9
BS		 502 else
503 dst_offset += dev_priv->vm_gart_base;
6ee73861
BS		 504 }
505
506 ret = RING_SPACE(chan, 3);
507 if (ret)
508 return ret;
6ee73861 509
f1ab0cc9
BS		 510 BEGIN_RING(chan, NvSubM2MF, 0x0184, 2);
511 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
512 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
513
514 while (length) {
515 u32 amount, stride, height;
516
5220b3c1
BS		 517 amount = min(length, (u64)(4 * 1024 * 1024));
518 stride = 16 * 4;
f1ab0cc9
BS		 519 height = amount / stride;
520
521 if (new_mem->mem_type == TTM_PL_VRAM && nvbo->tile_flags) {
522 ret = RING_SPACE(chan, 8);
523 if (ret)
524 return ret;
525
526 BEGIN_RING(chan, NvSubM2MF, 0x0200, 7);
527 OUT_RING (chan, 0);
5220b3c1 528 OUT_RING (chan, 0);
f1ab0cc9
BS		 529 OUT_RING (chan, stride);
530 OUT_RING (chan, height);
531 OUT_RING (chan, 1);
532 OUT_RING (chan, 0);
533 OUT_RING (chan, 0);
534 } else {
535 ret = RING_SPACE(chan, 2);
536 if (ret)
537 return ret;
538
539 BEGIN_RING(chan, NvSubM2MF, 0x0200, 1);
540 OUT_RING (chan, 1);
541 }
542 if (old_mem->mem_type == TTM_PL_VRAM && nvbo->tile_flags) {
543 ret = RING_SPACE(chan, 8);
544 if (ret)
545 return ret;
546
547 BEGIN_RING(chan, NvSubM2MF, 0x021c, 7);
548 OUT_RING (chan, 0);
5220b3c1 549 OUT_RING (chan, 0);
f1ab0cc9
BS		 550 OUT_RING (chan, stride);
551 OUT_RING (chan, height);
552 OUT_RING (chan, 1);
553 OUT_RING (chan, 0);
554 OUT_RING (chan, 0);
555 } else {
556 ret = RING_SPACE(chan, 2);
557 if (ret)
558 return ret;
559
560 BEGIN_RING(chan, NvSubM2MF, 0x021c, 1);
561 OUT_RING (chan, 1);
562 }
563
564 ret = RING_SPACE(chan, 14);
6ee73861
BS		 565 if (ret)
566 return ret;
f1ab0cc9
BS		 567
568 BEGIN_RING(chan, NvSubM2MF, 0x0238, 2);
569 OUT_RING (chan, upper_32_bits(src_offset));
570 OUT_RING (chan, upper_32_bits(dst_offset));
571 BEGIN_RING(chan, NvSubM2MF, 0x030c, 8);
572 OUT_RING (chan, lower_32_bits(src_offset));
573 OUT_RING (chan, lower_32_bits(dst_offset));
574 OUT_RING (chan, stride);
575 OUT_RING (chan, stride);
576 OUT_RING (chan, stride);
577 OUT_RING (chan, height);
578 OUT_RING (chan, 0x00000101);
579 OUT_RING (chan, 0x00000000);
580 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
581 OUT_RING (chan, 0);
582
583 length -= amount;
584 src_offset += amount;
585 dst_offset += amount;
6ee73861
BS		 586 }
587
f1ab0cc9
BS		 588 return 0;
589}
590
591static int
592nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
593 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
594{
595 u32 src_offset = old_mem->mm_node->start << PAGE_SHIFT;
596 u32 dst_offset = new_mem->mm_node->start << PAGE_SHIFT;
597 u32 page_count = new_mem->num_pages;
598 int ret;
599
600 ret = RING_SPACE(chan, 3);
601 if (ret)
602 return ret;
603
604 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
605 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
606 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
607
6ee73861
BS		 608 page_count = new_mem->num_pages;
609 while (page_count) {
610 int line_count = (page_count > 2047) ? 2047 : page_count;
611
6ee73861
BS		 612 ret = RING_SPACE(chan, 11);
613 if (ret)
614 return ret;
f1ab0cc9 615
6ee73861
BS		 616 BEGIN_RING(chan, NvSubM2MF,
617 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
f1ab0cc9
BS		 618 OUT_RING (chan, src_offset);
619 OUT_RING (chan, dst_offset);
620 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
621 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
622 OUT_RING (chan, PAGE_SIZE); /* line_length */
623 OUT_RING (chan, line_count);
624 OUT_RING (chan, 0x00000101);
625 OUT_RING (chan, 0x00000000);
6ee73861 626 BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
f1ab0cc9 627 OUT_RING (chan, 0);
6ee73861
BS		 628
629 page_count -= line_count;
630 src_offset += (PAGE_SIZE * line_count);
631 dst_offset += (PAGE_SIZE * line_count);
632 }
633
f1ab0cc9
BS		 634 return 0;
635}
636
637static int
638nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
639 bool no_wait_reserve, bool no_wait_gpu,
640 struct ttm_mem_reg *new_mem)
641{
642 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
643 struct nouveau_bo *nvbo = nouveau_bo(bo);
644 struct nouveau_channel *chan;
645 int ret;
646
647 chan = nvbo->channel;
648 if (!chan || nvbo->no_vm)
649 chan = dev_priv->channel;
650
651 if (dev_priv->card_type < NV_50)
652 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
653 else
654 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
655 if (ret)
656 return ret;
657
9d87fa21 658 return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861
BS		 659}
660
661static int
662nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
9d87fa21
JG		 663 bool no_wait_reserve, bool no_wait_gpu,
664 struct ttm_mem_reg *new_mem)
6ee73861
BS		 665{
666 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
667 struct ttm_placement placement;
668 struct ttm_mem_reg tmp_mem;
669 int ret;
670
671 placement.fpfn = placement.lpfn = 0;
672 placement.num_placement = placement.num_busy_placement = 1;
77e2b5ed 673 placement.placement = placement.busy_placement = &placement_memtype;
6ee73861
BS		 674
675 tmp_mem = *new_mem;
676 tmp_mem.mm_node = NULL;
9d87fa21 677 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
6ee73861
BS		 678 if (ret)
679 return ret;
680
681 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
682 if (ret)
683 goto out;
684
9d87fa21 685 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
6ee73861
BS		 686 if (ret)
687 goto out;
688
9d87fa21 689 ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861
BS		 690out:
691 if (tmp_mem.mm_node) {
692 spin_lock(&bo->bdev->glob->lru_lock);
693 drm_mm_put_block(tmp_mem.mm_node);
694 spin_unlock(&bo->bdev->glob->lru_lock);
695 }
696
697 return ret;
698}
699
700static int
701nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
9d87fa21
JG		 702 bool no_wait_reserve, bool no_wait_gpu,
703 struct ttm_mem_reg *new_mem)
6ee73861
BS		 704{
705 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
706 struct ttm_placement placement;
707 struct ttm_mem_reg tmp_mem;
708 int ret;
709
710 placement.fpfn = placement.lpfn = 0;
711 placement.num_placement = placement.num_busy_placement = 1;
77e2b5ed 712 placement.placement = placement.busy_placement = &placement_memtype;
6ee73861
BS		 713
714 tmp_mem = *new_mem;
715 tmp_mem.mm_node = NULL;
9d87fa21 716 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
6ee73861
BS		 717 if (ret)
718 return ret;
719
9d87fa21 720 ret = ttm_bo_move_ttm(bo, evict, no_wait_reserve, no_wait_gpu, &tmp_mem);
6ee73861
BS		 721 if (ret)
722 goto out;
723
9d87fa21 724 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861
BS		 725 if (ret)
726 goto out;
727
728out:
729 if (tmp_mem.mm_node) {
730 spin_lock(&bo->bdev->glob->lru_lock);
731 drm_mm_put_block(tmp_mem.mm_node);
732 spin_unlock(&bo->bdev->glob->lru_lock);
733 }
734
735 return ret;
736}
737
738static int
a0af9add
FJ		 739nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
740 struct nouveau_tile_reg **new_tile)
6ee73861
BS		 741{
742 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
6ee73861 743 struct drm_device *dev = dev_priv->dev;
a0af9add
FJ		 744 struct nouveau_bo *nvbo = nouveau_bo(bo);
745 uint64_t offset;
6ee73861
BS		 746 int ret;
747
a0af9add
FJ		 748 if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) {
749 /* Nothing to do. */
750 *new_tile = NULL;
751 return 0;
752 }
753
754 offset = new_mem->mm_node->start << PAGE_SHIFT;
6ee73861 755
a0af9add 756 if (dev_priv->card_type == NV_50) {
6ee73861
BS		 757 ret = nv50_mem_vm_bind_linear(dev,
758 offset + dev_priv->vm_vram_base,
759 new_mem->size, nvbo->tile_flags,
760 offset);
761 if (ret)
762 return ret;
a0af9add
FJ		 763
764 } else if (dev_priv->card_type >= NV_10) {
765 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
766 nvbo->tile_mode);
6ee73861
BS		 767 }
768
a0af9add
FJ		 769 return 0;
770}
771
772static void
773nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
774 struct nouveau_tile_reg *new_tile,
775 struct nouveau_tile_reg **old_tile)
776{
777 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
778 struct drm_device *dev = dev_priv->dev;
779
780 if (dev_priv->card_type >= NV_10 &&
781 dev_priv->card_type < NV_50) {
782 if (*old_tile)
783 nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj);
784
785 *old_tile = new_tile;
786 }
787}
788
789static int
790nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
9d87fa21
JG		 791 bool no_wait_reserve, bool no_wait_gpu,
792 struct ttm_mem_reg *new_mem)
a0af9add
FJ		 793{
794 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
795 struct nouveau_bo *nvbo = nouveau_bo(bo);
796 struct ttm_mem_reg *old_mem = &bo->mem;
797 struct nouveau_tile_reg *new_tile = NULL;
798 int ret = 0;
799
800 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
801 if (ret)
802 return ret;
803
a0af9add 804 /* Fake bo copy. */
6ee73861
BS		 805 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
806 BUG_ON(bo->mem.mm_node != NULL);
807 bo->mem = *new_mem;
808 new_mem->mm_node = NULL;
a0af9add 809 goto out;
6ee73861
BS		 810 }
811
b8a6a804
BS		 812 /* Software copy if the card isn't up and running yet. */
813 if (!dev_priv->channel) {
814 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
815 goto out;
816 }
817
a0af9add
FJ		 818 /* Hardware assisted copy. */
819 if (new_mem->mem_type == TTM_PL_SYSTEM)
9d87fa21 820 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
a0af9add 821 else if (old_mem->mem_type == TTM_PL_SYSTEM)
9d87fa21 822 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
a0af9add 823 else
9d87fa21 824 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861 825
a0af9add
FJ		 826 if (!ret)
827 goto out;
828
829 /* Fallback to software copy. */
9d87fa21 830 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
a0af9add
FJ		 831
832out:
833 if (ret)
834 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
835 else
836 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
837
838 return ret;
6ee73861
BS		 839}
840
841static int
842nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
843{
844 return 0;
845}
846
f32f02fd
JG		 847static int
848nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
849{
850 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
851 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
852 struct drm_device *dev = dev_priv->dev;
853
854 mem->bus.addr = NULL;
855 mem->bus.offset = 0;
856 mem->bus.size = mem->num_pages << PAGE_SHIFT;
857 mem->bus.base = 0;
858 mem->bus.is_iomem = false;
859 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
860 return -EINVAL;
861 switch (mem->mem_type) {
862 case TTM_PL_SYSTEM:
863 /* System memory */
864 return 0;
865 case TTM_PL_TT:
866#if __OS_HAS_AGP
867 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
868 mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
869 mem->bus.base = dev_priv->gart_info.aper_base;
870 mem->bus.is_iomem = true;
871 }
872#endif
873 break;
874 case TTM_PL_VRAM:
875 mem->bus.offset = mem->mm_node->start << PAGE_SHIFT;
01d73a69 876 mem->bus.base = pci_resource_start(dev->pdev, 1);
f32f02fd
JG		 877 mem->bus.is_iomem = true;
878 break;
879 default:
880 return -EINVAL;
881 }
882 return 0;
883}
884
885static void
886nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
887{
888}
889
890static int
891nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
892{
e1429b4c
BS		 893 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
894 struct nouveau_bo *nvbo = nouveau_bo(bo);
895
896 /* as long as the bo isn't in vram, and isn't tiled, we've got
897 * nothing to do here.
898 */
899 if (bo->mem.mem_type != TTM_PL_VRAM) {
9bb5863a 900 if (dev_priv->card_type < NV_50 || !nvbo->tile_flags)
e1429b4c
BS		 901 return 0;
902 }
903
904 /* make sure bo is in mappable vram */
905 if (bo->mem.mm_node->start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
906 return 0;
907
908
909 nvbo->placement.fpfn = 0;
910 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
911 nouveau_bo_placement_set(nvbo, TTM_PL_VRAM, 0);
912 return ttm_bo_validate(bo, &nvbo->placement, false, true, false);
f32f02fd
JG		 913}
914
6ee73861
BS		 915struct ttm_bo_driver nouveau_bo_driver = {
916 .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry,
917 .invalidate_caches = nouveau_bo_invalidate_caches,
918 .init_mem_type = nouveau_bo_init_mem_type,
919 .evict_flags = nouveau_bo_evict_flags,
920 .move = nouveau_bo_move,
921 .verify_access = nouveau_bo_verify_access,
922 .sync_obj_signaled = nouveau_fence_signalled,
923 .sync_obj_wait = nouveau_fence_wait,
924 .sync_obj_flush = nouveau_fence_flush,
925 .sync_obj_unref = nouveau_fence_unref,
926 .sync_obj_ref = nouveau_fence_ref,
f32f02fd
JG		 927 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
928 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
929 .io_mem_free = &nouveau_ttm_io_mem_free,
6ee73861
BS		 930};
931
Linux kernel - Deliverables
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