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6ee73861 BS |
1 | /* |
2 | * Copyright 2007 Dave Airlied | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * Authors: Dave Airlied <airlied@linux.ie> | |
26 | * Ben Skeggs <darktama@iinet.net.au> | |
27 | * Jeremy Kolb <jkolb@brandeis.edu> | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | ||
32 | #include "nouveau_drm.h" | |
33 | #include "nouveau_drv.h" | |
34 | #include "nouveau_dma.h" | |
35 | ||
36 | static void | |
37 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) | |
38 | { | |
39 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
a0af9add | 40 | struct drm_device *dev = dev_priv->dev; |
6ee73861 BS |
41 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
42 | ||
43 | ttm_bo_kunmap(&nvbo->kmap); | |
44 | ||
45 | if (unlikely(nvbo->gem)) | |
46 | DRM_ERROR("bo %p still attached to GEM object\n", bo); | |
47 | ||
a0af9add FJ |
48 | if (nvbo->tile) |
49 | nv10_mem_expire_tiling(dev, nvbo->tile, NULL); | |
50 | ||
6ee73861 BS |
51 | spin_lock(&dev_priv->ttm.bo_list_lock); |
52 | list_del(&nvbo->head); | |
53 | spin_unlock(&dev_priv->ttm.bo_list_lock); | |
54 | kfree(nvbo); | |
55 | } | |
56 | ||
a0af9add FJ |
57 | static void |
58 | nouveau_bo_fixup_align(struct drm_device *dev, | |
59 | uint32_t tile_mode, uint32_t tile_flags, | |
60 | int *align, int *size) | |
61 | { | |
62 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
63 | ||
64 | /* | |
65 | * Some of the tile_flags have a periodic structure of N*4096 bytes, | |
66 | * align to to that as well as the page size. Overallocate memory to | |
67 | * avoid corruption of other buffer objects. | |
68 | */ | |
69 | if (dev_priv->card_type == NV_50) { | |
70 | switch (tile_flags) { | |
71 | case 0x1800: | |
72 | case 0x2800: | |
73 | case 0x4800: | |
74 | case 0x7a00: | |
75 | if (dev_priv->chipset >= 0xA0) { | |
76 | /* This is based on high end cards with 448 bits | |
77 | * memory bus, could be different elsewhere.*/ | |
78 | *size += 6 * 28672; | |
79 | /* 8 * 28672 is the actual alignment requirement | |
80 | * but we must also align to page size. */ | |
81 | *align = 2 * 8 * 28672; | |
82 | } else if (dev_priv->chipset >= 0x90) { | |
83 | *size += 3 * 16384; | |
84 | *align = 12 * 16384; | |
85 | } else { | |
86 | *size += 3 * 8192; | |
87 | /* 12 * 8192 is the actual alignment requirement | |
88 | * but we must also align to page size. */ | |
89 | *align = 2 * 12 * 8192; | |
90 | } | |
91 | break; | |
92 | default: | |
93 | break; | |
94 | } | |
95 | ||
96 | } else { | |
97 | if (tile_mode) { | |
98 | if (dev_priv->chipset >= 0x40) { | |
99 | *align = 65536; | |
100 | *size = roundup(*size, 64 * tile_mode); | |
101 | ||
102 | } else if (dev_priv->chipset >= 0x30) { | |
103 | *align = 32768; | |
104 | *size = roundup(*size, 64 * tile_mode); | |
105 | ||
106 | } else if (dev_priv->chipset >= 0x20) { | |
107 | *align = 16384; | |
108 | *size = roundup(*size, 64 * tile_mode); | |
109 | ||
110 | } else if (dev_priv->chipset >= 0x10) { | |
111 | *align = 16384; | |
112 | *size = roundup(*size, 32 * tile_mode); | |
113 | } | |
114 | } | |
115 | } | |
116 | ||
117 | *size = ALIGN(*size, PAGE_SIZE); | |
118 | ||
119 | if (dev_priv->card_type == NV_50) { | |
120 | *size = ALIGN(*size, 65536); | |
121 | *align = max(65536, *align); | |
122 | } | |
123 | } | |
124 | ||
6ee73861 BS |
125 | int |
126 | nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, | |
127 | int size, int align, uint32_t flags, uint32_t tile_mode, | |
128 | uint32_t tile_flags, bool no_vm, bool mappable, | |
129 | struct nouveau_bo **pnvbo) | |
130 | { | |
131 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
132 | struct nouveau_bo *nvbo; | |
8dea4a19 | 133 | int ret = 0; |
6ee73861 BS |
134 | |
135 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); | |
136 | if (!nvbo) | |
137 | return -ENOMEM; | |
138 | INIT_LIST_HEAD(&nvbo->head); | |
139 | INIT_LIST_HEAD(&nvbo->entry); | |
140 | nvbo->mappable = mappable; | |
141 | nvbo->no_vm = no_vm; | |
142 | nvbo->tile_mode = tile_mode; | |
143 | nvbo->tile_flags = tile_flags; | |
144 | ||
a0af9add | 145 | nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size); |
6ee73861 BS |
146 | align >>= PAGE_SHIFT; |
147 | ||
6ee73861 BS |
148 | nvbo->placement.fpfn = 0; |
149 | nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; | |
8dea4a19 | 150 | nouveau_bo_placement_set(nvbo, flags); |
6ee73861 BS |
151 | |
152 | nvbo->channel = chan; | |
6ee73861 BS |
153 | ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, |
154 | ttm_bo_type_device, &nvbo->placement, align, 0, | |
155 | false, NULL, size, nouveau_bo_del_ttm); | |
156 | nvbo->channel = NULL; | |
157 | if (ret) { | |
158 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ | |
159 | return ret; | |
160 | } | |
161 | ||
162 | spin_lock(&dev_priv->ttm.bo_list_lock); | |
163 | list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list); | |
164 | spin_unlock(&dev_priv->ttm.bo_list_lock); | |
165 | *pnvbo = nvbo; | |
166 | return 0; | |
167 | } | |
168 | ||
169 | void | |
170 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype) | |
171 | { | |
172 | int n = 0; | |
173 | ||
174 | if (memtype & TTM_PL_FLAG_VRAM) | |
175 | nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING; | |
176 | if (memtype & TTM_PL_FLAG_TT) | |
177 | nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
178 | if (memtype & TTM_PL_FLAG_SYSTEM) | |
179 | nvbo->placements[n++] = TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; | |
180 | nvbo->placement.placement = nvbo->placements; | |
181 | nvbo->placement.busy_placement = nvbo->placements; | |
182 | nvbo->placement.num_placement = n; | |
183 | nvbo->placement.num_busy_placement = n; | |
37cb3e08 BS |
184 | |
185 | if (nvbo->pin_refcnt) { | |
186 | while (n--) | |
187 | nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT; | |
188 | } | |
6ee73861 BS |
189 | } |
190 | ||
191 | int | |
192 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) | |
193 | { | |
194 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
195 | struct ttm_buffer_object *bo = &nvbo->bo; | |
196 | int ret, i; | |
197 | ||
198 | if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { | |
199 | NV_ERROR(nouveau_bdev(bo->bdev)->dev, | |
200 | "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo, | |
201 | 1 << bo->mem.mem_type, memtype); | |
202 | return -EINVAL; | |
203 | } | |
204 | ||
205 | if (nvbo->pin_refcnt++) | |
206 | return 0; | |
207 | ||
208 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
209 | if (ret) | |
210 | goto out; | |
211 | ||
212 | nouveau_bo_placement_set(nvbo, memtype); | |
213 | for (i = 0; i < nvbo->placement.num_placement; i++) | |
214 | nvbo->placements[i] |= TTM_PL_FLAG_NO_EVICT; | |
215 | ||
216 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false); | |
217 | if (ret == 0) { | |
218 | switch (bo->mem.mem_type) { | |
219 | case TTM_PL_VRAM: | |
220 | dev_priv->fb_aper_free -= bo->mem.size; | |
221 | break; | |
222 | case TTM_PL_TT: | |
223 | dev_priv->gart_info.aper_free -= bo->mem.size; | |
224 | break; | |
225 | default: | |
226 | break; | |
227 | } | |
228 | } | |
229 | ttm_bo_unreserve(bo); | |
230 | out: | |
231 | if (unlikely(ret)) | |
232 | nvbo->pin_refcnt--; | |
233 | return ret; | |
234 | } | |
235 | ||
236 | int | |
237 | nouveau_bo_unpin(struct nouveau_bo *nvbo) | |
238 | { | |
239 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
240 | struct ttm_buffer_object *bo = &nvbo->bo; | |
241 | int ret, i; | |
242 | ||
243 | if (--nvbo->pin_refcnt) | |
244 | return 0; | |
245 | ||
246 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
247 | if (ret) | |
248 | return ret; | |
249 | ||
250 | for (i = 0; i < nvbo->placement.num_placement; i++) | |
251 | nvbo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; | |
252 | ||
253 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false); | |
254 | if (ret == 0) { | |
255 | switch (bo->mem.mem_type) { | |
256 | case TTM_PL_VRAM: | |
257 | dev_priv->fb_aper_free += bo->mem.size; | |
258 | break; | |
259 | case TTM_PL_TT: | |
260 | dev_priv->gart_info.aper_free += bo->mem.size; | |
261 | break; | |
262 | default: | |
263 | break; | |
264 | } | |
265 | } | |
266 | ||
267 | ttm_bo_unreserve(bo); | |
268 | return ret; | |
269 | } | |
270 | ||
271 | int | |
272 | nouveau_bo_map(struct nouveau_bo *nvbo) | |
273 | { | |
274 | int ret; | |
275 | ||
276 | ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0); | |
277 | if (ret) | |
278 | return ret; | |
279 | ||
280 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); | |
281 | ttm_bo_unreserve(&nvbo->bo); | |
282 | return ret; | |
283 | } | |
284 | ||
285 | void | |
286 | nouveau_bo_unmap(struct nouveau_bo *nvbo) | |
287 | { | |
288 | ttm_bo_kunmap(&nvbo->kmap); | |
289 | } | |
290 | ||
291 | u16 | |
292 | nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) | |
293 | { | |
294 | bool is_iomem; | |
295 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
296 | mem = &mem[index]; | |
297 | if (is_iomem) | |
298 | return ioread16_native((void __force __iomem *)mem); | |
299 | else | |
300 | return *mem; | |
301 | } | |
302 | ||
303 | void | |
304 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) | |
305 | { | |
306 | bool is_iomem; | |
307 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
308 | mem = &mem[index]; | |
309 | if (is_iomem) | |
310 | iowrite16_native(val, (void __force __iomem *)mem); | |
311 | else | |
312 | *mem = val; | |
313 | } | |
314 | ||
315 | u32 | |
316 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) | |
317 | { | |
318 | bool is_iomem; | |
319 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
320 | mem = &mem[index]; | |
321 | if (is_iomem) | |
322 | return ioread32_native((void __force __iomem *)mem); | |
323 | else | |
324 | return *mem; | |
325 | } | |
326 | ||
327 | void | |
328 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) | |
329 | { | |
330 | bool is_iomem; | |
331 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
332 | mem = &mem[index]; | |
333 | if (is_iomem) | |
334 | iowrite32_native(val, (void __force __iomem *)mem); | |
335 | else | |
336 | *mem = val; | |
337 | } | |
338 | ||
339 | static struct ttm_backend * | |
340 | nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev) | |
341 | { | |
342 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
343 | struct drm_device *dev = dev_priv->dev; | |
344 | ||
345 | switch (dev_priv->gart_info.type) { | |
b694dfb2 | 346 | #if __OS_HAS_AGP |
6ee73861 BS |
347 | case NOUVEAU_GART_AGP: |
348 | return ttm_agp_backend_init(bdev, dev->agp->bridge); | |
b694dfb2 | 349 | #endif |
6ee73861 BS |
350 | case NOUVEAU_GART_SGDMA: |
351 | return nouveau_sgdma_init_ttm(dev); | |
352 | default: | |
353 | NV_ERROR(dev, "Unknown GART type %d\n", | |
354 | dev_priv->gart_info.type); | |
355 | break; | |
356 | } | |
357 | ||
358 | return NULL; | |
359 | } | |
360 | ||
361 | static int | |
362 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
363 | { | |
364 | /* We'll do this from user space. */ | |
365 | return 0; | |
366 | } | |
367 | ||
368 | static int | |
369 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
370 | struct ttm_mem_type_manager *man) | |
371 | { | |
372 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
373 | struct drm_device *dev = dev_priv->dev; | |
374 | ||
375 | switch (type) { | |
376 | case TTM_PL_SYSTEM: | |
377 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
378 | man->available_caching = TTM_PL_MASK_CACHING; | |
379 | man->default_caching = TTM_PL_FLAG_CACHED; | |
380 | break; | |
381 | case TTM_PL_VRAM: | |
382 | man->flags = TTM_MEMTYPE_FLAG_FIXED | | |
383 | TTM_MEMTYPE_FLAG_MAPPABLE | | |
384 | TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; | |
385 | man->available_caching = TTM_PL_FLAG_UNCACHED | | |
386 | TTM_PL_FLAG_WC; | |
387 | man->default_caching = TTM_PL_FLAG_WC; | |
388 | ||
389 | man->io_addr = NULL; | |
390 | man->io_offset = drm_get_resource_start(dev, 1); | |
391 | man->io_size = drm_get_resource_len(dev, 1); | |
392 | if (man->io_size > nouveau_mem_fb_amount(dev)) | |
393 | man->io_size = nouveau_mem_fb_amount(dev); | |
394 | ||
395 | man->gpu_offset = dev_priv->vm_vram_base; | |
396 | break; | |
397 | case TTM_PL_TT: | |
398 | switch (dev_priv->gart_info.type) { | |
399 | case NOUVEAU_GART_AGP: | |
400 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | | |
401 | TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; | |
402 | man->available_caching = TTM_PL_FLAG_UNCACHED; | |
403 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
404 | break; | |
405 | case NOUVEAU_GART_SGDMA: | |
406 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | | |
407 | TTM_MEMTYPE_FLAG_CMA; | |
408 | man->available_caching = TTM_PL_MASK_CACHING; | |
409 | man->default_caching = TTM_PL_FLAG_CACHED; | |
410 | break; | |
411 | default: | |
412 | NV_ERROR(dev, "Unknown GART type: %d\n", | |
413 | dev_priv->gart_info.type); | |
414 | return -EINVAL; | |
415 | } | |
416 | ||
417 | man->io_offset = dev_priv->gart_info.aper_base; | |
418 | man->io_size = dev_priv->gart_info.aper_size; | |
419 | man->io_addr = NULL; | |
420 | man->gpu_offset = dev_priv->vm_gart_base; | |
421 | break; | |
422 | default: | |
423 | NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type); | |
424 | return -EINVAL; | |
425 | } | |
426 | return 0; | |
427 | } | |
428 | ||
429 | static void | |
430 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |
431 | { | |
432 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
433 | ||
434 | switch (bo->mem.mem_type) { | |
22fbd538 FJ |
435 | case TTM_PL_VRAM: |
436 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT | | |
437 | TTM_PL_FLAG_SYSTEM); | |
438 | break; | |
6ee73861 BS |
439 | default: |
440 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM); | |
441 | break; | |
442 | } | |
22fbd538 FJ |
443 | |
444 | *pl = nvbo->placement; | |
6ee73861 BS |
445 | } |
446 | ||
447 | ||
448 | /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access | |
449 | * TTM_PL_{VRAM,TT} directly. | |
450 | */ | |
a0af9add | 451 | |
6ee73861 BS |
452 | static int |
453 | nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, | |
454 | struct nouveau_bo *nvbo, bool evict, bool no_wait, | |
455 | struct ttm_mem_reg *new_mem) | |
456 | { | |
457 | struct nouveau_fence *fence = NULL; | |
458 | int ret; | |
459 | ||
460 | ret = nouveau_fence_new(chan, &fence, true); | |
461 | if (ret) | |
462 | return ret; | |
463 | ||
464 | ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, | |
465 | evict, no_wait, new_mem); | |
466 | nouveau_fence_unref((void *)&fence); | |
467 | return ret; | |
468 | } | |
469 | ||
470 | static inline uint32_t | |
471 | nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan, | |
472 | struct ttm_mem_reg *mem) | |
473 | { | |
474 | if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) { | |
475 | if (mem->mem_type == TTM_PL_TT) | |
476 | return NvDmaGART; | |
477 | return NvDmaVRAM; | |
478 | } | |
479 | ||
480 | if (mem->mem_type == TTM_PL_TT) | |
481 | return chan->gart_handle; | |
482 | return chan->vram_handle; | |
483 | } | |
484 | ||
485 | static int | |
a0af9add FJ |
486 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, |
487 | int no_wait, struct ttm_mem_reg *new_mem) | |
6ee73861 BS |
488 | { |
489 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
490 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
a0af9add | 491 | struct ttm_mem_reg *old_mem = &bo->mem; |
6ee73861 BS |
492 | struct nouveau_channel *chan; |
493 | uint64_t src_offset, dst_offset; | |
494 | uint32_t page_count; | |
495 | int ret; | |
496 | ||
497 | chan = nvbo->channel; | |
0735f62e | 498 | if (!chan || nvbo->tile_flags || nvbo->no_vm) |
6ee73861 | 499 | chan = dev_priv->channel; |
6ee73861 BS |
500 | |
501 | src_offset = old_mem->mm_node->start << PAGE_SHIFT; | |
502 | dst_offset = new_mem->mm_node->start << PAGE_SHIFT; | |
503 | if (chan != dev_priv->channel) { | |
504 | if (old_mem->mem_type == TTM_PL_TT) | |
505 | src_offset += dev_priv->vm_gart_base; | |
506 | else | |
507 | src_offset += dev_priv->vm_vram_base; | |
508 | ||
509 | if (new_mem->mem_type == TTM_PL_TT) | |
510 | dst_offset += dev_priv->vm_gart_base; | |
511 | else | |
512 | dst_offset += dev_priv->vm_vram_base; | |
513 | } | |
514 | ||
515 | ret = RING_SPACE(chan, 3); | |
516 | if (ret) | |
517 | return ret; | |
518 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); | |
519 | OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem)); | |
520 | OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem)); | |
521 | ||
522 | if (dev_priv->card_type >= NV_50) { | |
523 | ret = RING_SPACE(chan, 4); | |
524 | if (ret) | |
525 | return ret; | |
526 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); | |
527 | OUT_RING(chan, 1); | |
528 | BEGIN_RING(chan, NvSubM2MF, 0x021c, 1); | |
529 | OUT_RING(chan, 1); | |
530 | } | |
531 | ||
532 | page_count = new_mem->num_pages; | |
533 | while (page_count) { | |
534 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
535 | ||
536 | if (dev_priv->card_type >= NV_50) { | |
537 | ret = RING_SPACE(chan, 3); | |
538 | if (ret) | |
539 | return ret; | |
540 | BEGIN_RING(chan, NvSubM2MF, 0x0238, 2); | |
541 | OUT_RING(chan, upper_32_bits(src_offset)); | |
542 | OUT_RING(chan, upper_32_bits(dst_offset)); | |
543 | } | |
544 | ret = RING_SPACE(chan, 11); | |
545 | if (ret) | |
546 | return ret; | |
547 | BEGIN_RING(chan, NvSubM2MF, | |
548 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
549 | OUT_RING(chan, lower_32_bits(src_offset)); | |
550 | OUT_RING(chan, lower_32_bits(dst_offset)); | |
551 | OUT_RING(chan, PAGE_SIZE); /* src_pitch */ | |
552 | OUT_RING(chan, PAGE_SIZE); /* dst_pitch */ | |
553 | OUT_RING(chan, PAGE_SIZE); /* line_length */ | |
554 | OUT_RING(chan, line_count); | |
555 | OUT_RING(chan, (1<<8)|(1<<0)); | |
556 | OUT_RING(chan, 0); | |
557 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); | |
558 | OUT_RING(chan, 0); | |
559 | ||
560 | page_count -= line_count; | |
561 | src_offset += (PAGE_SIZE * line_count); | |
562 | dst_offset += (PAGE_SIZE * line_count); | |
563 | } | |
564 | ||
565 | return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait, new_mem); | |
566 | } | |
567 | ||
568 | static int | |
569 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |
570 | bool no_wait, struct ttm_mem_reg *new_mem) | |
571 | { | |
572 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
573 | struct ttm_placement placement; | |
574 | struct ttm_mem_reg tmp_mem; | |
575 | int ret; | |
576 | ||
577 | placement.fpfn = placement.lpfn = 0; | |
578 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 579 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
580 | |
581 | tmp_mem = *new_mem; | |
582 | tmp_mem.mm_node = NULL; | |
583 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait); | |
584 | if (ret) | |
585 | return ret; | |
586 | ||
587 | ret = ttm_tt_bind(bo->ttm, &tmp_mem); | |
588 | if (ret) | |
589 | goto out; | |
590 | ||
a0af9add | 591 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem); |
6ee73861 BS |
592 | if (ret) |
593 | goto out; | |
594 | ||
595 | ret = ttm_bo_move_ttm(bo, evict, no_wait, new_mem); | |
596 | out: | |
597 | if (tmp_mem.mm_node) { | |
598 | spin_lock(&bo->bdev->glob->lru_lock); | |
599 | drm_mm_put_block(tmp_mem.mm_node); | |
600 | spin_unlock(&bo->bdev->glob->lru_lock); | |
601 | } | |
602 | ||
603 | return ret; | |
604 | } | |
605 | ||
606 | static int | |
607 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |
608 | bool no_wait, struct ttm_mem_reg *new_mem) | |
609 | { | |
610 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
611 | struct ttm_placement placement; | |
612 | struct ttm_mem_reg tmp_mem; | |
613 | int ret; | |
614 | ||
615 | placement.fpfn = placement.lpfn = 0; | |
616 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 617 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
618 | |
619 | tmp_mem = *new_mem; | |
620 | tmp_mem.mm_node = NULL; | |
621 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait); | |
622 | if (ret) | |
623 | return ret; | |
624 | ||
625 | ret = ttm_bo_move_ttm(bo, evict, no_wait, &tmp_mem); | |
626 | if (ret) | |
627 | goto out; | |
628 | ||
27f691a6 | 629 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem); |
6ee73861 BS |
630 | if (ret) |
631 | goto out; | |
632 | ||
633 | out: | |
634 | if (tmp_mem.mm_node) { | |
635 | spin_lock(&bo->bdev->glob->lru_lock); | |
636 | drm_mm_put_block(tmp_mem.mm_node); | |
637 | spin_unlock(&bo->bdev->glob->lru_lock); | |
638 | } | |
639 | ||
640 | return ret; | |
641 | } | |
642 | ||
643 | static int | |
a0af9add FJ |
644 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, |
645 | struct nouveau_tile_reg **new_tile) | |
6ee73861 BS |
646 | { |
647 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
6ee73861 | 648 | struct drm_device *dev = dev_priv->dev; |
a0af9add FJ |
649 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
650 | uint64_t offset; | |
6ee73861 BS |
651 | int ret; |
652 | ||
a0af9add FJ |
653 | if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) { |
654 | /* Nothing to do. */ | |
655 | *new_tile = NULL; | |
656 | return 0; | |
657 | } | |
658 | ||
659 | offset = new_mem->mm_node->start << PAGE_SHIFT; | |
6ee73861 | 660 | |
a0af9add | 661 | if (dev_priv->card_type == NV_50) { |
6ee73861 BS |
662 | ret = nv50_mem_vm_bind_linear(dev, |
663 | offset + dev_priv->vm_vram_base, | |
664 | new_mem->size, nvbo->tile_flags, | |
665 | offset); | |
666 | if (ret) | |
667 | return ret; | |
a0af9add FJ |
668 | |
669 | } else if (dev_priv->card_type >= NV_10) { | |
670 | *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size, | |
671 | nvbo->tile_mode); | |
6ee73861 BS |
672 | } |
673 | ||
a0af9add FJ |
674 | return 0; |
675 | } | |
676 | ||
677 | static void | |
678 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, | |
679 | struct nouveau_tile_reg *new_tile, | |
680 | struct nouveau_tile_reg **old_tile) | |
681 | { | |
682 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
683 | struct drm_device *dev = dev_priv->dev; | |
684 | ||
685 | if (dev_priv->card_type >= NV_10 && | |
686 | dev_priv->card_type < NV_50) { | |
687 | if (*old_tile) | |
688 | nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj); | |
689 | ||
690 | *old_tile = new_tile; | |
691 | } | |
692 | } | |
693 | ||
694 | static int | |
695 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |
696 | bool no_wait, struct ttm_mem_reg *new_mem) | |
697 | { | |
698 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
699 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
700 | struct ttm_mem_reg *old_mem = &bo->mem; | |
701 | struct nouveau_tile_reg *new_tile = NULL; | |
702 | int ret = 0; | |
703 | ||
704 | ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); | |
705 | if (ret) | |
706 | return ret; | |
707 | ||
708 | /* Software copy if the card isn't up and running yet. */ | |
0735f62e | 709 | if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE || |
a0af9add FJ |
710 | !dev_priv->channel) { |
711 | ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); | |
712 | goto out; | |
713 | } | |
6ee73861 | 714 | |
a0af9add | 715 | /* Fake bo copy. */ |
6ee73861 BS |
716 | if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
717 | BUG_ON(bo->mem.mm_node != NULL); | |
718 | bo->mem = *new_mem; | |
719 | new_mem->mm_node = NULL; | |
a0af9add | 720 | goto out; |
6ee73861 BS |
721 | } |
722 | ||
a0af9add FJ |
723 | /* Hardware assisted copy. */ |
724 | if (new_mem->mem_type == TTM_PL_SYSTEM) | |
725 | ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem); | |
726 | else if (old_mem->mem_type == TTM_PL_SYSTEM) | |
727 | ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem); | |
728 | else | |
729 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem); | |
6ee73861 | 730 | |
a0af9add FJ |
731 | if (!ret) |
732 | goto out; | |
733 | ||
734 | /* Fallback to software copy. */ | |
735 | ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); | |
736 | ||
737 | out: | |
738 | if (ret) | |
739 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); | |
740 | else | |
741 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); | |
742 | ||
743 | return ret; | |
6ee73861 BS |
744 | } |
745 | ||
746 | static int | |
747 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
748 | { | |
749 | return 0; | |
750 | } | |
751 | ||
752 | struct ttm_bo_driver nouveau_bo_driver = { | |
753 | .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry, | |
754 | .invalidate_caches = nouveau_bo_invalidate_caches, | |
755 | .init_mem_type = nouveau_bo_init_mem_type, | |
756 | .evict_flags = nouveau_bo_evict_flags, | |
757 | .move = nouveau_bo_move, | |
758 | .verify_access = nouveau_bo_verify_access, | |
759 | .sync_obj_signaled = nouveau_fence_signalled, | |
760 | .sync_obj_wait = nouveau_fence_wait, | |
761 | .sync_obj_flush = nouveau_fence_flush, | |
762 | .sync_obj_unref = nouveau_fence_unref, | |
763 | .sync_obj_ref = nouveau_fence_ref, | |
764 | }; | |
765 |