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6ee73861 BS |
1 | /* |
2 | * Copyright 2007 Dave Airlied | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * Authors: Dave Airlied <airlied@linux.ie> | |
26 | * Ben Skeggs <darktama@iinet.net.au> | |
27 | * Jeremy Kolb <jkolb@brandeis.edu> | |
28 | */ | |
29 | ||
30 | #include "drmP.h" | |
31 | ||
32 | #include "nouveau_drm.h" | |
33 | #include "nouveau_drv.h" | |
34 | #include "nouveau_dma.h" | |
35 | ||
36 | static void | |
37 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) | |
38 | { | |
39 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
a0af9add | 40 | struct drm_device *dev = dev_priv->dev; |
6ee73861 BS |
41 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
42 | ||
43 | ttm_bo_kunmap(&nvbo->kmap); | |
44 | ||
45 | if (unlikely(nvbo->gem)) | |
46 | DRM_ERROR("bo %p still attached to GEM object\n", bo); | |
47 | ||
a0af9add FJ |
48 | if (nvbo->tile) |
49 | nv10_mem_expire_tiling(dev, nvbo->tile, NULL); | |
50 | ||
6ee73861 BS |
51 | spin_lock(&dev_priv->ttm.bo_list_lock); |
52 | list_del(&nvbo->head); | |
53 | spin_unlock(&dev_priv->ttm.bo_list_lock); | |
54 | kfree(nvbo); | |
55 | } | |
56 | ||
a0af9add FJ |
57 | static void |
58 | nouveau_bo_fixup_align(struct drm_device *dev, | |
59 | uint32_t tile_mode, uint32_t tile_flags, | |
60 | int *align, int *size) | |
61 | { | |
62 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
63 | ||
64 | /* | |
65 | * Some of the tile_flags have a periodic structure of N*4096 bytes, | |
66 | * align to to that as well as the page size. Overallocate memory to | |
67 | * avoid corruption of other buffer objects. | |
68 | */ | |
69 | if (dev_priv->card_type == NV_50) { | |
70 | switch (tile_flags) { | |
71 | case 0x1800: | |
72 | case 0x2800: | |
73 | case 0x4800: | |
74 | case 0x7a00: | |
75 | if (dev_priv->chipset >= 0xA0) { | |
76 | /* This is based on high end cards with 448 bits | |
77 | * memory bus, could be different elsewhere.*/ | |
78 | *size += 6 * 28672; | |
79 | /* 8 * 28672 is the actual alignment requirement | |
80 | * but we must also align to page size. */ | |
81 | *align = 2 * 8 * 28672; | |
82 | } else if (dev_priv->chipset >= 0x90) { | |
83 | *size += 3 * 16384; | |
84 | *align = 12 * 16384; | |
85 | } else { | |
86 | *size += 3 * 8192; | |
87 | /* 12 * 8192 is the actual alignment requirement | |
88 | * but we must also align to page size. */ | |
89 | *align = 2 * 12 * 8192; | |
90 | } | |
91 | break; | |
92 | default: | |
93 | break; | |
94 | } | |
95 | ||
96 | } else { | |
97 | if (tile_mode) { | |
98 | if (dev_priv->chipset >= 0x40) { | |
99 | *align = 65536; | |
100 | *size = roundup(*size, 64 * tile_mode); | |
101 | ||
102 | } else if (dev_priv->chipset >= 0x30) { | |
103 | *align = 32768; | |
104 | *size = roundup(*size, 64 * tile_mode); | |
105 | ||
106 | } else if (dev_priv->chipset >= 0x20) { | |
107 | *align = 16384; | |
108 | *size = roundup(*size, 64 * tile_mode); | |
109 | ||
110 | } else if (dev_priv->chipset >= 0x10) { | |
111 | *align = 16384; | |
112 | *size = roundup(*size, 32 * tile_mode); | |
113 | } | |
114 | } | |
115 | } | |
116 | ||
117 | *size = ALIGN(*size, PAGE_SIZE); | |
118 | ||
119 | if (dev_priv->card_type == NV_50) { | |
120 | *size = ALIGN(*size, 65536); | |
121 | *align = max(65536, *align); | |
122 | } | |
123 | } | |
124 | ||
6ee73861 BS |
125 | int |
126 | nouveau_bo_new(struct drm_device *dev, struct nouveau_channel *chan, | |
127 | int size, int align, uint32_t flags, uint32_t tile_mode, | |
128 | uint32_t tile_flags, bool no_vm, bool mappable, | |
129 | struct nouveau_bo **pnvbo) | |
130 | { | |
131 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
132 | struct nouveau_bo *nvbo; | |
133 | int ret, n = 0; | |
134 | ||
135 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); | |
136 | if (!nvbo) | |
137 | return -ENOMEM; | |
138 | INIT_LIST_HEAD(&nvbo->head); | |
139 | INIT_LIST_HEAD(&nvbo->entry); | |
140 | nvbo->mappable = mappable; | |
141 | nvbo->no_vm = no_vm; | |
142 | nvbo->tile_mode = tile_mode; | |
143 | nvbo->tile_flags = tile_flags; | |
144 | ||
a0af9add | 145 | nouveau_bo_fixup_align(dev, tile_mode, tile_flags, &align, &size); |
6ee73861 BS |
146 | align >>= PAGE_SHIFT; |
147 | ||
6ee73861 BS |
148 | if (flags & TTM_PL_FLAG_VRAM) |
149 | nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING; | |
150 | if (flags & TTM_PL_FLAG_TT) | |
151 | nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
152 | nvbo->placement.fpfn = 0; | |
153 | nvbo->placement.lpfn = mappable ? dev_priv->fb_mappable_pages : 0; | |
154 | nvbo->placement.placement = nvbo->placements; | |
155 | nvbo->placement.busy_placement = nvbo->placements; | |
156 | nvbo->placement.num_placement = n; | |
157 | nvbo->placement.num_busy_placement = n; | |
158 | ||
159 | nvbo->channel = chan; | |
160 | nouveau_bo_placement_set(nvbo, flags); | |
161 | ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size, | |
162 | ttm_bo_type_device, &nvbo->placement, align, 0, | |
163 | false, NULL, size, nouveau_bo_del_ttm); | |
164 | nvbo->channel = NULL; | |
165 | if (ret) { | |
166 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ | |
167 | return ret; | |
168 | } | |
169 | ||
170 | spin_lock(&dev_priv->ttm.bo_list_lock); | |
171 | list_add_tail(&nvbo->head, &dev_priv->ttm.bo_list); | |
172 | spin_unlock(&dev_priv->ttm.bo_list_lock); | |
173 | *pnvbo = nvbo; | |
174 | return 0; | |
175 | } | |
176 | ||
177 | void | |
178 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t memtype) | |
179 | { | |
180 | int n = 0; | |
181 | ||
182 | if (memtype & TTM_PL_FLAG_VRAM) | |
183 | nvbo->placements[n++] = TTM_PL_FLAG_VRAM | TTM_PL_MASK_CACHING; | |
184 | if (memtype & TTM_PL_FLAG_TT) | |
185 | nvbo->placements[n++] = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
186 | if (memtype & TTM_PL_FLAG_SYSTEM) | |
187 | nvbo->placements[n++] = TTM_PL_FLAG_SYSTEM | TTM_PL_MASK_CACHING; | |
188 | nvbo->placement.placement = nvbo->placements; | |
189 | nvbo->placement.busy_placement = nvbo->placements; | |
190 | nvbo->placement.num_placement = n; | |
191 | nvbo->placement.num_busy_placement = n; | |
37cb3e08 BS |
192 | |
193 | if (nvbo->pin_refcnt) { | |
194 | while (n--) | |
195 | nvbo->placements[n] |= TTM_PL_FLAG_NO_EVICT; | |
196 | } | |
6ee73861 BS |
197 | } |
198 | ||
199 | int | |
200 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) | |
201 | { | |
202 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
203 | struct ttm_buffer_object *bo = &nvbo->bo; | |
204 | int ret, i; | |
205 | ||
206 | if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { | |
207 | NV_ERROR(nouveau_bdev(bo->bdev)->dev, | |
208 | "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo, | |
209 | 1 << bo->mem.mem_type, memtype); | |
210 | return -EINVAL; | |
211 | } | |
212 | ||
213 | if (nvbo->pin_refcnt++) | |
214 | return 0; | |
215 | ||
216 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
217 | if (ret) | |
218 | goto out; | |
219 | ||
220 | nouveau_bo_placement_set(nvbo, memtype); | |
221 | for (i = 0; i < nvbo->placement.num_placement; i++) | |
222 | nvbo->placements[i] |= TTM_PL_FLAG_NO_EVICT; | |
223 | ||
224 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false); | |
225 | if (ret == 0) { | |
226 | switch (bo->mem.mem_type) { | |
227 | case TTM_PL_VRAM: | |
228 | dev_priv->fb_aper_free -= bo->mem.size; | |
229 | break; | |
230 | case TTM_PL_TT: | |
231 | dev_priv->gart_info.aper_free -= bo->mem.size; | |
232 | break; | |
233 | default: | |
234 | break; | |
235 | } | |
236 | } | |
237 | ttm_bo_unreserve(bo); | |
238 | out: | |
239 | if (unlikely(ret)) | |
240 | nvbo->pin_refcnt--; | |
241 | return ret; | |
242 | } | |
243 | ||
244 | int | |
245 | nouveau_bo_unpin(struct nouveau_bo *nvbo) | |
246 | { | |
247 | struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev); | |
248 | struct ttm_buffer_object *bo = &nvbo->bo; | |
249 | int ret, i; | |
250 | ||
251 | if (--nvbo->pin_refcnt) | |
252 | return 0; | |
253 | ||
254 | ret = ttm_bo_reserve(bo, false, false, false, 0); | |
255 | if (ret) | |
256 | return ret; | |
257 | ||
258 | for (i = 0; i < nvbo->placement.num_placement; i++) | |
259 | nvbo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT; | |
260 | ||
261 | ret = ttm_bo_validate(bo, &nvbo->placement, false, false); | |
262 | if (ret == 0) { | |
263 | switch (bo->mem.mem_type) { | |
264 | case TTM_PL_VRAM: | |
265 | dev_priv->fb_aper_free += bo->mem.size; | |
266 | break; | |
267 | case TTM_PL_TT: | |
268 | dev_priv->gart_info.aper_free += bo->mem.size; | |
269 | break; | |
270 | default: | |
271 | break; | |
272 | } | |
273 | } | |
274 | ||
275 | ttm_bo_unreserve(bo); | |
276 | return ret; | |
277 | } | |
278 | ||
279 | int | |
280 | nouveau_bo_map(struct nouveau_bo *nvbo) | |
281 | { | |
282 | int ret; | |
283 | ||
284 | ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0); | |
285 | if (ret) | |
286 | return ret; | |
287 | ||
288 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); | |
289 | ttm_bo_unreserve(&nvbo->bo); | |
290 | return ret; | |
291 | } | |
292 | ||
293 | void | |
294 | nouveau_bo_unmap(struct nouveau_bo *nvbo) | |
295 | { | |
296 | ttm_bo_kunmap(&nvbo->kmap); | |
297 | } | |
298 | ||
299 | u16 | |
300 | nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) | |
301 | { | |
302 | bool is_iomem; | |
303 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
304 | mem = &mem[index]; | |
305 | if (is_iomem) | |
306 | return ioread16_native((void __force __iomem *)mem); | |
307 | else | |
308 | return *mem; | |
309 | } | |
310 | ||
311 | void | |
312 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) | |
313 | { | |
314 | bool is_iomem; | |
315 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
316 | mem = &mem[index]; | |
317 | if (is_iomem) | |
318 | iowrite16_native(val, (void __force __iomem *)mem); | |
319 | else | |
320 | *mem = val; | |
321 | } | |
322 | ||
323 | u32 | |
324 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) | |
325 | { | |
326 | bool is_iomem; | |
327 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
328 | mem = &mem[index]; | |
329 | if (is_iomem) | |
330 | return ioread32_native((void __force __iomem *)mem); | |
331 | else | |
332 | return *mem; | |
333 | } | |
334 | ||
335 | void | |
336 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) | |
337 | { | |
338 | bool is_iomem; | |
339 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
340 | mem = &mem[index]; | |
341 | if (is_iomem) | |
342 | iowrite32_native(val, (void __force __iomem *)mem); | |
343 | else | |
344 | *mem = val; | |
345 | } | |
346 | ||
347 | static struct ttm_backend * | |
348 | nouveau_bo_create_ttm_backend_entry(struct ttm_bo_device *bdev) | |
349 | { | |
350 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
351 | struct drm_device *dev = dev_priv->dev; | |
352 | ||
353 | switch (dev_priv->gart_info.type) { | |
b694dfb2 | 354 | #if __OS_HAS_AGP |
6ee73861 BS |
355 | case NOUVEAU_GART_AGP: |
356 | return ttm_agp_backend_init(bdev, dev->agp->bridge); | |
b694dfb2 | 357 | #endif |
6ee73861 BS |
358 | case NOUVEAU_GART_SGDMA: |
359 | return nouveau_sgdma_init_ttm(dev); | |
360 | default: | |
361 | NV_ERROR(dev, "Unknown GART type %d\n", | |
362 | dev_priv->gart_info.type); | |
363 | break; | |
364 | } | |
365 | ||
366 | return NULL; | |
367 | } | |
368 | ||
369 | static int | |
370 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
371 | { | |
372 | /* We'll do this from user space. */ | |
373 | return 0; | |
374 | } | |
375 | ||
376 | static int | |
377 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
378 | struct ttm_mem_type_manager *man) | |
379 | { | |
380 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev); | |
381 | struct drm_device *dev = dev_priv->dev; | |
382 | ||
383 | switch (type) { | |
384 | case TTM_PL_SYSTEM: | |
385 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
386 | man->available_caching = TTM_PL_MASK_CACHING; | |
387 | man->default_caching = TTM_PL_FLAG_CACHED; | |
388 | break; | |
389 | case TTM_PL_VRAM: | |
390 | man->flags = TTM_MEMTYPE_FLAG_FIXED | | |
391 | TTM_MEMTYPE_FLAG_MAPPABLE | | |
392 | TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; | |
393 | man->available_caching = TTM_PL_FLAG_UNCACHED | | |
394 | TTM_PL_FLAG_WC; | |
395 | man->default_caching = TTM_PL_FLAG_WC; | |
396 | ||
397 | man->io_addr = NULL; | |
398 | man->io_offset = drm_get_resource_start(dev, 1); | |
399 | man->io_size = drm_get_resource_len(dev, 1); | |
400 | if (man->io_size > nouveau_mem_fb_amount(dev)) | |
401 | man->io_size = nouveau_mem_fb_amount(dev); | |
402 | ||
403 | man->gpu_offset = dev_priv->vm_vram_base; | |
404 | break; | |
405 | case TTM_PL_TT: | |
406 | switch (dev_priv->gart_info.type) { | |
407 | case NOUVEAU_GART_AGP: | |
408 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | | |
409 | TTM_MEMTYPE_FLAG_NEEDS_IOREMAP; | |
410 | man->available_caching = TTM_PL_FLAG_UNCACHED; | |
411 | man->default_caching = TTM_PL_FLAG_UNCACHED; | |
412 | break; | |
413 | case NOUVEAU_GART_SGDMA: | |
414 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | | |
415 | TTM_MEMTYPE_FLAG_CMA; | |
416 | man->available_caching = TTM_PL_MASK_CACHING; | |
417 | man->default_caching = TTM_PL_FLAG_CACHED; | |
418 | break; | |
419 | default: | |
420 | NV_ERROR(dev, "Unknown GART type: %d\n", | |
421 | dev_priv->gart_info.type); | |
422 | return -EINVAL; | |
423 | } | |
424 | ||
425 | man->io_offset = dev_priv->gart_info.aper_base; | |
426 | man->io_size = dev_priv->gart_info.aper_size; | |
427 | man->io_addr = NULL; | |
428 | man->gpu_offset = dev_priv->vm_gart_base; | |
429 | break; | |
430 | default: | |
431 | NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type); | |
432 | return -EINVAL; | |
433 | } | |
434 | return 0; | |
435 | } | |
436 | ||
437 | static void | |
438 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |
439 | { | |
440 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
441 | ||
442 | switch (bo->mem.mem_type) { | |
22fbd538 FJ |
443 | case TTM_PL_VRAM: |
444 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT | | |
445 | TTM_PL_FLAG_SYSTEM); | |
446 | break; | |
6ee73861 BS |
447 | default: |
448 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM); | |
449 | break; | |
450 | } | |
22fbd538 FJ |
451 | |
452 | *pl = nvbo->placement; | |
6ee73861 BS |
453 | } |
454 | ||
455 | ||
456 | /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access | |
457 | * TTM_PL_{VRAM,TT} directly. | |
458 | */ | |
a0af9add | 459 | |
6ee73861 BS |
460 | static int |
461 | nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, | |
462 | struct nouveau_bo *nvbo, bool evict, bool no_wait, | |
463 | struct ttm_mem_reg *new_mem) | |
464 | { | |
465 | struct nouveau_fence *fence = NULL; | |
466 | int ret; | |
467 | ||
468 | ret = nouveau_fence_new(chan, &fence, true); | |
469 | if (ret) | |
470 | return ret; | |
471 | ||
472 | ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, | |
473 | evict, no_wait, new_mem); | |
474 | nouveau_fence_unref((void *)&fence); | |
475 | return ret; | |
476 | } | |
477 | ||
478 | static inline uint32_t | |
479 | nouveau_bo_mem_ctxdma(struct nouveau_bo *nvbo, struct nouveau_channel *chan, | |
480 | struct ttm_mem_reg *mem) | |
481 | { | |
482 | if (chan == nouveau_bdev(nvbo->bo.bdev)->channel) { | |
483 | if (mem->mem_type == TTM_PL_TT) | |
484 | return NvDmaGART; | |
485 | return NvDmaVRAM; | |
486 | } | |
487 | ||
488 | if (mem->mem_type == TTM_PL_TT) | |
489 | return chan->gart_handle; | |
490 | return chan->vram_handle; | |
491 | } | |
492 | ||
493 | static int | |
a0af9add FJ |
494 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, |
495 | int no_wait, struct ttm_mem_reg *new_mem) | |
6ee73861 BS |
496 | { |
497 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
498 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
a0af9add | 499 | struct ttm_mem_reg *old_mem = &bo->mem; |
6ee73861 BS |
500 | struct nouveau_channel *chan; |
501 | uint64_t src_offset, dst_offset; | |
502 | uint32_t page_count; | |
503 | int ret; | |
504 | ||
505 | chan = nvbo->channel; | |
0735f62e | 506 | if (!chan || nvbo->tile_flags || nvbo->no_vm) |
6ee73861 | 507 | chan = dev_priv->channel; |
6ee73861 BS |
508 | |
509 | src_offset = old_mem->mm_node->start << PAGE_SHIFT; | |
510 | dst_offset = new_mem->mm_node->start << PAGE_SHIFT; | |
511 | if (chan != dev_priv->channel) { | |
512 | if (old_mem->mem_type == TTM_PL_TT) | |
513 | src_offset += dev_priv->vm_gart_base; | |
514 | else | |
515 | src_offset += dev_priv->vm_vram_base; | |
516 | ||
517 | if (new_mem->mem_type == TTM_PL_TT) | |
518 | dst_offset += dev_priv->vm_gart_base; | |
519 | else | |
520 | dst_offset += dev_priv->vm_vram_base; | |
521 | } | |
522 | ||
523 | ret = RING_SPACE(chan, 3); | |
524 | if (ret) | |
525 | return ret; | |
526 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); | |
527 | OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, old_mem)); | |
528 | OUT_RING(chan, nouveau_bo_mem_ctxdma(nvbo, chan, new_mem)); | |
529 | ||
530 | if (dev_priv->card_type >= NV_50) { | |
531 | ret = RING_SPACE(chan, 4); | |
532 | if (ret) | |
533 | return ret; | |
534 | BEGIN_RING(chan, NvSubM2MF, 0x0200, 1); | |
535 | OUT_RING(chan, 1); | |
536 | BEGIN_RING(chan, NvSubM2MF, 0x021c, 1); | |
537 | OUT_RING(chan, 1); | |
538 | } | |
539 | ||
540 | page_count = new_mem->num_pages; | |
541 | while (page_count) { | |
542 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
543 | ||
544 | if (dev_priv->card_type >= NV_50) { | |
545 | ret = RING_SPACE(chan, 3); | |
546 | if (ret) | |
547 | return ret; | |
548 | BEGIN_RING(chan, NvSubM2MF, 0x0238, 2); | |
549 | OUT_RING(chan, upper_32_bits(src_offset)); | |
550 | OUT_RING(chan, upper_32_bits(dst_offset)); | |
551 | } | |
552 | ret = RING_SPACE(chan, 11); | |
553 | if (ret) | |
554 | return ret; | |
555 | BEGIN_RING(chan, NvSubM2MF, | |
556 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); | |
557 | OUT_RING(chan, lower_32_bits(src_offset)); | |
558 | OUT_RING(chan, lower_32_bits(dst_offset)); | |
559 | OUT_RING(chan, PAGE_SIZE); /* src_pitch */ | |
560 | OUT_RING(chan, PAGE_SIZE); /* dst_pitch */ | |
561 | OUT_RING(chan, PAGE_SIZE); /* line_length */ | |
562 | OUT_RING(chan, line_count); | |
563 | OUT_RING(chan, (1<<8)|(1<<0)); | |
564 | OUT_RING(chan, 0); | |
565 | BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); | |
566 | OUT_RING(chan, 0); | |
567 | ||
568 | page_count -= line_count; | |
569 | src_offset += (PAGE_SIZE * line_count); | |
570 | dst_offset += (PAGE_SIZE * line_count); | |
571 | } | |
572 | ||
573 | return nouveau_bo_move_accel_cleanup(chan, nvbo, evict, no_wait, new_mem); | |
574 | } | |
575 | ||
576 | static int | |
577 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |
578 | bool no_wait, struct ttm_mem_reg *new_mem) | |
579 | { | |
580 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
581 | struct ttm_placement placement; | |
582 | struct ttm_mem_reg tmp_mem; | |
583 | int ret; | |
584 | ||
585 | placement.fpfn = placement.lpfn = 0; | |
586 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 587 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
588 | |
589 | tmp_mem = *new_mem; | |
590 | tmp_mem.mm_node = NULL; | |
591 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait); | |
592 | if (ret) | |
593 | return ret; | |
594 | ||
595 | ret = ttm_tt_bind(bo->ttm, &tmp_mem); | |
596 | if (ret) | |
597 | goto out; | |
598 | ||
a0af9add | 599 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, &tmp_mem); |
6ee73861 BS |
600 | if (ret) |
601 | goto out; | |
602 | ||
603 | ret = ttm_bo_move_ttm(bo, evict, no_wait, new_mem); | |
604 | out: | |
605 | if (tmp_mem.mm_node) { | |
606 | spin_lock(&bo->bdev->glob->lru_lock); | |
607 | drm_mm_put_block(tmp_mem.mm_node); | |
608 | spin_unlock(&bo->bdev->glob->lru_lock); | |
609 | } | |
610 | ||
611 | return ret; | |
612 | } | |
613 | ||
614 | static int | |
615 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |
616 | bool no_wait, struct ttm_mem_reg *new_mem) | |
617 | { | |
618 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
619 | struct ttm_placement placement; | |
620 | struct ttm_mem_reg tmp_mem; | |
621 | int ret; | |
622 | ||
623 | placement.fpfn = placement.lpfn = 0; | |
624 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 625 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
626 | |
627 | tmp_mem = *new_mem; | |
628 | tmp_mem.mm_node = NULL; | |
629 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait); | |
630 | if (ret) | |
631 | return ret; | |
632 | ||
633 | ret = ttm_bo_move_ttm(bo, evict, no_wait, &tmp_mem); | |
634 | if (ret) | |
635 | goto out; | |
636 | ||
a0af9add | 637 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait, new_mem); |
6ee73861 BS |
638 | if (ret) |
639 | goto out; | |
640 | ||
641 | out: | |
642 | if (tmp_mem.mm_node) { | |
643 | spin_lock(&bo->bdev->glob->lru_lock); | |
644 | drm_mm_put_block(tmp_mem.mm_node); | |
645 | spin_unlock(&bo->bdev->glob->lru_lock); | |
646 | } | |
647 | ||
648 | return ret; | |
649 | } | |
650 | ||
651 | static int | |
a0af9add FJ |
652 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, |
653 | struct nouveau_tile_reg **new_tile) | |
6ee73861 BS |
654 | { |
655 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
6ee73861 | 656 | struct drm_device *dev = dev_priv->dev; |
a0af9add FJ |
657 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
658 | uint64_t offset; | |
6ee73861 BS |
659 | int ret; |
660 | ||
a0af9add FJ |
661 | if (nvbo->no_vm || new_mem->mem_type != TTM_PL_VRAM) { |
662 | /* Nothing to do. */ | |
663 | *new_tile = NULL; | |
664 | return 0; | |
665 | } | |
666 | ||
667 | offset = new_mem->mm_node->start << PAGE_SHIFT; | |
6ee73861 | 668 | |
a0af9add | 669 | if (dev_priv->card_type == NV_50) { |
6ee73861 BS |
670 | ret = nv50_mem_vm_bind_linear(dev, |
671 | offset + dev_priv->vm_vram_base, | |
672 | new_mem->size, nvbo->tile_flags, | |
673 | offset); | |
674 | if (ret) | |
675 | return ret; | |
a0af9add FJ |
676 | |
677 | } else if (dev_priv->card_type >= NV_10) { | |
678 | *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size, | |
679 | nvbo->tile_mode); | |
6ee73861 BS |
680 | } |
681 | ||
a0af9add FJ |
682 | return 0; |
683 | } | |
684 | ||
685 | static void | |
686 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, | |
687 | struct nouveau_tile_reg *new_tile, | |
688 | struct nouveau_tile_reg **old_tile) | |
689 | { | |
690 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
691 | struct drm_device *dev = dev_priv->dev; | |
692 | ||
693 | if (dev_priv->card_type >= NV_10 && | |
694 | dev_priv->card_type < NV_50) { | |
695 | if (*old_tile) | |
696 | nv10_mem_expire_tiling(dev, *old_tile, bo->sync_obj); | |
697 | ||
698 | *old_tile = new_tile; | |
699 | } | |
700 | } | |
701 | ||
702 | static int | |
703 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |
704 | bool no_wait, struct ttm_mem_reg *new_mem) | |
705 | { | |
706 | struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev); | |
707 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
708 | struct ttm_mem_reg *old_mem = &bo->mem; | |
709 | struct nouveau_tile_reg *new_tile = NULL; | |
710 | int ret = 0; | |
711 | ||
712 | ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); | |
713 | if (ret) | |
714 | return ret; | |
715 | ||
716 | /* Software copy if the card isn't up and running yet. */ | |
0735f62e | 717 | if (dev_priv->init_state != NOUVEAU_CARD_INIT_DONE || |
a0af9add FJ |
718 | !dev_priv->channel) { |
719 | ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); | |
720 | goto out; | |
721 | } | |
6ee73861 | 722 | |
a0af9add | 723 | /* Fake bo copy. */ |
6ee73861 BS |
724 | if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
725 | BUG_ON(bo->mem.mm_node != NULL); | |
726 | bo->mem = *new_mem; | |
727 | new_mem->mm_node = NULL; | |
a0af9add | 728 | goto out; |
6ee73861 BS |
729 | } |
730 | ||
a0af9add FJ |
731 | /* Hardware assisted copy. */ |
732 | if (new_mem->mem_type == TTM_PL_SYSTEM) | |
733 | ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait, new_mem); | |
734 | else if (old_mem->mem_type == TTM_PL_SYSTEM) | |
735 | ret = nouveau_bo_move_flips(bo, evict, intr, no_wait, new_mem); | |
736 | else | |
737 | ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait, new_mem); | |
6ee73861 | 738 | |
a0af9add FJ |
739 | if (!ret) |
740 | goto out; | |
741 | ||
742 | /* Fallback to software copy. */ | |
743 | ret = ttm_bo_move_memcpy(bo, evict, no_wait, new_mem); | |
744 | ||
745 | out: | |
746 | if (ret) | |
747 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); | |
748 | else | |
749 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); | |
750 | ||
751 | return ret; | |
6ee73861 BS |
752 | } |
753 | ||
754 | static int | |
755 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
756 | { | |
757 | return 0; | |
758 | } | |
759 | ||
760 | struct ttm_bo_driver nouveau_bo_driver = { | |
761 | .create_ttm_backend_entry = nouveau_bo_create_ttm_backend_entry, | |
762 | .invalidate_caches = nouveau_bo_invalidate_caches, | |
763 | .init_mem_type = nouveau_bo_init_mem_type, | |
764 | .evict_flags = nouveau_bo_evict_flags, | |
765 | .move = nouveau_bo_move, | |
766 | .verify_access = nouveau_bo_verify_access, | |
767 | .sync_obj_signaled = nouveau_fence_signalled, | |
768 | .sync_obj_wait = nouveau_fence_wait, | |
769 | .sync_obj_flush = nouveau_fence_flush, | |
770 | .sync_obj_unref = nouveau_fence_unref, | |
771 | .sync_obj_ref = nouveau_fence_ref, | |
772 | }; | |
773 |