drm/nouveau/fbcon: use fence for sync, rather than notifier
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
CommitLineData
6ee73861
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1/*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24/*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30#include "drmP.h"
b1e5f172 31#include "ttm/ttm_page_alloc.h"
6ee73861
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32
33#include "nouveau_drm.h"
34#include "nouveau_drv.h"
35#include "nouveau_dma.h"
f869ef88
BS
36#include "nouveau_mm.h"
37#include "nouveau_vm.h"
d375e7d5 38#include "nouveau_fence.h"
6ee73861 39
a510604d 40#include <linux/log2.h>
5a0e3ad6 41#include <linux/slab.h>
a510604d 42
6ee73861
BS
43static void
44nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
45{
46 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
a0af9add 47 struct drm_device *dev = dev_priv->dev;
6ee73861
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48 struct nouveau_bo *nvbo = nouveau_bo(bo);
49
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50 if (unlikely(nvbo->gem))
51 DRM_ERROR("bo %p still attached to GEM object\n", bo);
52
a5cf68b0 53 nv10_mem_put_tile_region(dev, nvbo->tile, NULL);
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BS
54 kfree(nvbo);
55}
56
a0af9add 57static void
db5c8e29 58nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
f91bac5b 59 int *align, int *size)
a0af9add 60{
bfd83aca 61 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
a0af9add 62
573a2a37 63 if (dev_priv->card_type < NV_50) {
bfd83aca 64 if (nvbo->tile_mode) {
a0af9add
FJ
65 if (dev_priv->chipset >= 0x40) {
66 *align = 65536;
bfd83aca 67 *size = roundup(*size, 64 * nvbo->tile_mode);
a0af9add
FJ
68
69 } else if (dev_priv->chipset >= 0x30) {
70 *align = 32768;
bfd83aca 71 *size = roundup(*size, 64 * nvbo->tile_mode);
a0af9add
FJ
72
73 } else if (dev_priv->chipset >= 0x20) {
74 *align = 16384;
bfd83aca 75 *size = roundup(*size, 64 * nvbo->tile_mode);
a0af9add
FJ
76
77 } else if (dev_priv->chipset >= 0x10) {
78 *align = 16384;
bfd83aca 79 *size = roundup(*size, 32 * nvbo->tile_mode);
a0af9add
FJ
80 }
81 }
bfd83aca 82 } else {
f91bac5b
BS
83 *size = roundup(*size, (1 << nvbo->page_shift));
84 *align = max((1 << nvbo->page_shift), *align);
a0af9add
FJ
85 }
86
1c7059e4 87 *size = roundup(*size, PAGE_SIZE);
a0af9add
FJ
88}
89
6ee73861 90int
7375c95b
BS
91nouveau_bo_new(struct drm_device *dev, int size, int align,
92 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
22b33e8e 93 struct sg_table *sg,
7375c95b 94 struct nouveau_bo **pnvbo)
6ee73861
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95{
96 struct drm_nouveau_private *dev_priv = dev->dev_private;
97 struct nouveau_bo *nvbo;
57de4ba9 98 size_t acc_size;
f91bac5b 99 int ret;
22b33e8e
DA
100 int type = ttm_bo_type_device;
101
102 if (sg)
103 type = ttm_bo_type_sg;
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104
105 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
106 if (!nvbo)
107 return -ENOMEM;
108 INIT_LIST_HEAD(&nvbo->head);
109 INIT_LIST_HEAD(&nvbo->entry);
fd2871af 110 INIT_LIST_HEAD(&nvbo->vma_list);
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111 nvbo->tile_mode = tile_mode;
112 nvbo->tile_flags = tile_flags;
699ddfd9 113 nvbo->bo.bdev = &dev_priv->ttm.bdev;
6ee73861 114
f91bac5b
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115 nvbo->page_shift = 12;
116 if (dev_priv->bar1_vm) {
117 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
118 nvbo->page_shift = dev_priv->bar1_vm->lpg_shift;
119 }
120
121 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
fd2871af
BS
122 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
123 nouveau_bo_placement_set(nvbo, flags, 0);
6ee73861 124
57de4ba9
JG
125 acc_size = ttm_bo_dma_acc_size(&dev_priv->ttm.bdev, size,
126 sizeof(struct nouveau_bo));
127
6ee73861 128 ret = ttm_bo_init(&dev_priv->ttm.bdev, &nvbo->bo, size,
22b33e8e
DA
129 type, &nvbo->placement,
130 align >> PAGE_SHIFT, 0, false, NULL, acc_size, sg,
fd2871af 131 nouveau_bo_del_ttm);
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132 if (ret) {
133 /* ttm will call nouveau_bo_del_ttm if it fails.. */
134 return ret;
135 }
136
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137 *pnvbo = nvbo;
138 return 0;
139}
140
78ad0f7b
FJ
141static void
142set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags)
143{
144 *n = 0;
145
146 if (type & TTM_PL_FLAG_VRAM)
147 pl[(*n)++] = TTM_PL_FLAG_VRAM | flags;
148 if (type & TTM_PL_FLAG_TT)
149 pl[(*n)++] = TTM_PL_FLAG_TT | flags;
150 if (type & TTM_PL_FLAG_SYSTEM)
151 pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags;
152}
153
699ddfd9
FJ
154static void
155set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
156{
157 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
812f219a 158 int vram_pages = dev_priv->vram_size >> PAGE_SHIFT;
699ddfd9
FJ
159
160 if (dev_priv->card_type == NV_10 &&
812f219a 161 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
4beb116a 162 nvbo->bo.mem.num_pages < vram_pages / 4) {
699ddfd9
FJ
163 /*
164 * Make sure that the color and depth buffers are handled
165 * by independent memory controller units. Up to a 9x
166 * speed up when alpha-blending and depth-test are enabled
167 * at the same time.
168 */
699ddfd9
FJ
169 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
170 nvbo->placement.fpfn = vram_pages / 2;
171 nvbo->placement.lpfn = ~0;
172 } else {
173 nvbo->placement.fpfn = 0;
174 nvbo->placement.lpfn = vram_pages / 2;
175 }
176 }
177}
178
6ee73861 179void
78ad0f7b 180nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
6ee73861 181{
78ad0f7b
FJ
182 struct ttm_placement *pl = &nvbo->placement;
183 uint32_t flags = TTM_PL_MASK_CACHING |
184 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
185
186 pl->placement = nvbo->placements;
187 set_placement_list(nvbo->placements, &pl->num_placement,
188 type, flags);
189
190 pl->busy_placement = nvbo->busy_placements;
191 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
192 type | busy, flags);
699ddfd9
FJ
193
194 set_placement_range(nvbo, type);
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195}
196
197int
198nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype)
199{
200 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
201 struct ttm_buffer_object *bo = &nvbo->bo;
78ad0f7b 202 int ret;
6ee73861
BS
203
204 if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) {
205 NV_ERROR(nouveau_bdev(bo->bdev)->dev,
206 "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo,
207 1 << bo->mem.mem_type, memtype);
208 return -EINVAL;
209 }
210
211 if (nvbo->pin_refcnt++)
212 return 0;
213
214 ret = ttm_bo_reserve(bo, false, false, false, 0);
215 if (ret)
216 goto out;
217
78ad0f7b 218 nouveau_bo_placement_set(nvbo, memtype, 0);
6ee73861 219
7a45d764 220 ret = nouveau_bo_validate(nvbo, false, false, false);
6ee73861
BS
221 if (ret == 0) {
222 switch (bo->mem.mem_type) {
223 case TTM_PL_VRAM:
224 dev_priv->fb_aper_free -= bo->mem.size;
225 break;
226 case TTM_PL_TT:
227 dev_priv->gart_info.aper_free -= bo->mem.size;
228 break;
229 default:
230 break;
231 }
232 }
233 ttm_bo_unreserve(bo);
234out:
235 if (unlikely(ret))
236 nvbo->pin_refcnt--;
237 return ret;
238}
239
240int
241nouveau_bo_unpin(struct nouveau_bo *nvbo)
242{
243 struct drm_nouveau_private *dev_priv = nouveau_bdev(nvbo->bo.bdev);
244 struct ttm_buffer_object *bo = &nvbo->bo;
78ad0f7b 245 int ret;
6ee73861
BS
246
247 if (--nvbo->pin_refcnt)
248 return 0;
249
250 ret = ttm_bo_reserve(bo, false, false, false, 0);
251 if (ret)
252 return ret;
253
78ad0f7b 254 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
6ee73861 255
7a45d764 256 ret = nouveau_bo_validate(nvbo, false, false, false);
6ee73861
BS
257 if (ret == 0) {
258 switch (bo->mem.mem_type) {
259 case TTM_PL_VRAM:
260 dev_priv->fb_aper_free += bo->mem.size;
261 break;
262 case TTM_PL_TT:
263 dev_priv->gart_info.aper_free += bo->mem.size;
264 break;
265 default:
266 break;
267 }
268 }
269
270 ttm_bo_unreserve(bo);
271 return ret;
272}
273
274int
275nouveau_bo_map(struct nouveau_bo *nvbo)
276{
277 int ret;
278
279 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0);
280 if (ret)
281 return ret;
282
283 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap);
284 ttm_bo_unreserve(&nvbo->bo);
285 return ret;
286}
287
288void
289nouveau_bo_unmap(struct nouveau_bo *nvbo)
290{
9d59e8a1
BS
291 if (nvbo)
292 ttm_bo_kunmap(&nvbo->kmap);
6ee73861
BS
293}
294
7a45d764
BS
295int
296nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
297 bool no_wait_reserve, bool no_wait_gpu)
298{
299 int ret;
300
301 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, interruptible,
302 no_wait_reserve, no_wait_gpu);
303 if (ret)
304 return ret;
305
306 return 0;
307}
308
6ee73861
BS
309u16
310nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index)
311{
312 bool is_iomem;
313 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
314 mem = &mem[index];
315 if (is_iomem)
316 return ioread16_native((void __force __iomem *)mem);
317 else
318 return *mem;
319}
320
321void
322nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
323{
324 bool is_iomem;
325 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
326 mem = &mem[index];
327 if (is_iomem)
328 iowrite16_native(val, (void __force __iomem *)mem);
329 else
330 *mem = val;
331}
332
333u32
334nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
335{
336 bool is_iomem;
337 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
338 mem = &mem[index];
339 if (is_iomem)
340 return ioread32_native((void __force __iomem *)mem);
341 else
342 return *mem;
343}
344
345void
346nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
347{
348 bool is_iomem;
349 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
350 mem = &mem[index];
351 if (is_iomem)
352 iowrite32_native(val, (void __force __iomem *)mem);
353 else
354 *mem = val;
355}
356
649bf3ca
JG
357static struct ttm_tt *
358nouveau_ttm_tt_create(struct ttm_bo_device *bdev,
359 unsigned long size, uint32_t page_flags,
360 struct page *dummy_read_page)
6ee73861
BS
361{
362 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
363 struct drm_device *dev = dev_priv->dev;
364
365 switch (dev_priv->gart_info.type) {
b694dfb2 366#if __OS_HAS_AGP
6ee73861 367 case NOUVEAU_GART_AGP:
649bf3ca
JG
368 return ttm_agp_tt_create(bdev, dev->agp->bridge,
369 size, page_flags, dummy_read_page);
b694dfb2 370#endif
58e6c7a9
BS
371 case NOUVEAU_GART_PDMA:
372 case NOUVEAU_GART_HW:
649bf3ca
JG
373 return nouveau_sgdma_create_ttm(bdev, size, page_flags,
374 dummy_read_page);
6ee73861
BS
375 default:
376 NV_ERROR(dev, "Unknown GART type %d\n",
377 dev_priv->gart_info.type);
378 break;
379 }
380
381 return NULL;
382}
383
384static int
385nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
386{
387 /* We'll do this from user space. */
388 return 0;
389}
390
391static int
392nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
393 struct ttm_mem_type_manager *man)
394{
395 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
396 struct drm_device *dev = dev_priv->dev;
397
398 switch (type) {
399 case TTM_PL_SYSTEM:
400 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
401 man->available_caching = TTM_PL_MASK_CACHING;
402 man->default_caching = TTM_PL_FLAG_CACHED;
403 break;
404 case TTM_PL_VRAM:
8984e046 405 if (dev_priv->card_type >= NV_50) {
573a2a37 406 man->func = &nouveau_vram_manager;
f869ef88
BS
407 man->io_reserve_fastpath = false;
408 man->use_io_reserve_lru = true;
409 } else {
573a2a37 410 man->func = &ttm_bo_manager_func;
f869ef88 411 }
6ee73861 412 man->flags = TTM_MEMTYPE_FLAG_FIXED |
f32f02fd 413 TTM_MEMTYPE_FLAG_MAPPABLE;
6ee73861
BS
414 man->available_caching = TTM_PL_FLAG_UNCACHED |
415 TTM_PL_FLAG_WC;
416 man->default_caching = TTM_PL_FLAG_WC;
6ee73861
BS
417 break;
418 case TTM_PL_TT:
26c0c9e3
BS
419 if (dev_priv->card_type >= NV_50)
420 man->func = &nouveau_gart_manager;
421 else
422 man->func = &ttm_bo_manager_func;
6ee73861
BS
423 switch (dev_priv->gart_info.type) {
424 case NOUVEAU_GART_AGP:
f32f02fd 425 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
a3d487ea
FJ
426 man->available_caching = TTM_PL_FLAG_UNCACHED |
427 TTM_PL_FLAG_WC;
428 man->default_caching = TTM_PL_FLAG_WC;
6ee73861 429 break;
58e6c7a9
BS
430 case NOUVEAU_GART_PDMA:
431 case NOUVEAU_GART_HW:
6ee73861
BS
432 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
433 TTM_MEMTYPE_FLAG_CMA;
434 man->available_caching = TTM_PL_MASK_CACHING;
435 man->default_caching = TTM_PL_FLAG_CACHED;
436 break;
437 default:
438 NV_ERROR(dev, "Unknown GART type: %d\n",
439 dev_priv->gart_info.type);
440 return -EINVAL;
441 }
6ee73861
BS
442 break;
443 default:
444 NV_ERROR(dev, "Unsupported memory type %u\n", (unsigned)type);
445 return -EINVAL;
446 }
447 return 0;
448}
449
450static void
451nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
452{
453 struct nouveau_bo *nvbo = nouveau_bo(bo);
454
455 switch (bo->mem.mem_type) {
22fbd538 456 case TTM_PL_VRAM:
78ad0f7b
FJ
457 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
458 TTM_PL_FLAG_SYSTEM);
22fbd538 459 break;
6ee73861 460 default:
78ad0f7b 461 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
6ee73861
BS
462 break;
463 }
22fbd538
FJ
464
465 *pl = nvbo->placement;
6ee73861
BS
466}
467
468
469/* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access
470 * TTM_PL_{VRAM,TT} directly.
471 */
a0af9add 472
6ee73861
BS
473static int
474nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan,
9d87fa21
JG
475 struct nouveau_bo *nvbo, bool evict,
476 bool no_wait_reserve, bool no_wait_gpu,
6ee73861
BS
477 struct ttm_mem_reg *new_mem)
478{
479 struct nouveau_fence *fence = NULL;
480 int ret;
481
d375e7d5 482 ret = nouveau_fence_new(chan, &fence);
6ee73861
BS
483 if (ret)
484 return ret;
485
64798817 486 ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, NULL, evict,
311ab694 487 no_wait_reserve, no_wait_gpu, new_mem);
382d62e5 488 nouveau_fence_unref(&fence);
6ee73861
BS
489 return ret;
490}
491
c6b7e895
BS
492static int
493nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
494 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
495{
496 struct nouveau_mem *node = old_mem->mm_node;
497 int ret = RING_SPACE(chan, 10);
498 if (ret == 0) {
6d597027 499 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
c6b7e895
BS
500 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
501 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
502 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
503 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
504 OUT_RING (chan, PAGE_SIZE);
505 OUT_RING (chan, PAGE_SIZE);
506 OUT_RING (chan, PAGE_SIZE);
507 OUT_RING (chan, new_mem->num_pages);
6d597027 508 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
c6b7e895
BS
509 }
510 return ret;
511}
512
183720b8
BS
513static int
514nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
515 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
516{
d2f96666
BS
517 struct nouveau_mem *node = old_mem->mm_node;
518 u64 src_offset = node->vma[0].offset;
519 u64 dst_offset = node->vma[1].offset;
183720b8
BS
520 u32 page_count = new_mem->num_pages;
521 int ret;
522
183720b8
BS
523 page_count = new_mem->num_pages;
524 while (page_count) {
525 int line_count = (page_count > 2047) ? 2047 : page_count;
526
527 ret = RING_SPACE(chan, 12);
528 if (ret)
529 return ret;
530
6d597027 531 BEGIN_NVC0(chan, NvSubM2MF, 0x0238, 2);
183720b8
BS
532 OUT_RING (chan, upper_32_bits(dst_offset));
533 OUT_RING (chan, lower_32_bits(dst_offset));
6d597027 534 BEGIN_NVC0(chan, NvSubM2MF, 0x030c, 6);
183720b8
BS
535 OUT_RING (chan, upper_32_bits(src_offset));
536 OUT_RING (chan, lower_32_bits(src_offset));
537 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
538 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
539 OUT_RING (chan, PAGE_SIZE); /* line_length */
540 OUT_RING (chan, line_count);
6d597027 541 BEGIN_NVC0(chan, NvSubM2MF, 0x0300, 1);
183720b8
BS
542 OUT_RING (chan, 0x00100110);
543
544 page_count -= line_count;
545 src_offset += (PAGE_SIZE * line_count);
546 dst_offset += (PAGE_SIZE * line_count);
547 }
548
549 return 0;
550}
551
6ee73861 552static int
f1ab0cc9
BS
553nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
554 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
6ee73861 555{
d2f96666 556 struct nouveau_mem *node = old_mem->mm_node;
f1ab0cc9
BS
557 struct nouveau_bo *nvbo = nouveau_bo(bo);
558 u64 length = (new_mem->num_pages << PAGE_SHIFT);
d2f96666
BS
559 u64 src_offset = node->vma[0].offset;
560 u64 dst_offset = node->vma[1].offset;
6ee73861
BS
561 int ret;
562
f1ab0cc9
BS
563 while (length) {
564 u32 amount, stride, height;
565
5220b3c1
BS
566 amount = min(length, (u64)(4 * 1024 * 1024));
567 stride = 16 * 4;
f1ab0cc9
BS
568 height = amount / stride;
569
f13b3263
FJ
570 if (new_mem->mem_type == TTM_PL_VRAM &&
571 nouveau_bo_tile_layout(nvbo)) {
f1ab0cc9
BS
572 ret = RING_SPACE(chan, 8);
573 if (ret)
574 return ret;
575
6d597027 576 BEGIN_NV04(chan, NvSubM2MF, 0x0200, 7);
f1ab0cc9 577 OUT_RING (chan, 0);
5220b3c1 578 OUT_RING (chan, 0);
f1ab0cc9
BS
579 OUT_RING (chan, stride);
580 OUT_RING (chan, height);
581 OUT_RING (chan, 1);
582 OUT_RING (chan, 0);
583 OUT_RING (chan, 0);
584 } else {
585 ret = RING_SPACE(chan, 2);
586 if (ret)
587 return ret;
588
6d597027 589 BEGIN_NV04(chan, NvSubM2MF, 0x0200, 1);
f1ab0cc9
BS
590 OUT_RING (chan, 1);
591 }
f13b3263
FJ
592 if (old_mem->mem_type == TTM_PL_VRAM &&
593 nouveau_bo_tile_layout(nvbo)) {
f1ab0cc9
BS
594 ret = RING_SPACE(chan, 8);
595 if (ret)
596 return ret;
597
6d597027 598 BEGIN_NV04(chan, NvSubM2MF, 0x021c, 7);
f1ab0cc9 599 OUT_RING (chan, 0);
5220b3c1 600 OUT_RING (chan, 0);
f1ab0cc9
BS
601 OUT_RING (chan, stride);
602 OUT_RING (chan, height);
603 OUT_RING (chan, 1);
604 OUT_RING (chan, 0);
605 OUT_RING (chan, 0);
606 } else {
607 ret = RING_SPACE(chan, 2);
608 if (ret)
609 return ret;
610
6d597027 611 BEGIN_NV04(chan, NvSubM2MF, 0x021c, 1);
f1ab0cc9
BS
612 OUT_RING (chan, 1);
613 }
614
615 ret = RING_SPACE(chan, 14);
6ee73861
BS
616 if (ret)
617 return ret;
f1ab0cc9 618
6d597027 619 BEGIN_NV04(chan, NvSubM2MF, 0x0238, 2);
f1ab0cc9
BS
620 OUT_RING (chan, upper_32_bits(src_offset));
621 OUT_RING (chan, upper_32_bits(dst_offset));
6d597027 622 BEGIN_NV04(chan, NvSubM2MF, 0x030c, 8);
f1ab0cc9
BS
623 OUT_RING (chan, lower_32_bits(src_offset));
624 OUT_RING (chan, lower_32_bits(dst_offset));
625 OUT_RING (chan, stride);
626 OUT_RING (chan, stride);
627 OUT_RING (chan, stride);
628 OUT_RING (chan, height);
629 OUT_RING (chan, 0x00000101);
630 OUT_RING (chan, 0x00000000);
6d597027 631 BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
f1ab0cc9
BS
632 OUT_RING (chan, 0);
633
634 length -= amount;
635 src_offset += amount;
636 dst_offset += amount;
6ee73861
BS
637 }
638
f1ab0cc9
BS
639 return 0;
640}
641
a6704788
BS
642static inline uint32_t
643nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
644 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
645{
646 if (mem->mem_type == TTM_PL_TT)
647 return chan->gart_handle;
648 return chan->vram_handle;
649}
650
f1ab0cc9
BS
651static int
652nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
653 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
654{
d961db75
BS
655 u32 src_offset = old_mem->start << PAGE_SHIFT;
656 u32 dst_offset = new_mem->start << PAGE_SHIFT;
f1ab0cc9
BS
657 u32 page_count = new_mem->num_pages;
658 int ret;
659
660 ret = RING_SPACE(chan, 3);
661 if (ret)
662 return ret;
663
6d597027 664 BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
f1ab0cc9
BS
665 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
666 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
667
6ee73861
BS
668 page_count = new_mem->num_pages;
669 while (page_count) {
670 int line_count = (page_count > 2047) ? 2047 : page_count;
671
6ee73861
BS
672 ret = RING_SPACE(chan, 11);
673 if (ret)
674 return ret;
f1ab0cc9 675
6d597027 676 BEGIN_NV04(chan, NvSubM2MF,
6ee73861 677 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
f1ab0cc9
BS
678 OUT_RING (chan, src_offset);
679 OUT_RING (chan, dst_offset);
680 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
681 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
682 OUT_RING (chan, PAGE_SIZE); /* line_length */
683 OUT_RING (chan, line_count);
684 OUT_RING (chan, 0x00000101);
685 OUT_RING (chan, 0x00000000);
6d597027 686 BEGIN_NV04(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
f1ab0cc9 687 OUT_RING (chan, 0);
6ee73861
BS
688
689 page_count -= line_count;
690 src_offset += (PAGE_SIZE * line_count);
691 dst_offset += (PAGE_SIZE * line_count);
692 }
693
f1ab0cc9
BS
694 return 0;
695}
696
d2f96666
BS
697static int
698nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo,
699 struct ttm_mem_reg *mem, struct nouveau_vma *vma)
700{
701 struct nouveau_mem *node = mem->mm_node;
702 int ret;
703
704 ret = nouveau_vm_get(chan->vm, mem->num_pages << PAGE_SHIFT,
705 node->page_shift, NV_MEM_ACCESS_RO, vma);
706 if (ret)
707 return ret;
708
709 if (mem->mem_type == TTM_PL_VRAM)
710 nouveau_vm_map(vma, node);
711 else
f7b24c42 712 nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node);
d2f96666
BS
713
714 return 0;
715}
716
f1ab0cc9
BS
717static int
718nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
719 bool no_wait_reserve, bool no_wait_gpu,
720 struct ttm_mem_reg *new_mem)
721{
722 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
accf9496 723 struct nouveau_channel *chan = chan = dev_priv->channel;
f1ab0cc9 724 struct nouveau_bo *nvbo = nouveau_bo(bo);
3425df48 725 struct ttm_mem_reg *old_mem = &bo->mem;
f1ab0cc9
BS
726 int ret;
727
accf9496 728 mutex_lock_nested(&chan->mutex, NOUVEAU_KCHANNEL_MUTEX);
f1ab0cc9 729
d2f96666
BS
730 /* create temporary vmas for the transfer and attach them to the
731 * old nouveau_mem node, these will get cleaned up after ttm has
732 * destroyed the ttm_mem_reg
3425df48 733 */
26c0c9e3 734 if (dev_priv->card_type >= NV_50) {
d5f42394 735 struct nouveau_mem *node = old_mem->mm_node;
3425df48 736
d2f96666
BS
737 ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]);
738 if (ret)
739 goto out;
740
741 ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]);
742 if (ret)
743 goto out;
3425df48
BS
744 }
745
f1ab0cc9
BS
746 if (dev_priv->card_type < NV_50)
747 ret = nv04_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
748 else
183720b8 749 if (dev_priv->card_type < NV_C0)
f1ab0cc9 750 ret = nv50_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
183720b8 751 else
c6b7e895 752 if (dev_priv->card_type < NV_E0)
183720b8 753 ret = nvc0_bo_move_m2mf(chan, bo, &bo->mem, new_mem);
c6b7e895
BS
754 else
755 ret = nve0_bo_move_copy(chan, bo, &bo->mem, new_mem);
6a6b73f2
BS
756 if (ret == 0) {
757 ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict,
758 no_wait_reserve,
759 no_wait_gpu, new_mem);
760 }
f1ab0cc9 761
3425df48 762out:
accf9496 763 mutex_unlock(&chan->mutex);
6a6b73f2 764 return ret;
6ee73861
BS
765}
766
767static int
768nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
9d87fa21
JG
769 bool no_wait_reserve, bool no_wait_gpu,
770 struct ttm_mem_reg *new_mem)
6ee73861
BS
771{
772 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
773 struct ttm_placement placement;
774 struct ttm_mem_reg tmp_mem;
775 int ret;
776
777 placement.fpfn = placement.lpfn = 0;
778 placement.num_placement = placement.num_busy_placement = 1;
77e2b5ed 779 placement.placement = placement.busy_placement = &placement_memtype;
6ee73861
BS
780
781 tmp_mem = *new_mem;
782 tmp_mem.mm_node = NULL;
9d87fa21 783 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
6ee73861
BS
784 if (ret)
785 return ret;
786
787 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
788 if (ret)
789 goto out;
790
9d87fa21 791 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, &tmp_mem);
6ee73861
BS
792 if (ret)
793 goto out;
794
b8884da6 795 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861 796out:
42311ff9 797 ttm_bo_mem_put(bo, &tmp_mem);
6ee73861
BS
798 return ret;
799}
800
801static int
802nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
9d87fa21
JG
803 bool no_wait_reserve, bool no_wait_gpu,
804 struct ttm_mem_reg *new_mem)
6ee73861
BS
805{
806 u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING;
807 struct ttm_placement placement;
808 struct ttm_mem_reg tmp_mem;
809 int ret;
810
811 placement.fpfn = placement.lpfn = 0;
812 placement.num_placement = placement.num_busy_placement = 1;
77e2b5ed 813 placement.placement = placement.busy_placement = &placement_memtype;
6ee73861
BS
814
815 tmp_mem = *new_mem;
816 tmp_mem.mm_node = NULL;
9d87fa21 817 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_reserve, no_wait_gpu);
6ee73861
BS
818 if (ret)
819 return ret;
820
b8884da6 821 ret = ttm_bo_move_ttm(bo, true, no_wait_reserve, no_wait_gpu, &tmp_mem);
6ee73861
BS
822 if (ret)
823 goto out;
824
b8884da6 825 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861
BS
826 if (ret)
827 goto out;
828
829out:
42311ff9 830 ttm_bo_mem_put(bo, &tmp_mem);
6ee73861
BS
831 return ret;
832}
833
a4154bbf
BS
834static void
835nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
836{
a4154bbf 837 struct nouveau_bo *nvbo = nouveau_bo(bo);
fd2871af
BS
838 struct nouveau_vma *vma;
839
9f1feed2
BS
840 /* ttm can now (stupidly) pass the driver bos it didn't create... */
841 if (bo->destroy != nouveau_bo_del_ttm)
842 return;
843
fd2871af 844 list_for_each_entry(vma, &nvbo->vma_list, head) {
dc97b340 845 if (new_mem && new_mem->mem_type == TTM_PL_VRAM) {
fd2871af
BS
846 nouveau_vm_map(vma, new_mem->mm_node);
847 } else
dc97b340 848 if (new_mem && new_mem->mem_type == TTM_PL_TT &&
fd2871af 849 nvbo->page_shift == vma->vm->spg_shift) {
22b33e8e
DA
850 if (((struct nouveau_mem *)new_mem->mm_node)->sg)
851 nouveau_vm_map_sg_table(vma, 0, new_mem->
852 num_pages << PAGE_SHIFT,
853 new_mem->mm_node);
854 else
855 nouveau_vm_map_sg(vma, 0, new_mem->
856 num_pages << PAGE_SHIFT,
857 new_mem->mm_node);
fd2871af
BS
858 } else {
859 nouveau_vm_unmap(vma);
860 }
a4154bbf
BS
861 }
862}
863
6ee73861 864static int
a0af9add
FJ
865nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
866 struct nouveau_tile_reg **new_tile)
6ee73861
BS
867{
868 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
6ee73861 869 struct drm_device *dev = dev_priv->dev;
a0af9add 870 struct nouveau_bo *nvbo = nouveau_bo(bo);
a4154bbf 871 u64 offset = new_mem->start << PAGE_SHIFT;
6ee73861 872
a4154bbf
BS
873 *new_tile = NULL;
874 if (new_mem->mem_type != TTM_PL_VRAM)
a0af9add 875 return 0;
a0af9add 876
a4154bbf 877 if (dev_priv->card_type >= NV_10) {
a0af9add 878 *new_tile = nv10_mem_set_tiling(dev, offset, new_mem->size,
a5cf68b0
FJ
879 nvbo->tile_mode,
880 nvbo->tile_flags);
6ee73861
BS
881 }
882
a0af9add
FJ
883 return 0;
884}
885
886static void
887nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
888 struct nouveau_tile_reg *new_tile,
889 struct nouveau_tile_reg **old_tile)
890{
891 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
892 struct drm_device *dev = dev_priv->dev;
893
a4154bbf
BS
894 nv10_mem_put_tile_region(dev, *old_tile, bo->sync_obj);
895 *old_tile = new_tile;
a0af9add
FJ
896}
897
898static int
899nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
9d87fa21
JG
900 bool no_wait_reserve, bool no_wait_gpu,
901 struct ttm_mem_reg *new_mem)
a0af9add
FJ
902{
903 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
904 struct nouveau_bo *nvbo = nouveau_bo(bo);
905 struct ttm_mem_reg *old_mem = &bo->mem;
906 struct nouveau_tile_reg *new_tile = NULL;
907 int ret = 0;
908
a4154bbf
BS
909 if (dev_priv->card_type < NV_50) {
910 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
911 if (ret)
912 return ret;
913 }
a0af9add 914
a0af9add 915 /* Fake bo copy. */
6ee73861
BS
916 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
917 BUG_ON(bo->mem.mm_node != NULL);
918 bo->mem = *new_mem;
919 new_mem->mm_node = NULL;
a0af9add 920 goto out;
6ee73861
BS
921 }
922
b8a6a804 923 /* Software copy if the card isn't up and running yet. */
183720b8 924 if (!dev_priv->channel) {
b8a6a804
BS
925 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
926 goto out;
927 }
928
a0af9add
FJ
929 /* Hardware assisted copy. */
930 if (new_mem->mem_type == TTM_PL_SYSTEM)
9d87fa21 931 ret = nouveau_bo_move_flipd(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
a0af9add 932 else if (old_mem->mem_type == TTM_PL_SYSTEM)
9d87fa21 933 ret = nouveau_bo_move_flips(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
a0af9add 934 else
9d87fa21 935 ret = nouveau_bo_move_m2mf(bo, evict, intr, no_wait_reserve, no_wait_gpu, new_mem);
6ee73861 936
a0af9add
FJ
937 if (!ret)
938 goto out;
939
940 /* Fallback to software copy. */
9d87fa21 941 ret = ttm_bo_move_memcpy(bo, evict, no_wait_reserve, no_wait_gpu, new_mem);
a0af9add
FJ
942
943out:
a4154bbf
BS
944 if (dev_priv->card_type < NV_50) {
945 if (ret)
946 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
947 else
948 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
949 }
a0af9add
FJ
950
951 return ret;
6ee73861
BS
952}
953
954static int
955nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
956{
957 return 0;
958}
959
f32f02fd
JG
960static int
961nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
962{
963 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
964 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
965 struct drm_device *dev = dev_priv->dev;
f869ef88 966 int ret;
f32f02fd
JG
967
968 mem->bus.addr = NULL;
969 mem->bus.offset = 0;
970 mem->bus.size = mem->num_pages << PAGE_SHIFT;
971 mem->bus.base = 0;
972 mem->bus.is_iomem = false;
973 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
974 return -EINVAL;
975 switch (mem->mem_type) {
976 case TTM_PL_SYSTEM:
977 /* System memory */
978 return 0;
979 case TTM_PL_TT:
980#if __OS_HAS_AGP
981 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
d961db75 982 mem->bus.offset = mem->start << PAGE_SHIFT;
f32f02fd
JG
983 mem->bus.base = dev_priv->gart_info.aper_base;
984 mem->bus.is_iomem = true;
985 }
986#endif
987 break;
988 case TTM_PL_VRAM:
f869ef88 989 {
d5f42394 990 struct nouveau_mem *node = mem->mm_node;
8984e046 991 u8 page_shift;
f869ef88
BS
992
993 if (!dev_priv->bar1_vm) {
994 mem->bus.offset = mem->start << PAGE_SHIFT;
995 mem->bus.base = pci_resource_start(dev->pdev, 1);
996 mem->bus.is_iomem = true;
997 break;
998 }
999
2e9733ff 1000 if (dev_priv->card_type >= NV_C0)
d5f42394 1001 page_shift = node->page_shift;
8984e046
BS
1002 else
1003 page_shift = 12;
1004
4c74eb7f 1005 ret = nouveau_vm_get(dev_priv->bar1_vm, mem->bus.size,
8984e046 1006 page_shift, NV_MEM_ACCESS_RW,
d5f42394 1007 &node->bar_vma);
f869ef88
BS
1008 if (ret)
1009 return ret;
1010
d5f42394 1011 nouveau_vm_map(&node->bar_vma, node);
f869ef88 1012 if (ret) {
d5f42394 1013 nouveau_vm_put(&node->bar_vma);
f869ef88
BS
1014 return ret;
1015 }
1016
d5f42394 1017 mem->bus.offset = node->bar_vma.offset;
8984e046
BS
1018 if (dev_priv->card_type == NV_50) /*XXX*/
1019 mem->bus.offset -= 0x0020000000ULL;
01d73a69 1020 mem->bus.base = pci_resource_start(dev->pdev, 1);
f32f02fd 1021 mem->bus.is_iomem = true;
f869ef88 1022 }
f32f02fd
JG
1023 break;
1024 default:
1025 return -EINVAL;
1026 }
1027 return 0;
1028}
1029
1030static void
1031nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1032{
f869ef88 1033 struct drm_nouveau_private *dev_priv = nouveau_bdev(bdev);
d5f42394 1034 struct nouveau_mem *node = mem->mm_node;
f869ef88
BS
1035
1036 if (!dev_priv->bar1_vm || mem->mem_type != TTM_PL_VRAM)
1037 return;
1038
d5f42394 1039 if (!node->bar_vma.node)
f869ef88
BS
1040 return;
1041
d5f42394
BS
1042 nouveau_vm_unmap(&node->bar_vma);
1043 nouveau_vm_put(&node->bar_vma);
f32f02fd
JG
1044}
1045
1046static int
1047nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1048{
e1429b4c
BS
1049 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
1050 struct nouveau_bo *nvbo = nouveau_bo(bo);
1051
1052 /* as long as the bo isn't in vram, and isn't tiled, we've got
1053 * nothing to do here.
1054 */
1055 if (bo->mem.mem_type != TTM_PL_VRAM) {
f13b3263
FJ
1056 if (dev_priv->card_type < NV_50 ||
1057 !nouveau_bo_tile_layout(nvbo))
e1429b4c
BS
1058 return 0;
1059 }
1060
1061 /* make sure bo is in mappable vram */
d961db75 1062 if (bo->mem.start + bo->mem.num_pages < dev_priv->fb_mappable_pages)
e1429b4c
BS
1063 return 0;
1064
1065
1066 nvbo->placement.fpfn = 0;
1067 nvbo->placement.lpfn = dev_priv->fb_mappable_pages;
c284815d 1068 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
7a45d764 1069 return nouveau_bo_validate(nvbo, false, true, false);
f32f02fd
JG
1070}
1071
3230cfc3
KRW
1072static int
1073nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1074{
8e7e7052 1075 struct ttm_dma_tt *ttm_dma = (void *)ttm;
3230cfc3
KRW
1076 struct drm_nouveau_private *dev_priv;
1077 struct drm_device *dev;
1078 unsigned i;
1079 int r;
22b33e8e 1080 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
3230cfc3
KRW
1081
1082 if (ttm->state != tt_unpopulated)
1083 return 0;
1084
22b33e8e
DA
1085 if (slave && ttm->sg) {
1086 /* make userspace faulting work */
1087 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1088 ttm_dma->dma_address, ttm->num_pages);
1089 ttm->state = tt_unbound;
1090 return 0;
1091 }
1092
3230cfc3
KRW
1093 dev_priv = nouveau_bdev(ttm->bdev);
1094 dev = dev_priv->dev;
1095
dea7e0ac
JG
1096#if __OS_HAS_AGP
1097 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1098 return ttm_agp_tt_populate(ttm);
1099 }
1100#endif
1101
3230cfc3
KRW
1102#ifdef CONFIG_SWIOTLB
1103 if (swiotlb_nr_tbl()) {
8e7e7052 1104 return ttm_dma_populate((void *)ttm, dev->dev);
3230cfc3
KRW
1105 }
1106#endif
1107
1108 r = ttm_pool_populate(ttm);
1109 if (r) {
1110 return r;
1111 }
1112
1113 for (i = 0; i < ttm->num_pages; i++) {
8e7e7052 1114 ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i],
3230cfc3
KRW
1115 0, PAGE_SIZE,
1116 PCI_DMA_BIDIRECTIONAL);
8e7e7052 1117 if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) {
3230cfc3 1118 while (--i) {
8e7e7052 1119 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
3230cfc3 1120 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
8e7e7052 1121 ttm_dma->dma_address[i] = 0;
3230cfc3
KRW
1122 }
1123 ttm_pool_unpopulate(ttm);
1124 return -EFAULT;
1125 }
1126 }
1127 return 0;
1128}
1129
1130static void
1131nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1132{
8e7e7052 1133 struct ttm_dma_tt *ttm_dma = (void *)ttm;
3230cfc3
KRW
1134 struct drm_nouveau_private *dev_priv;
1135 struct drm_device *dev;
1136 unsigned i;
22b33e8e
DA
1137 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1138
1139 if (slave)
1140 return;
3230cfc3
KRW
1141
1142 dev_priv = nouveau_bdev(ttm->bdev);
1143 dev = dev_priv->dev;
1144
dea7e0ac
JG
1145#if __OS_HAS_AGP
1146 if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) {
1147 ttm_agp_tt_unpopulate(ttm);
1148 return;
1149 }
1150#endif
1151
3230cfc3
KRW
1152#ifdef CONFIG_SWIOTLB
1153 if (swiotlb_nr_tbl()) {
8e7e7052 1154 ttm_dma_unpopulate((void *)ttm, dev->dev);
3230cfc3
KRW
1155 return;
1156 }
1157#endif
1158
1159 for (i = 0; i < ttm->num_pages; i++) {
8e7e7052
JG
1160 if (ttm_dma->dma_address[i]) {
1161 pci_unmap_page(dev->pdev, ttm_dma->dma_address[i],
3230cfc3
KRW
1162 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
1163 }
1164 }
1165
1166 ttm_pool_unpopulate(ttm);
1167}
1168
875ac34a
BS
1169void
1170nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence)
1171{
1172 struct nouveau_fence *old_fence = NULL;
1173
1174 if (likely(fence))
1175 nouveau_fence_ref(fence);
1176
1177 spin_lock(&nvbo->bo.bdev->fence_lock);
1178 old_fence = nvbo->bo.sync_obj;
1179 nvbo->bo.sync_obj = fence;
1180 spin_unlock(&nvbo->bo.bdev->fence_lock);
1181
1182 nouveau_fence_unref(&old_fence);
1183}
1184
1185static void
1186nouveau_bo_fence_unref(void **sync_obj)
1187{
1188 nouveau_fence_unref((struct nouveau_fence **)sync_obj);
1189}
1190
1191static void *
1192nouveau_bo_fence_ref(void *sync_obj)
1193{
1194 return nouveau_fence_ref(sync_obj);
1195}
1196
1197static bool
1198nouveau_bo_fence_signalled(void *sync_obj, void *sync_arg)
1199{
d375e7d5 1200 return nouveau_fence_done(sync_obj);
875ac34a
BS
1201}
1202
1203static int
1204nouveau_bo_fence_wait(void *sync_obj, void *sync_arg, bool lazy, bool intr)
1205{
1206 return nouveau_fence_wait(sync_obj, lazy, intr);
1207}
1208
1209static int
1210nouveau_bo_fence_flush(void *sync_obj, void *sync_arg)
1211{
1212 return 0;
1213}
1214
6ee73861 1215struct ttm_bo_driver nouveau_bo_driver = {
649bf3ca 1216 .ttm_tt_create = &nouveau_ttm_tt_create,
3230cfc3
KRW
1217 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1218 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
6ee73861
BS
1219 .invalidate_caches = nouveau_bo_invalidate_caches,
1220 .init_mem_type = nouveau_bo_init_mem_type,
1221 .evict_flags = nouveau_bo_evict_flags,
a4154bbf 1222 .move_notify = nouveau_bo_move_ntfy,
6ee73861
BS
1223 .move = nouveau_bo_move,
1224 .verify_access = nouveau_bo_verify_access,
875ac34a
BS
1225 .sync_obj_signaled = nouveau_bo_fence_signalled,
1226 .sync_obj_wait = nouveau_bo_fence_wait,
1227 .sync_obj_flush = nouveau_bo_fence_flush,
1228 .sync_obj_unref = nouveau_bo_fence_unref,
1229 .sync_obj_ref = nouveau_bo_fence_ref,
f32f02fd
JG
1230 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1231 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1232 .io_mem_free = &nouveau_ttm_io_mem_free,
6ee73861
BS
1233};
1234
fd2871af
BS
1235struct nouveau_vma *
1236nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1237{
1238 struct nouveau_vma *vma;
1239 list_for_each_entry(vma, &nvbo->vma_list, head) {
1240 if (vma->vm == vm)
1241 return vma;
1242 }
1243
1244 return NULL;
1245}
1246
1247int
1248nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1249 struct nouveau_vma *vma)
1250{
1251 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1252 struct nouveau_mem *node = nvbo->bo.mem.mm_node;
1253 int ret;
1254
1255 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1256 NV_MEM_ACCESS_RW, vma);
1257 if (ret)
1258 return ret;
1259
1260 if (nvbo->bo.mem.mem_type == TTM_PL_VRAM)
1261 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
22b33e8e
DA
1262 else if (nvbo->bo.mem.mem_type == TTM_PL_TT) {
1263 if (node->sg)
1264 nouveau_vm_map_sg_table(vma, 0, size, node);
1265 else
1266 nouveau_vm_map_sg(vma, 0, size, node);
1267 }
fd2871af
BS
1268
1269 list_add_tail(&vma->head, &nvbo->vma_list);
2fd3db6f 1270 vma->refcount = 1;
fd2871af
BS
1271 return 0;
1272}
1273
1274void
1275nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1276{
1277 if (vma->node) {
1278 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) {
1279 spin_lock(&nvbo->bo.bdev->fence_lock);
1717c0e2 1280 ttm_bo_wait(&nvbo->bo, false, false, false);
fd2871af
BS
1281 spin_unlock(&nvbo->bo.bdev->fence_lock);
1282 nouveau_vm_unmap(vma);
1283 }
1284
1285 nouveau_vm_put(vma);
1286 list_del(&vma->head);
1287 }
1288}
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