Commit | Line | Data |
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6ee73861 BS |
1 | /* |
2 | * Copyright 2007 Dave Airlied | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | /* | |
25 | * Authors: Dave Airlied <airlied@linux.ie> | |
26 | * Ben Skeggs <darktama@iinet.net.au> | |
27 | * Jeremy Kolb <jkolb@brandeis.edu> | |
28 | */ | |
29 | ||
ebb945a9 | 30 | #include <core/engine.h> |
3e2b756b | 31 | #include <linux/swiotlb.h> |
6ee73861 | 32 | |
ebb945a9 BS |
33 | #include <subdev/fb.h> |
34 | #include <subdev/vm.h> | |
35 | #include <subdev/bar.h> | |
36 | ||
37 | #include "nouveau_drm.h" | |
6ee73861 | 38 | #include "nouveau_dma.h" |
d375e7d5 | 39 | #include "nouveau_fence.h" |
6ee73861 | 40 | |
ebb945a9 BS |
41 | #include "nouveau_bo.h" |
42 | #include "nouveau_ttm.h" | |
43 | #include "nouveau_gem.h" | |
a510604d | 44 | |
bc9e7b9a BS |
45 | /* |
46 | * NV10-NV40 tiling helpers | |
47 | */ | |
48 | ||
49 | static void | |
ebb945a9 BS |
50 | nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg, |
51 | u32 addr, u32 size, u32 pitch, u32 flags) | |
bc9e7b9a | 52 | { |
77145f1c | 53 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 BS |
54 | int i = reg - drm->tile.reg; |
55 | struct nouveau_fb *pfb = nouveau_fb(drm->device); | |
56 | struct nouveau_fb_tile *tile = &pfb->tile.region[i]; | |
57 | struct nouveau_engine *engine; | |
bc9e7b9a | 58 | |
ebb945a9 | 59 | nouveau_fence_unref(®->fence); |
bc9e7b9a BS |
60 | |
61 | if (tile->pitch) | |
ebb945a9 | 62 | pfb->tile.fini(pfb, i, tile); |
bc9e7b9a BS |
63 | |
64 | if (pitch) | |
ebb945a9 | 65 | pfb->tile.init(pfb, i, addr, size, pitch, flags, tile); |
bc9e7b9a | 66 | |
ebb945a9 | 67 | pfb->tile.prog(pfb, i, tile); |
bc9e7b9a | 68 | |
ebb945a9 BS |
69 | if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR))) |
70 | engine->tile_prog(engine, i); | |
71 | if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG))) | |
72 | engine->tile_prog(engine, i); | |
bc9e7b9a BS |
73 | } |
74 | ||
ebb945a9 | 75 | static struct nouveau_drm_tile * |
bc9e7b9a BS |
76 | nv10_bo_get_tile_region(struct drm_device *dev, int i) |
77 | { | |
77145f1c | 78 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 | 79 | struct nouveau_drm_tile *tile = &drm->tile.reg[i]; |
bc9e7b9a | 80 | |
ebb945a9 | 81 | spin_lock(&drm->tile.lock); |
bc9e7b9a BS |
82 | |
83 | if (!tile->used && | |
84 | (!tile->fence || nouveau_fence_done(tile->fence))) | |
85 | tile->used = true; | |
86 | else | |
87 | tile = NULL; | |
88 | ||
ebb945a9 | 89 | spin_unlock(&drm->tile.lock); |
bc9e7b9a BS |
90 | return tile; |
91 | } | |
92 | ||
93 | static void | |
ebb945a9 BS |
94 | nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile, |
95 | struct nouveau_fence *fence) | |
bc9e7b9a | 96 | { |
77145f1c | 97 | struct nouveau_drm *drm = nouveau_drm(dev); |
bc9e7b9a BS |
98 | |
99 | if (tile) { | |
ebb945a9 | 100 | spin_lock(&drm->tile.lock); |
bc9e7b9a BS |
101 | if (fence) { |
102 | /* Mark it as pending. */ | |
103 | tile->fence = fence; | |
104 | nouveau_fence_ref(fence); | |
105 | } | |
106 | ||
107 | tile->used = false; | |
ebb945a9 | 108 | spin_unlock(&drm->tile.lock); |
bc9e7b9a BS |
109 | } |
110 | } | |
111 | ||
ebb945a9 BS |
112 | static struct nouveau_drm_tile * |
113 | nv10_bo_set_tiling(struct drm_device *dev, u32 addr, | |
114 | u32 size, u32 pitch, u32 flags) | |
bc9e7b9a | 115 | { |
77145f1c | 116 | struct nouveau_drm *drm = nouveau_drm(dev); |
ebb945a9 BS |
117 | struct nouveau_fb *pfb = nouveau_fb(drm->device); |
118 | struct nouveau_drm_tile *tile, *found = NULL; | |
bc9e7b9a BS |
119 | int i; |
120 | ||
ebb945a9 | 121 | for (i = 0; i < pfb->tile.regions; i++) { |
bc9e7b9a BS |
122 | tile = nv10_bo_get_tile_region(dev, i); |
123 | ||
124 | if (pitch && !found) { | |
125 | found = tile; | |
126 | continue; | |
127 | ||
ebb945a9 | 128 | } else if (tile && pfb->tile.region[i].pitch) { |
bc9e7b9a BS |
129 | /* Kill an unused tile region. */ |
130 | nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0); | |
131 | } | |
132 | ||
133 | nv10_bo_put_tile_region(dev, tile, NULL); | |
134 | } | |
135 | ||
136 | if (found) | |
137 | nv10_bo_update_tile_region(dev, found, addr, size, | |
138 | pitch, flags); | |
139 | return found; | |
140 | } | |
141 | ||
6ee73861 BS |
142 | static void |
143 | nouveau_bo_del_ttm(struct ttm_buffer_object *bo) | |
144 | { | |
ebb945a9 BS |
145 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
146 | struct drm_device *dev = drm->dev; | |
6ee73861 BS |
147 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
148 | ||
6ee73861 BS |
149 | if (unlikely(nvbo->gem)) |
150 | DRM_ERROR("bo %p still attached to GEM object\n", bo); | |
4f385599 | 151 | WARN_ON(nvbo->pin_refcnt > 0); |
bc9e7b9a | 152 | nv10_bo_put_tile_region(dev, nvbo->tile, NULL); |
6ee73861 BS |
153 | kfree(nvbo); |
154 | } | |
155 | ||
a0af9add | 156 | static void |
db5c8e29 | 157 | nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags, |
f91bac5b | 158 | int *align, int *size) |
a0af9add | 159 | { |
ebb945a9 BS |
160 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
161 | struct nouveau_device *device = nv_device(drm->device); | |
a0af9add | 162 | |
ebb945a9 | 163 | if (device->card_type < NV_50) { |
bfd83aca | 164 | if (nvbo->tile_mode) { |
ebb945a9 | 165 | if (device->chipset >= 0x40) { |
a0af9add | 166 | *align = 65536; |
bfd83aca | 167 | *size = roundup(*size, 64 * nvbo->tile_mode); |
a0af9add | 168 | |
ebb945a9 | 169 | } else if (device->chipset >= 0x30) { |
a0af9add | 170 | *align = 32768; |
bfd83aca | 171 | *size = roundup(*size, 64 * nvbo->tile_mode); |
a0af9add | 172 | |
ebb945a9 | 173 | } else if (device->chipset >= 0x20) { |
a0af9add | 174 | *align = 16384; |
bfd83aca | 175 | *size = roundup(*size, 64 * nvbo->tile_mode); |
a0af9add | 176 | |
ebb945a9 | 177 | } else if (device->chipset >= 0x10) { |
a0af9add | 178 | *align = 16384; |
bfd83aca | 179 | *size = roundup(*size, 32 * nvbo->tile_mode); |
a0af9add FJ |
180 | } |
181 | } | |
bfd83aca | 182 | } else { |
f91bac5b BS |
183 | *size = roundup(*size, (1 << nvbo->page_shift)); |
184 | *align = max((1 << nvbo->page_shift), *align); | |
a0af9add FJ |
185 | } |
186 | ||
1c7059e4 | 187 | *size = roundup(*size, PAGE_SIZE); |
a0af9add FJ |
188 | } |
189 | ||
6ee73861 | 190 | int |
7375c95b BS |
191 | nouveau_bo_new(struct drm_device *dev, int size, int align, |
192 | uint32_t flags, uint32_t tile_mode, uint32_t tile_flags, | |
22b33e8e | 193 | struct sg_table *sg, |
7375c95b | 194 | struct nouveau_bo **pnvbo) |
6ee73861 | 195 | { |
77145f1c | 196 | struct nouveau_drm *drm = nouveau_drm(dev); |
6ee73861 | 197 | struct nouveau_bo *nvbo; |
57de4ba9 | 198 | size_t acc_size; |
f91bac5b | 199 | int ret; |
22b33e8e | 200 | int type = ttm_bo_type_device; |
0108bc80 ML |
201 | int max_size = INT_MAX & ~((1 << drm->client.base.vm->vmm->lpg_shift) - 1); |
202 | ||
203 | if (size <= 0 || size > max_size) { | |
204 | nv_warn(drm, "skipped size %x\n", (u32)size); | |
205 | return -EINVAL; | |
206 | } | |
22b33e8e DA |
207 | |
208 | if (sg) | |
209 | type = ttm_bo_type_sg; | |
6ee73861 BS |
210 | |
211 | nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL); | |
212 | if (!nvbo) | |
213 | return -ENOMEM; | |
214 | INIT_LIST_HEAD(&nvbo->head); | |
215 | INIT_LIST_HEAD(&nvbo->entry); | |
fd2871af | 216 | INIT_LIST_HEAD(&nvbo->vma_list); |
6ee73861 BS |
217 | nvbo->tile_mode = tile_mode; |
218 | nvbo->tile_flags = tile_flags; | |
ebb945a9 | 219 | nvbo->bo.bdev = &drm->ttm.bdev; |
6ee73861 | 220 | |
f91bac5b | 221 | nvbo->page_shift = 12; |
ebb945a9 | 222 | if (drm->client.base.vm) { |
f91bac5b | 223 | if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024) |
ebb945a9 | 224 | nvbo->page_shift = drm->client.base.vm->vmm->lpg_shift; |
f91bac5b BS |
225 | } |
226 | ||
227 | nouveau_bo_fixup_align(nvbo, flags, &align, &size); | |
fd2871af BS |
228 | nvbo->bo.mem.num_pages = size >> PAGE_SHIFT; |
229 | nouveau_bo_placement_set(nvbo, flags, 0); | |
6ee73861 | 230 | |
ebb945a9 | 231 | acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size, |
57de4ba9 JG |
232 | sizeof(struct nouveau_bo)); |
233 | ||
ebb945a9 | 234 | ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size, |
22b33e8e | 235 | type, &nvbo->placement, |
0b91c4a1 | 236 | align >> PAGE_SHIFT, false, NULL, acc_size, sg, |
fd2871af | 237 | nouveau_bo_del_ttm); |
6ee73861 BS |
238 | if (ret) { |
239 | /* ttm will call nouveau_bo_del_ttm if it fails.. */ | |
240 | return ret; | |
241 | } | |
242 | ||
6ee73861 BS |
243 | *pnvbo = nvbo; |
244 | return 0; | |
245 | } | |
246 | ||
78ad0f7b FJ |
247 | static void |
248 | set_placement_list(uint32_t *pl, unsigned *n, uint32_t type, uint32_t flags) | |
249 | { | |
250 | *n = 0; | |
251 | ||
252 | if (type & TTM_PL_FLAG_VRAM) | |
253 | pl[(*n)++] = TTM_PL_FLAG_VRAM | flags; | |
254 | if (type & TTM_PL_FLAG_TT) | |
255 | pl[(*n)++] = TTM_PL_FLAG_TT | flags; | |
256 | if (type & TTM_PL_FLAG_SYSTEM) | |
257 | pl[(*n)++] = TTM_PL_FLAG_SYSTEM | flags; | |
258 | } | |
259 | ||
699ddfd9 FJ |
260 | static void |
261 | set_placement_range(struct nouveau_bo *nvbo, uint32_t type) | |
262 | { | |
ebb945a9 BS |
263 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
264 | struct nouveau_fb *pfb = nouveau_fb(drm->device); | |
dceef5d8 | 265 | u32 vram_pages = pfb->ram->size >> PAGE_SHIFT; |
699ddfd9 | 266 | |
ebb945a9 | 267 | if (nv_device(drm->device)->card_type == NV_10 && |
812f219a | 268 | nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) && |
4beb116a | 269 | nvbo->bo.mem.num_pages < vram_pages / 4) { |
699ddfd9 FJ |
270 | /* |
271 | * Make sure that the color and depth buffers are handled | |
272 | * by independent memory controller units. Up to a 9x | |
273 | * speed up when alpha-blending and depth-test are enabled | |
274 | * at the same time. | |
275 | */ | |
699ddfd9 FJ |
276 | if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) { |
277 | nvbo->placement.fpfn = vram_pages / 2; | |
278 | nvbo->placement.lpfn = ~0; | |
279 | } else { | |
280 | nvbo->placement.fpfn = 0; | |
281 | nvbo->placement.lpfn = vram_pages / 2; | |
282 | } | |
283 | } | |
284 | } | |
285 | ||
6ee73861 | 286 | void |
78ad0f7b | 287 | nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy) |
6ee73861 | 288 | { |
78ad0f7b FJ |
289 | struct ttm_placement *pl = &nvbo->placement; |
290 | uint32_t flags = TTM_PL_MASK_CACHING | | |
291 | (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0); | |
292 | ||
293 | pl->placement = nvbo->placements; | |
294 | set_placement_list(nvbo->placements, &pl->num_placement, | |
295 | type, flags); | |
296 | ||
297 | pl->busy_placement = nvbo->busy_placements; | |
298 | set_placement_list(nvbo->busy_placements, &pl->num_busy_placement, | |
299 | type | busy, flags); | |
699ddfd9 FJ |
300 | |
301 | set_placement_range(nvbo, type); | |
6ee73861 BS |
302 | } |
303 | ||
304 | int | |
305 | nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype) | |
306 | { | |
ebb945a9 | 307 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
6ee73861 | 308 | struct ttm_buffer_object *bo = &nvbo->bo; |
78ad0f7b | 309 | int ret; |
6ee73861 | 310 | |
0ae6d7bc DV |
311 | ret = ttm_bo_reserve(bo, false, false, false, 0); |
312 | if (ret) | |
313 | goto out; | |
314 | ||
6ee73861 | 315 | if (nvbo->pin_refcnt && !(memtype & (1 << bo->mem.mem_type))) { |
ebb945a9 | 316 | NV_ERROR(drm, "bo %p pinned elsewhere: 0x%08x vs 0x%08x\n", bo, |
6ee73861 | 317 | 1 << bo->mem.mem_type, memtype); |
0ae6d7bc DV |
318 | ret = -EINVAL; |
319 | goto out; | |
6ee73861 BS |
320 | } |
321 | ||
322 | if (nvbo->pin_refcnt++) | |
6ee73861 BS |
323 | goto out; |
324 | ||
78ad0f7b | 325 | nouveau_bo_placement_set(nvbo, memtype, 0); |
6ee73861 | 326 | |
97a875cb | 327 | ret = nouveau_bo_validate(nvbo, false, false); |
6ee73861 BS |
328 | if (ret == 0) { |
329 | switch (bo->mem.mem_type) { | |
330 | case TTM_PL_VRAM: | |
ebb945a9 | 331 | drm->gem.vram_available -= bo->mem.size; |
6ee73861 BS |
332 | break; |
333 | case TTM_PL_TT: | |
ebb945a9 | 334 | drm->gem.gart_available -= bo->mem.size; |
6ee73861 BS |
335 | break; |
336 | default: | |
337 | break; | |
338 | } | |
339 | } | |
6ee73861 | 340 | out: |
0ae6d7bc | 341 | ttm_bo_unreserve(bo); |
6ee73861 BS |
342 | return ret; |
343 | } | |
344 | ||
345 | int | |
346 | nouveau_bo_unpin(struct nouveau_bo *nvbo) | |
347 | { | |
ebb945a9 | 348 | struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev); |
6ee73861 | 349 | struct ttm_buffer_object *bo = &nvbo->bo; |
4f385599 | 350 | int ret, ref; |
6ee73861 | 351 | |
6ee73861 BS |
352 | ret = ttm_bo_reserve(bo, false, false, false, 0); |
353 | if (ret) | |
354 | return ret; | |
355 | ||
4f385599 ML |
356 | ref = --nvbo->pin_refcnt; |
357 | WARN_ON_ONCE(ref < 0); | |
358 | if (ref) | |
0ae6d7bc DV |
359 | goto out; |
360 | ||
78ad0f7b | 361 | nouveau_bo_placement_set(nvbo, bo->mem.placement, 0); |
6ee73861 | 362 | |
97a875cb | 363 | ret = nouveau_bo_validate(nvbo, false, false); |
6ee73861 BS |
364 | if (ret == 0) { |
365 | switch (bo->mem.mem_type) { | |
366 | case TTM_PL_VRAM: | |
ebb945a9 | 367 | drm->gem.vram_available += bo->mem.size; |
6ee73861 BS |
368 | break; |
369 | case TTM_PL_TT: | |
ebb945a9 | 370 | drm->gem.gart_available += bo->mem.size; |
6ee73861 BS |
371 | break; |
372 | default: | |
373 | break; | |
374 | } | |
375 | } | |
376 | ||
0ae6d7bc | 377 | out: |
6ee73861 BS |
378 | ttm_bo_unreserve(bo); |
379 | return ret; | |
380 | } | |
381 | ||
382 | int | |
383 | nouveau_bo_map(struct nouveau_bo *nvbo) | |
384 | { | |
385 | int ret; | |
386 | ||
387 | ret = ttm_bo_reserve(&nvbo->bo, false, false, false, 0); | |
388 | if (ret) | |
389 | return ret; | |
390 | ||
391 | ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages, &nvbo->kmap); | |
392 | ttm_bo_unreserve(&nvbo->bo); | |
393 | return ret; | |
394 | } | |
395 | ||
396 | void | |
397 | nouveau_bo_unmap(struct nouveau_bo *nvbo) | |
398 | { | |
9d59e8a1 BS |
399 | if (nvbo) |
400 | ttm_bo_kunmap(&nvbo->kmap); | |
6ee73861 BS |
401 | } |
402 | ||
7a45d764 BS |
403 | int |
404 | nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible, | |
97a875cb | 405 | bool no_wait_gpu) |
7a45d764 BS |
406 | { |
407 | int ret; | |
408 | ||
97a875cb ML |
409 | ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement, |
410 | interruptible, no_wait_gpu); | |
7a45d764 BS |
411 | if (ret) |
412 | return ret; | |
413 | ||
414 | return 0; | |
415 | } | |
416 | ||
6ee73861 BS |
417 | u16 |
418 | nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index) | |
419 | { | |
420 | bool is_iomem; | |
421 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
422 | mem = &mem[index]; | |
423 | if (is_iomem) | |
424 | return ioread16_native((void __force __iomem *)mem); | |
425 | else | |
426 | return *mem; | |
427 | } | |
428 | ||
429 | void | |
430 | nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val) | |
431 | { | |
432 | bool is_iomem; | |
433 | u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
434 | mem = &mem[index]; | |
435 | if (is_iomem) | |
436 | iowrite16_native(val, (void __force __iomem *)mem); | |
437 | else | |
438 | *mem = val; | |
439 | } | |
440 | ||
441 | u32 | |
442 | nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index) | |
443 | { | |
444 | bool is_iomem; | |
445 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
446 | mem = &mem[index]; | |
447 | if (is_iomem) | |
448 | return ioread32_native((void __force __iomem *)mem); | |
449 | else | |
450 | return *mem; | |
451 | } | |
452 | ||
453 | void | |
454 | nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val) | |
455 | { | |
456 | bool is_iomem; | |
457 | u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem); | |
458 | mem = &mem[index]; | |
459 | if (is_iomem) | |
460 | iowrite32_native(val, (void __force __iomem *)mem); | |
461 | else | |
462 | *mem = val; | |
463 | } | |
464 | ||
649bf3ca | 465 | static struct ttm_tt * |
ebb945a9 BS |
466 | nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size, |
467 | uint32_t page_flags, struct page *dummy_read) | |
6ee73861 | 468 | { |
df1b4b91 | 469 | #if __OS_HAS_AGP |
ebb945a9 BS |
470 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
471 | struct drm_device *dev = drm->dev; | |
6ee73861 | 472 | |
ebb945a9 BS |
473 | if (drm->agp.stat == ENABLED) { |
474 | return ttm_agp_tt_create(bdev, dev->agp->bridge, size, | |
475 | page_flags, dummy_read); | |
6ee73861 | 476 | } |
df1b4b91 | 477 | #endif |
6ee73861 | 478 | |
ebb945a9 | 479 | return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read); |
6ee73861 BS |
480 | } |
481 | ||
482 | static int | |
483 | nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags) | |
484 | { | |
485 | /* We'll do this from user space. */ | |
486 | return 0; | |
487 | } | |
488 | ||
489 | static int | |
490 | nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type, | |
491 | struct ttm_mem_type_manager *man) | |
492 | { | |
ebb945a9 | 493 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
6ee73861 BS |
494 | |
495 | switch (type) { | |
496 | case TTM_PL_SYSTEM: | |
497 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; | |
498 | man->available_caching = TTM_PL_MASK_CACHING; | |
499 | man->default_caching = TTM_PL_FLAG_CACHED; | |
500 | break; | |
501 | case TTM_PL_VRAM: | |
ebb945a9 | 502 | if (nv_device(drm->device)->card_type >= NV_50) { |
573a2a37 | 503 | man->func = &nouveau_vram_manager; |
f869ef88 BS |
504 | man->io_reserve_fastpath = false; |
505 | man->use_io_reserve_lru = true; | |
506 | } else { | |
573a2a37 | 507 | man->func = &ttm_bo_manager_func; |
f869ef88 | 508 | } |
6ee73861 | 509 | man->flags = TTM_MEMTYPE_FLAG_FIXED | |
f32f02fd | 510 | TTM_MEMTYPE_FLAG_MAPPABLE; |
6ee73861 BS |
511 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
512 | TTM_PL_FLAG_WC; | |
513 | man->default_caching = TTM_PL_FLAG_WC; | |
6ee73861 BS |
514 | break; |
515 | case TTM_PL_TT: | |
ebb945a9 | 516 | if (nv_device(drm->device)->card_type >= NV_50) |
26c0c9e3 | 517 | man->func = &nouveau_gart_manager; |
3863c9bc | 518 | else |
ebb945a9 | 519 | if (drm->agp.stat != ENABLED) |
3863c9bc | 520 | man->func = &nv04_gart_manager; |
26c0c9e3 BS |
521 | else |
522 | man->func = &ttm_bo_manager_func; | |
ebb945a9 BS |
523 | |
524 | if (drm->agp.stat == ENABLED) { | |
f32f02fd | 525 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE; |
a3d487ea FJ |
526 | man->available_caching = TTM_PL_FLAG_UNCACHED | |
527 | TTM_PL_FLAG_WC; | |
528 | man->default_caching = TTM_PL_FLAG_WC; | |
ebb945a9 | 529 | } else { |
6ee73861 BS |
530 | man->flags = TTM_MEMTYPE_FLAG_MAPPABLE | |
531 | TTM_MEMTYPE_FLAG_CMA; | |
532 | man->available_caching = TTM_PL_MASK_CACHING; | |
533 | man->default_caching = TTM_PL_FLAG_CACHED; | |
6ee73861 | 534 | } |
ebb945a9 | 535 | |
6ee73861 BS |
536 | break; |
537 | default: | |
6ee73861 BS |
538 | return -EINVAL; |
539 | } | |
540 | return 0; | |
541 | } | |
542 | ||
543 | static void | |
544 | nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl) | |
545 | { | |
546 | struct nouveau_bo *nvbo = nouveau_bo(bo); | |
547 | ||
548 | switch (bo->mem.mem_type) { | |
22fbd538 | 549 | case TTM_PL_VRAM: |
78ad0f7b FJ |
550 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, |
551 | TTM_PL_FLAG_SYSTEM); | |
22fbd538 | 552 | break; |
6ee73861 | 553 | default: |
78ad0f7b | 554 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0); |
6ee73861 BS |
555 | break; |
556 | } | |
22fbd538 FJ |
557 | |
558 | *pl = nvbo->placement; | |
6ee73861 BS |
559 | } |
560 | ||
561 | ||
562 | /* GPU-assisted copy using NV_MEMORY_TO_MEMORY_FORMAT, can access | |
563 | * TTM_PL_{VRAM,TT} directly. | |
564 | */ | |
a0af9add | 565 | |
6ee73861 BS |
566 | static int |
567 | nouveau_bo_move_accel_cleanup(struct nouveau_channel *chan, | |
9d87fa21 | 568 | struct nouveau_bo *nvbo, bool evict, |
97a875cb | 569 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
6ee73861 BS |
570 | { |
571 | struct nouveau_fence *fence = NULL; | |
572 | int ret; | |
573 | ||
264ce192 | 574 | ret = nouveau_fence_new(chan, false, &fence); |
6ee73861 BS |
575 | if (ret) |
576 | return ret; | |
577 | ||
b03640b1 | 578 | ret = ttm_bo_move_accel_cleanup(&nvbo->bo, fence, evict, |
97a875cb | 579 | no_wait_gpu, new_mem); |
382d62e5 | 580 | nouveau_fence_unref(&fence); |
6ee73861 BS |
581 | return ret; |
582 | } | |
583 | ||
49981046 BS |
584 | static int |
585 | nve0_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
586 | { | |
587 | int ret = RING_SPACE(chan, 2); | |
588 | if (ret == 0) { | |
589 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); | |
00fc6f6f | 590 | OUT_RING (chan, handle & 0x0000ffff); |
49981046 BS |
591 | FIRE_RING (chan); |
592 | } | |
593 | return ret; | |
594 | } | |
595 | ||
c6b7e895 BS |
596 | static int |
597 | nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
598 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
599 | { | |
600 | struct nouveau_mem *node = old_mem->mm_node; | |
601 | int ret = RING_SPACE(chan, 10); | |
602 | if (ret == 0) { | |
6d597027 | 603 | BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8); |
c6b7e895 BS |
604 | OUT_RING (chan, upper_32_bits(node->vma[0].offset)); |
605 | OUT_RING (chan, lower_32_bits(node->vma[0].offset)); | |
606 | OUT_RING (chan, upper_32_bits(node->vma[1].offset)); | |
607 | OUT_RING (chan, lower_32_bits(node->vma[1].offset)); | |
608 | OUT_RING (chan, PAGE_SIZE); | |
609 | OUT_RING (chan, PAGE_SIZE); | |
610 | OUT_RING (chan, PAGE_SIZE); | |
611 | OUT_RING (chan, new_mem->num_pages); | |
6d597027 | 612 | BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386); |
c6b7e895 BS |
613 | } |
614 | return ret; | |
615 | } | |
616 | ||
d1b167e1 BS |
617 | static int |
618 | nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
619 | { | |
620 | int ret = RING_SPACE(chan, 2); | |
621 | if (ret == 0) { | |
622 | BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1); | |
623 | OUT_RING (chan, handle); | |
624 | } | |
625 | return ret; | |
626 | } | |
627 | ||
1a46098e BS |
628 | static int |
629 | nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
630 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
631 | { | |
632 | struct nouveau_mem *node = old_mem->mm_node; | |
633 | u64 src_offset = node->vma[0].offset; | |
634 | u64 dst_offset = node->vma[1].offset; | |
635 | u32 page_count = new_mem->num_pages; | |
636 | int ret; | |
637 | ||
638 | page_count = new_mem->num_pages; | |
639 | while (page_count) { | |
640 | int line_count = (page_count > 8191) ? 8191 : page_count; | |
641 | ||
642 | ret = RING_SPACE(chan, 11); | |
643 | if (ret) | |
644 | return ret; | |
645 | ||
646 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8); | |
647 | OUT_RING (chan, upper_32_bits(src_offset)); | |
648 | OUT_RING (chan, lower_32_bits(src_offset)); | |
649 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
650 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
651 | OUT_RING (chan, PAGE_SIZE); | |
652 | OUT_RING (chan, PAGE_SIZE); | |
653 | OUT_RING (chan, PAGE_SIZE); | |
654 | OUT_RING (chan, line_count); | |
655 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); | |
656 | OUT_RING (chan, 0x00000110); | |
657 | ||
658 | page_count -= line_count; | |
659 | src_offset += (PAGE_SIZE * line_count); | |
660 | dst_offset += (PAGE_SIZE * line_count); | |
661 | } | |
662 | ||
663 | return 0; | |
664 | } | |
665 | ||
183720b8 BS |
666 | static int |
667 | nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
668 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
669 | { | |
d2f96666 BS |
670 | struct nouveau_mem *node = old_mem->mm_node; |
671 | u64 src_offset = node->vma[0].offset; | |
672 | u64 dst_offset = node->vma[1].offset; | |
183720b8 BS |
673 | u32 page_count = new_mem->num_pages; |
674 | int ret; | |
675 | ||
183720b8 BS |
676 | page_count = new_mem->num_pages; |
677 | while (page_count) { | |
678 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
679 | ||
680 | ret = RING_SPACE(chan, 12); | |
681 | if (ret) | |
682 | return ret; | |
683 | ||
d1b167e1 | 684 | BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2); |
183720b8 BS |
685 | OUT_RING (chan, upper_32_bits(dst_offset)); |
686 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
d1b167e1 | 687 | BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6); |
183720b8 BS |
688 | OUT_RING (chan, upper_32_bits(src_offset)); |
689 | OUT_RING (chan, lower_32_bits(src_offset)); | |
690 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
691 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
692 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
693 | OUT_RING (chan, line_count); | |
d1b167e1 | 694 | BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1); |
183720b8 BS |
695 | OUT_RING (chan, 0x00100110); |
696 | ||
697 | page_count -= line_count; | |
698 | src_offset += (PAGE_SIZE * line_count); | |
699 | dst_offset += (PAGE_SIZE * line_count); | |
700 | } | |
701 | ||
702 | return 0; | |
703 | } | |
704 | ||
fdf53241 BS |
705 | static int |
706 | nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
707 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
708 | { | |
709 | struct nouveau_mem *node = old_mem->mm_node; | |
710 | u64 src_offset = node->vma[0].offset; | |
711 | u64 dst_offset = node->vma[1].offset; | |
712 | u32 page_count = new_mem->num_pages; | |
713 | int ret; | |
714 | ||
715 | page_count = new_mem->num_pages; | |
716 | while (page_count) { | |
717 | int line_count = (page_count > 8191) ? 8191 : page_count; | |
718 | ||
719 | ret = RING_SPACE(chan, 11); | |
720 | if (ret) | |
721 | return ret; | |
722 | ||
723 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); | |
724 | OUT_RING (chan, upper_32_bits(src_offset)); | |
725 | OUT_RING (chan, lower_32_bits(src_offset)); | |
726 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
727 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
728 | OUT_RING (chan, PAGE_SIZE); | |
729 | OUT_RING (chan, PAGE_SIZE); | |
730 | OUT_RING (chan, PAGE_SIZE); | |
731 | OUT_RING (chan, line_count); | |
732 | BEGIN_NV04(chan, NvSubCopy, 0x0300, 1); | |
733 | OUT_RING (chan, 0x00000110); | |
734 | ||
735 | page_count -= line_count; | |
736 | src_offset += (PAGE_SIZE * line_count); | |
737 | dst_offset += (PAGE_SIZE * line_count); | |
738 | } | |
739 | ||
740 | return 0; | |
741 | } | |
742 | ||
5490e5df BS |
743 | static int |
744 | nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
745 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
746 | { | |
747 | struct nouveau_mem *node = old_mem->mm_node; | |
748 | int ret = RING_SPACE(chan, 7); | |
749 | if (ret == 0) { | |
750 | BEGIN_NV04(chan, NvSubCopy, 0x0320, 6); | |
751 | OUT_RING (chan, upper_32_bits(node->vma[0].offset)); | |
752 | OUT_RING (chan, lower_32_bits(node->vma[0].offset)); | |
753 | OUT_RING (chan, upper_32_bits(node->vma[1].offset)); | |
754 | OUT_RING (chan, lower_32_bits(node->vma[1].offset)); | |
755 | OUT_RING (chan, 0x00000000 /* COPY */); | |
756 | OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); | |
757 | } | |
758 | return ret; | |
759 | } | |
760 | ||
4c193d25 BS |
761 | static int |
762 | nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
763 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
764 | { | |
765 | struct nouveau_mem *node = old_mem->mm_node; | |
766 | int ret = RING_SPACE(chan, 7); | |
767 | if (ret == 0) { | |
768 | BEGIN_NV04(chan, NvSubCopy, 0x0304, 6); | |
769 | OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT); | |
770 | OUT_RING (chan, upper_32_bits(node->vma[0].offset)); | |
771 | OUT_RING (chan, lower_32_bits(node->vma[0].offset)); | |
772 | OUT_RING (chan, upper_32_bits(node->vma[1].offset)); | |
773 | OUT_RING (chan, lower_32_bits(node->vma[1].offset)); | |
774 | OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */); | |
775 | } | |
776 | return ret; | |
777 | } | |
778 | ||
d1b167e1 BS |
779 | static int |
780 | nv50_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
781 | { | |
ebb945a9 | 782 | int ret = RING_SPACE(chan, 6); |
d1b167e1 | 783 | if (ret == 0) { |
ebb945a9 BS |
784 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
785 | OUT_RING (chan, handle); | |
786 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 3); | |
787 | OUT_RING (chan, NvNotify0); | |
788 | OUT_RING (chan, NvDmaFB); | |
789 | OUT_RING (chan, NvDmaFB); | |
d1b167e1 BS |
790 | } |
791 | ||
792 | return ret; | |
793 | } | |
794 | ||
6ee73861 | 795 | static int |
f1ab0cc9 BS |
796 | nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, |
797 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
6ee73861 | 798 | { |
d2f96666 | 799 | struct nouveau_mem *node = old_mem->mm_node; |
f1ab0cc9 BS |
800 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
801 | u64 length = (new_mem->num_pages << PAGE_SHIFT); | |
d2f96666 BS |
802 | u64 src_offset = node->vma[0].offset; |
803 | u64 dst_offset = node->vma[1].offset; | |
6ee73861 BS |
804 | int ret; |
805 | ||
f1ab0cc9 BS |
806 | while (length) { |
807 | u32 amount, stride, height; | |
808 | ||
5220b3c1 BS |
809 | amount = min(length, (u64)(4 * 1024 * 1024)); |
810 | stride = 16 * 4; | |
f1ab0cc9 BS |
811 | height = amount / stride; |
812 | ||
c1b90df2 | 813 | if (old_mem->mem_type == TTM_PL_VRAM && |
f13b3263 | 814 | nouveau_bo_tile_layout(nvbo)) { |
f1ab0cc9 BS |
815 | ret = RING_SPACE(chan, 8); |
816 | if (ret) | |
817 | return ret; | |
818 | ||
d1b167e1 | 819 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); |
f1ab0cc9 | 820 | OUT_RING (chan, 0); |
5220b3c1 | 821 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
822 | OUT_RING (chan, stride); |
823 | OUT_RING (chan, height); | |
824 | OUT_RING (chan, 1); | |
825 | OUT_RING (chan, 0); | |
826 | OUT_RING (chan, 0); | |
827 | } else { | |
828 | ret = RING_SPACE(chan, 2); | |
829 | if (ret) | |
830 | return ret; | |
831 | ||
d1b167e1 | 832 | BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); |
f1ab0cc9 BS |
833 | OUT_RING (chan, 1); |
834 | } | |
c1b90df2 | 835 | if (new_mem->mem_type == TTM_PL_VRAM && |
f13b3263 | 836 | nouveau_bo_tile_layout(nvbo)) { |
f1ab0cc9 BS |
837 | ret = RING_SPACE(chan, 8); |
838 | if (ret) | |
839 | return ret; | |
840 | ||
d1b167e1 | 841 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); |
f1ab0cc9 | 842 | OUT_RING (chan, 0); |
5220b3c1 | 843 | OUT_RING (chan, 0); |
f1ab0cc9 BS |
844 | OUT_RING (chan, stride); |
845 | OUT_RING (chan, height); | |
846 | OUT_RING (chan, 1); | |
847 | OUT_RING (chan, 0); | |
848 | OUT_RING (chan, 0); | |
849 | } else { | |
850 | ret = RING_SPACE(chan, 2); | |
851 | if (ret) | |
852 | return ret; | |
853 | ||
d1b167e1 | 854 | BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); |
f1ab0cc9 BS |
855 | OUT_RING (chan, 1); |
856 | } | |
857 | ||
858 | ret = RING_SPACE(chan, 14); | |
6ee73861 BS |
859 | if (ret) |
860 | return ret; | |
f1ab0cc9 | 861 | |
d1b167e1 | 862 | BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); |
f1ab0cc9 BS |
863 | OUT_RING (chan, upper_32_bits(src_offset)); |
864 | OUT_RING (chan, upper_32_bits(dst_offset)); | |
d1b167e1 | 865 | BEGIN_NV04(chan, NvSubCopy, 0x030c, 8); |
f1ab0cc9 BS |
866 | OUT_RING (chan, lower_32_bits(src_offset)); |
867 | OUT_RING (chan, lower_32_bits(dst_offset)); | |
868 | OUT_RING (chan, stride); | |
869 | OUT_RING (chan, stride); | |
870 | OUT_RING (chan, stride); | |
871 | OUT_RING (chan, height); | |
872 | OUT_RING (chan, 0x00000101); | |
873 | OUT_RING (chan, 0x00000000); | |
d1b167e1 | 874 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 BS |
875 | OUT_RING (chan, 0); |
876 | ||
877 | length -= amount; | |
878 | src_offset += amount; | |
879 | dst_offset += amount; | |
6ee73861 BS |
880 | } |
881 | ||
f1ab0cc9 BS |
882 | return 0; |
883 | } | |
884 | ||
d1b167e1 BS |
885 | static int |
886 | nv04_bo_move_init(struct nouveau_channel *chan, u32 handle) | |
887 | { | |
ebb945a9 | 888 | int ret = RING_SPACE(chan, 4); |
d1b167e1 | 889 | if (ret == 0) { |
ebb945a9 BS |
890 | BEGIN_NV04(chan, NvSubCopy, 0x0000, 1); |
891 | OUT_RING (chan, handle); | |
892 | BEGIN_NV04(chan, NvSubCopy, 0x0180, 1); | |
893 | OUT_RING (chan, NvNotify0); | |
d1b167e1 BS |
894 | } |
895 | ||
896 | return ret; | |
897 | } | |
898 | ||
a6704788 BS |
899 | static inline uint32_t |
900 | nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo, | |
901 | struct nouveau_channel *chan, struct ttm_mem_reg *mem) | |
902 | { | |
903 | if (mem->mem_type == TTM_PL_TT) | |
ebb945a9 BS |
904 | return NvDmaTT; |
905 | return NvDmaFB; | |
a6704788 BS |
906 | } |
907 | ||
f1ab0cc9 BS |
908 | static int |
909 | nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo, | |
910 | struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) | |
911 | { | |
d961db75 BS |
912 | u32 src_offset = old_mem->start << PAGE_SHIFT; |
913 | u32 dst_offset = new_mem->start << PAGE_SHIFT; | |
f1ab0cc9 BS |
914 | u32 page_count = new_mem->num_pages; |
915 | int ret; | |
916 | ||
917 | ret = RING_SPACE(chan, 3); | |
918 | if (ret) | |
919 | return ret; | |
920 | ||
d1b167e1 | 921 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2); |
f1ab0cc9 BS |
922 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem)); |
923 | OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem)); | |
924 | ||
6ee73861 BS |
925 | page_count = new_mem->num_pages; |
926 | while (page_count) { | |
927 | int line_count = (page_count > 2047) ? 2047 : page_count; | |
928 | ||
6ee73861 BS |
929 | ret = RING_SPACE(chan, 11); |
930 | if (ret) | |
931 | return ret; | |
f1ab0cc9 | 932 | |
d1b167e1 | 933 | BEGIN_NV04(chan, NvSubCopy, |
6ee73861 | 934 | NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8); |
f1ab0cc9 BS |
935 | OUT_RING (chan, src_offset); |
936 | OUT_RING (chan, dst_offset); | |
937 | OUT_RING (chan, PAGE_SIZE); /* src_pitch */ | |
938 | OUT_RING (chan, PAGE_SIZE); /* dst_pitch */ | |
939 | OUT_RING (chan, PAGE_SIZE); /* line_length */ | |
940 | OUT_RING (chan, line_count); | |
941 | OUT_RING (chan, 0x00000101); | |
942 | OUT_RING (chan, 0x00000000); | |
d1b167e1 | 943 | BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1); |
f1ab0cc9 | 944 | OUT_RING (chan, 0); |
6ee73861 BS |
945 | |
946 | page_count -= line_count; | |
947 | src_offset += (PAGE_SIZE * line_count); | |
948 | dst_offset += (PAGE_SIZE * line_count); | |
949 | } | |
950 | ||
f1ab0cc9 BS |
951 | return 0; |
952 | } | |
953 | ||
d2f96666 BS |
954 | static int |
955 | nouveau_vma_getmap(struct nouveau_channel *chan, struct nouveau_bo *nvbo, | |
956 | struct ttm_mem_reg *mem, struct nouveau_vma *vma) | |
957 | { | |
958 | struct nouveau_mem *node = mem->mm_node; | |
959 | int ret; | |
960 | ||
ebb945a9 BS |
961 | ret = nouveau_vm_get(nv_client(chan->cli)->vm, mem->num_pages << |
962 | PAGE_SHIFT, node->page_shift, | |
963 | NV_MEM_ACCESS_RW, vma); | |
d2f96666 BS |
964 | if (ret) |
965 | return ret; | |
966 | ||
967 | if (mem->mem_type == TTM_PL_VRAM) | |
968 | nouveau_vm_map(vma, node); | |
969 | else | |
f7b24c42 | 970 | nouveau_vm_map_sg(vma, 0, mem->num_pages << PAGE_SHIFT, node); |
d2f96666 BS |
971 | |
972 | return 0; | |
973 | } | |
974 | ||
f1ab0cc9 BS |
975 | static int |
976 | nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr, | |
97a875cb | 977 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
f1ab0cc9 | 978 | { |
ebb945a9 | 979 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1bb3f6a2 | 980 | struct nouveau_channel *chan = chan = drm->ttm.chan; |
f1ab0cc9 | 981 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
3425df48 | 982 | struct ttm_mem_reg *old_mem = &bo->mem; |
f1ab0cc9 BS |
983 | int ret; |
984 | ||
060810d7 | 985 | mutex_lock_nested(&chan->cli->mutex, SINGLE_DEPTH_NESTING); |
f1ab0cc9 | 986 | |
d2f96666 BS |
987 | /* create temporary vmas for the transfer and attach them to the |
988 | * old nouveau_mem node, these will get cleaned up after ttm has | |
989 | * destroyed the ttm_mem_reg | |
3425df48 | 990 | */ |
ebb945a9 | 991 | if (nv_device(drm->device)->card_type >= NV_50) { |
d5f42394 | 992 | struct nouveau_mem *node = old_mem->mm_node; |
3425df48 | 993 | |
d2f96666 BS |
994 | ret = nouveau_vma_getmap(chan, nvbo, old_mem, &node->vma[0]); |
995 | if (ret) | |
996 | goto out; | |
997 | ||
998 | ret = nouveau_vma_getmap(chan, nvbo, new_mem, &node->vma[1]); | |
999 | if (ret) | |
1000 | goto out; | |
3425df48 BS |
1001 | } |
1002 | ||
ebb945a9 | 1003 | ret = drm->ttm.move(chan, bo, &bo->mem, new_mem); |
6a6b73f2 BS |
1004 | if (ret == 0) { |
1005 | ret = nouveau_bo_move_accel_cleanup(chan, nvbo, evict, | |
6a6b73f2 BS |
1006 | no_wait_gpu, new_mem); |
1007 | } | |
f1ab0cc9 | 1008 | |
3425df48 | 1009 | out: |
ebb945a9 | 1010 | mutex_unlock(&chan->cli->mutex); |
6a6b73f2 | 1011 | return ret; |
6ee73861 BS |
1012 | } |
1013 | ||
d1b167e1 | 1014 | void |
49981046 | 1015 | nouveau_bo_move_init(struct nouveau_drm *drm) |
d1b167e1 | 1016 | { |
d1b167e1 BS |
1017 | static const struct { |
1018 | const char *name; | |
1a46098e | 1019 | int engine; |
d1b167e1 BS |
1020 | u32 oclass; |
1021 | int (*exec)(struct nouveau_channel *, | |
1022 | struct ttm_buffer_object *, | |
1023 | struct ttm_mem_reg *, struct ttm_mem_reg *); | |
1024 | int (*init)(struct nouveau_channel *, u32 handle); | |
1025 | } _methods[] = { | |
00fc6f6f | 1026 | { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init }, |
49981046 | 1027 | { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init }, |
1a46098e BS |
1028 | { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init }, |
1029 | { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init }, | |
1030 | { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init }, | |
1031 | { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init }, | |
1032 | { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init }, | |
1033 | { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init }, | |
1034 | { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init }, | |
5490e5df | 1035 | {}, |
1a46098e | 1036 | { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init }, |
d1b167e1 BS |
1037 | }, *mthd = _methods; |
1038 | const char *name = "CPU"; | |
1039 | int ret; | |
1040 | ||
1041 | do { | |
ebb945a9 | 1042 | struct nouveau_object *object; |
49981046 | 1043 | struct nouveau_channel *chan; |
1a46098e | 1044 | u32 handle = (mthd->engine << 16) | mthd->oclass; |
ebb945a9 | 1045 | |
00fc6f6f | 1046 | if (mthd->engine) |
49981046 BS |
1047 | chan = drm->cechan; |
1048 | else | |
1049 | chan = drm->channel; | |
1050 | if (chan == NULL) | |
1051 | continue; | |
1052 | ||
1053 | ret = nouveau_object_new(nv_object(drm), chan->handle, handle, | |
ebb945a9 | 1054 | mthd->oclass, NULL, 0, &object); |
d1b167e1 | 1055 | if (ret == 0) { |
1a46098e | 1056 | ret = mthd->init(chan, handle); |
ebb945a9 | 1057 | if (ret) { |
49981046 | 1058 | nouveau_object_del(nv_object(drm), |
ebb945a9 BS |
1059 | chan->handle, handle); |
1060 | continue; | |
d1b167e1 | 1061 | } |
ebb945a9 BS |
1062 | |
1063 | drm->ttm.move = mthd->exec; | |
1bb3f6a2 | 1064 | drm->ttm.chan = chan; |
ebb945a9 BS |
1065 | name = mthd->name; |
1066 | break; | |
d1b167e1 BS |
1067 | } |
1068 | } while ((++mthd)->exec); | |
1069 | ||
ebb945a9 | 1070 | NV_INFO(drm, "MM: using %s for buffer copies\n", name); |
d1b167e1 BS |
1071 | } |
1072 | ||
6ee73861 BS |
1073 | static int |
1074 | nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr, | |
97a875cb | 1075 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
6ee73861 BS |
1076 | { |
1077 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
1078 | struct ttm_placement placement; | |
1079 | struct ttm_mem_reg tmp_mem; | |
1080 | int ret; | |
1081 | ||
1082 | placement.fpfn = placement.lpfn = 0; | |
1083 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 1084 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
1085 | |
1086 | tmp_mem = *new_mem; | |
1087 | tmp_mem.mm_node = NULL; | |
97a875cb | 1088 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); |
6ee73861 BS |
1089 | if (ret) |
1090 | return ret; | |
1091 | ||
1092 | ret = ttm_tt_bind(bo->ttm, &tmp_mem); | |
1093 | if (ret) | |
1094 | goto out; | |
1095 | ||
97a875cb | 1096 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
1097 | if (ret) |
1098 | goto out; | |
1099 | ||
97a875cb | 1100 | ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem); |
6ee73861 | 1101 | out: |
42311ff9 | 1102 | ttm_bo_mem_put(bo, &tmp_mem); |
6ee73861 BS |
1103 | return ret; |
1104 | } | |
1105 | ||
1106 | static int | |
1107 | nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr, | |
97a875cb | 1108 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
6ee73861 BS |
1109 | { |
1110 | u32 placement_memtype = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING; | |
1111 | struct ttm_placement placement; | |
1112 | struct ttm_mem_reg tmp_mem; | |
1113 | int ret; | |
1114 | ||
1115 | placement.fpfn = placement.lpfn = 0; | |
1116 | placement.num_placement = placement.num_busy_placement = 1; | |
77e2b5ed | 1117 | placement.placement = placement.busy_placement = &placement_memtype; |
6ee73861 BS |
1118 | |
1119 | tmp_mem = *new_mem; | |
1120 | tmp_mem.mm_node = NULL; | |
97a875cb | 1121 | ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu); |
6ee73861 BS |
1122 | if (ret) |
1123 | return ret; | |
1124 | ||
97a875cb | 1125 | ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem); |
6ee73861 BS |
1126 | if (ret) |
1127 | goto out; | |
1128 | ||
97a875cb | 1129 | ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem); |
6ee73861 BS |
1130 | if (ret) |
1131 | goto out; | |
1132 | ||
1133 | out: | |
42311ff9 | 1134 | ttm_bo_mem_put(bo, &tmp_mem); |
6ee73861 BS |
1135 | return ret; |
1136 | } | |
1137 | ||
a4154bbf BS |
1138 | static void |
1139 | nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem) | |
1140 | { | |
a4154bbf | 1141 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
fd2871af BS |
1142 | struct nouveau_vma *vma; |
1143 | ||
9f1feed2 BS |
1144 | /* ttm can now (stupidly) pass the driver bos it didn't create... */ |
1145 | if (bo->destroy != nouveau_bo_del_ttm) | |
1146 | return; | |
1147 | ||
fd2871af | 1148 | list_for_each_entry(vma, &nvbo->vma_list, head) { |
dc97b340 | 1149 | if (new_mem && new_mem->mem_type == TTM_PL_VRAM) { |
fd2871af BS |
1150 | nouveau_vm_map(vma, new_mem->mm_node); |
1151 | } else | |
dc97b340 | 1152 | if (new_mem && new_mem->mem_type == TTM_PL_TT && |
ebb945a9 | 1153 | nvbo->page_shift == vma->vm->vmm->spg_shift) { |
22b33e8e DA |
1154 | if (((struct nouveau_mem *)new_mem->mm_node)->sg) |
1155 | nouveau_vm_map_sg_table(vma, 0, new_mem-> | |
1156 | num_pages << PAGE_SHIFT, | |
1157 | new_mem->mm_node); | |
1158 | else | |
1159 | nouveau_vm_map_sg(vma, 0, new_mem-> | |
1160 | num_pages << PAGE_SHIFT, | |
1161 | new_mem->mm_node); | |
fd2871af BS |
1162 | } else { |
1163 | nouveau_vm_unmap(vma); | |
1164 | } | |
a4154bbf BS |
1165 | } |
1166 | } | |
1167 | ||
6ee73861 | 1168 | static int |
a0af9add | 1169 | nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem, |
ebb945a9 | 1170 | struct nouveau_drm_tile **new_tile) |
6ee73861 | 1171 | { |
ebb945a9 BS |
1172 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1173 | struct drm_device *dev = drm->dev; | |
a0af9add | 1174 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
a4154bbf | 1175 | u64 offset = new_mem->start << PAGE_SHIFT; |
6ee73861 | 1176 | |
a4154bbf BS |
1177 | *new_tile = NULL; |
1178 | if (new_mem->mem_type != TTM_PL_VRAM) | |
a0af9add | 1179 | return 0; |
a0af9add | 1180 | |
ebb945a9 | 1181 | if (nv_device(drm->device)->card_type >= NV_10) { |
bc9e7b9a | 1182 | *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size, |
a5cf68b0 FJ |
1183 | nvbo->tile_mode, |
1184 | nvbo->tile_flags); | |
6ee73861 BS |
1185 | } |
1186 | ||
a0af9add FJ |
1187 | return 0; |
1188 | } | |
1189 | ||
1190 | static void | |
1191 | nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo, | |
ebb945a9 BS |
1192 | struct nouveau_drm_tile *new_tile, |
1193 | struct nouveau_drm_tile **old_tile) | |
a0af9add | 1194 | { |
ebb945a9 BS |
1195 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
1196 | struct drm_device *dev = drm->dev; | |
a0af9add | 1197 | |
bc9e7b9a | 1198 | nv10_bo_put_tile_region(dev, *old_tile, bo->sync_obj); |
a4154bbf | 1199 | *old_tile = new_tile; |
a0af9add FJ |
1200 | } |
1201 | ||
1202 | static int | |
1203 | nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr, | |
97a875cb | 1204 | bool no_wait_gpu, struct ttm_mem_reg *new_mem) |
a0af9add | 1205 | { |
ebb945a9 | 1206 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
a0af9add FJ |
1207 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
1208 | struct ttm_mem_reg *old_mem = &bo->mem; | |
ebb945a9 | 1209 | struct nouveau_drm_tile *new_tile = NULL; |
a0af9add FJ |
1210 | int ret = 0; |
1211 | ||
ebb945a9 | 1212 | if (nv_device(drm->device)->card_type < NV_50) { |
a4154bbf BS |
1213 | ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile); |
1214 | if (ret) | |
1215 | return ret; | |
1216 | } | |
a0af9add | 1217 | |
a0af9add | 1218 | /* Fake bo copy. */ |
6ee73861 BS |
1219 | if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) { |
1220 | BUG_ON(bo->mem.mm_node != NULL); | |
1221 | bo->mem = *new_mem; | |
1222 | new_mem->mm_node = NULL; | |
a0af9add | 1223 | goto out; |
6ee73861 BS |
1224 | } |
1225 | ||
d1b167e1 | 1226 | /* CPU copy if we have no accelerated method available */ |
ebb945a9 | 1227 | if (!drm->ttm.move) { |
97a875cb | 1228 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); |
b8a6a804 BS |
1229 | goto out; |
1230 | } | |
1231 | ||
a0af9add FJ |
1232 | /* Hardware assisted copy. */ |
1233 | if (new_mem->mem_type == TTM_PL_SYSTEM) | |
97a875cb ML |
1234 | ret = nouveau_bo_move_flipd(bo, evict, intr, |
1235 | no_wait_gpu, new_mem); | |
a0af9add | 1236 | else if (old_mem->mem_type == TTM_PL_SYSTEM) |
97a875cb ML |
1237 | ret = nouveau_bo_move_flips(bo, evict, intr, |
1238 | no_wait_gpu, new_mem); | |
a0af9add | 1239 | else |
97a875cb ML |
1240 | ret = nouveau_bo_move_m2mf(bo, evict, intr, |
1241 | no_wait_gpu, new_mem); | |
6ee73861 | 1242 | |
a0af9add FJ |
1243 | if (!ret) |
1244 | goto out; | |
1245 | ||
1246 | /* Fallback to software copy. */ | |
97a875cb | 1247 | ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem); |
a0af9add FJ |
1248 | |
1249 | out: | |
ebb945a9 | 1250 | if (nv_device(drm->device)->card_type < NV_50) { |
a4154bbf BS |
1251 | if (ret) |
1252 | nouveau_bo_vm_cleanup(bo, NULL, &new_tile); | |
1253 | else | |
1254 | nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile); | |
1255 | } | |
a0af9add FJ |
1256 | |
1257 | return ret; | |
6ee73861 BS |
1258 | } |
1259 | ||
1260 | static int | |
1261 | nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp) | |
1262 | { | |
acb46527 DH |
1263 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
1264 | ||
1265 | return drm_vma_node_verify_access(&nvbo->gem->vma_node, filp); | |
6ee73861 BS |
1266 | } |
1267 | ||
f32f02fd JG |
1268 | static int |
1269 | nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
1270 | { | |
1271 | struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type]; | |
ebb945a9 BS |
1272 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
1273 | struct drm_device *dev = drm->dev; | |
f869ef88 | 1274 | int ret; |
f32f02fd JG |
1275 | |
1276 | mem->bus.addr = NULL; | |
1277 | mem->bus.offset = 0; | |
1278 | mem->bus.size = mem->num_pages << PAGE_SHIFT; | |
1279 | mem->bus.base = 0; | |
1280 | mem->bus.is_iomem = false; | |
1281 | if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE)) | |
1282 | return -EINVAL; | |
1283 | switch (mem->mem_type) { | |
1284 | case TTM_PL_SYSTEM: | |
1285 | /* System memory */ | |
1286 | return 0; | |
1287 | case TTM_PL_TT: | |
1288 | #if __OS_HAS_AGP | |
ebb945a9 | 1289 | if (drm->agp.stat == ENABLED) { |
d961db75 | 1290 | mem->bus.offset = mem->start << PAGE_SHIFT; |
ebb945a9 | 1291 | mem->bus.base = drm->agp.base; |
eda85d6a | 1292 | mem->bus.is_iomem = !dev->agp->cant_use_aperture; |
f32f02fd JG |
1293 | } |
1294 | #endif | |
1295 | break; | |
1296 | case TTM_PL_VRAM: | |
3863c9bc BS |
1297 | mem->bus.offset = mem->start << PAGE_SHIFT; |
1298 | mem->bus.base = pci_resource_start(dev->pdev, 1); | |
1299 | mem->bus.is_iomem = true; | |
ebb945a9 BS |
1300 | if (nv_device(drm->device)->card_type >= NV_50) { |
1301 | struct nouveau_bar *bar = nouveau_bar(drm->device); | |
3863c9bc | 1302 | struct nouveau_mem *node = mem->mm_node; |
8984e046 | 1303 | |
ebb945a9 | 1304 | ret = bar->umap(bar, node, NV_MEM_ACCESS_RW, |
3863c9bc BS |
1305 | &node->bar_vma); |
1306 | if (ret) | |
1307 | return ret; | |
f869ef88 | 1308 | |
3863c9bc | 1309 | mem->bus.offset = node->bar_vma.offset; |
f869ef88 | 1310 | } |
f32f02fd JG |
1311 | break; |
1312 | default: | |
1313 | return -EINVAL; | |
1314 | } | |
1315 | return 0; | |
1316 | } | |
1317 | ||
1318 | static void | |
1319 | nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem) | |
1320 | { | |
ebb945a9 BS |
1321 | struct nouveau_drm *drm = nouveau_bdev(bdev); |
1322 | struct nouveau_bar *bar = nouveau_bar(drm->device); | |
d5f42394 | 1323 | struct nouveau_mem *node = mem->mm_node; |
f869ef88 | 1324 | |
d5f42394 | 1325 | if (!node->bar_vma.node) |
f869ef88 BS |
1326 | return; |
1327 | ||
ebb945a9 | 1328 | bar->unmap(bar, &node->bar_vma); |
f32f02fd JG |
1329 | } |
1330 | ||
1331 | static int | |
1332 | nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo) | |
1333 | { | |
ebb945a9 | 1334 | struct nouveau_drm *drm = nouveau_bdev(bo->bdev); |
e1429b4c | 1335 | struct nouveau_bo *nvbo = nouveau_bo(bo); |
ebb945a9 BS |
1336 | struct nouveau_device *device = nv_device(drm->device); |
1337 | u32 mappable = pci_resource_len(device->pdev, 1) >> PAGE_SHIFT; | |
e1429b4c BS |
1338 | |
1339 | /* as long as the bo isn't in vram, and isn't tiled, we've got | |
1340 | * nothing to do here. | |
1341 | */ | |
1342 | if (bo->mem.mem_type != TTM_PL_VRAM) { | |
ebb945a9 | 1343 | if (nv_device(drm->device)->card_type < NV_50 || |
f13b3263 | 1344 | !nouveau_bo_tile_layout(nvbo)) |
e1429b4c BS |
1345 | return 0; |
1346 | } | |
1347 | ||
1348 | /* make sure bo is in mappable vram */ | |
ebb945a9 | 1349 | if (bo->mem.start + bo->mem.num_pages < mappable) |
e1429b4c BS |
1350 | return 0; |
1351 | ||
1352 | ||
1353 | nvbo->placement.fpfn = 0; | |
ebb945a9 | 1354 | nvbo->placement.lpfn = mappable; |
c284815d | 1355 | nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0); |
97a875cb | 1356 | return nouveau_bo_validate(nvbo, false, false); |
f32f02fd JG |
1357 | } |
1358 | ||
3230cfc3 KRW |
1359 | static int |
1360 | nouveau_ttm_tt_populate(struct ttm_tt *ttm) | |
1361 | { | |
8e7e7052 | 1362 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
ebb945a9 | 1363 | struct nouveau_drm *drm; |
3230cfc3 KRW |
1364 | struct drm_device *dev; |
1365 | unsigned i; | |
1366 | int r; | |
22b33e8e | 1367 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
3230cfc3 KRW |
1368 | |
1369 | if (ttm->state != tt_unpopulated) | |
1370 | return 0; | |
1371 | ||
22b33e8e DA |
1372 | if (slave && ttm->sg) { |
1373 | /* make userspace faulting work */ | |
1374 | drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages, | |
1375 | ttm_dma->dma_address, ttm->num_pages); | |
1376 | ttm->state = tt_unbound; | |
1377 | return 0; | |
1378 | } | |
1379 | ||
ebb945a9 BS |
1380 | drm = nouveau_bdev(ttm->bdev); |
1381 | dev = drm->dev; | |
3230cfc3 | 1382 | |
dea7e0ac | 1383 | #if __OS_HAS_AGP |
ebb945a9 | 1384 | if (drm->agp.stat == ENABLED) { |
dea7e0ac JG |
1385 | return ttm_agp_tt_populate(ttm); |
1386 | } | |
1387 | #endif | |
1388 | ||
3230cfc3 KRW |
1389 | #ifdef CONFIG_SWIOTLB |
1390 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 1391 | return ttm_dma_populate((void *)ttm, dev->dev); |
3230cfc3 KRW |
1392 | } |
1393 | #endif | |
1394 | ||
1395 | r = ttm_pool_populate(ttm); | |
1396 | if (r) { | |
1397 | return r; | |
1398 | } | |
1399 | ||
1400 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 | 1401 | ttm_dma->dma_address[i] = pci_map_page(dev->pdev, ttm->pages[i], |
3230cfc3 KRW |
1402 | 0, PAGE_SIZE, |
1403 | PCI_DMA_BIDIRECTIONAL); | |
8e7e7052 | 1404 | if (pci_dma_mapping_error(dev->pdev, ttm_dma->dma_address[i])) { |
3230cfc3 | 1405 | while (--i) { |
8e7e7052 | 1406 | pci_unmap_page(dev->pdev, ttm_dma->dma_address[i], |
3230cfc3 | 1407 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
8e7e7052 | 1408 | ttm_dma->dma_address[i] = 0; |
3230cfc3 KRW |
1409 | } |
1410 | ttm_pool_unpopulate(ttm); | |
1411 | return -EFAULT; | |
1412 | } | |
1413 | } | |
1414 | return 0; | |
1415 | } | |
1416 | ||
1417 | static void | |
1418 | nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) | |
1419 | { | |
8e7e7052 | 1420 | struct ttm_dma_tt *ttm_dma = (void *)ttm; |
ebb945a9 | 1421 | struct nouveau_drm *drm; |
3230cfc3 KRW |
1422 | struct drm_device *dev; |
1423 | unsigned i; | |
22b33e8e DA |
1424 | bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG); |
1425 | ||
1426 | if (slave) | |
1427 | return; | |
3230cfc3 | 1428 | |
ebb945a9 BS |
1429 | drm = nouveau_bdev(ttm->bdev); |
1430 | dev = drm->dev; | |
3230cfc3 | 1431 | |
dea7e0ac | 1432 | #if __OS_HAS_AGP |
ebb945a9 | 1433 | if (drm->agp.stat == ENABLED) { |
dea7e0ac JG |
1434 | ttm_agp_tt_unpopulate(ttm); |
1435 | return; | |
1436 | } | |
1437 | #endif | |
1438 | ||
3230cfc3 KRW |
1439 | #ifdef CONFIG_SWIOTLB |
1440 | if (swiotlb_nr_tbl()) { | |
8e7e7052 | 1441 | ttm_dma_unpopulate((void *)ttm, dev->dev); |
3230cfc3 KRW |
1442 | return; |
1443 | } | |
1444 | #endif | |
1445 | ||
1446 | for (i = 0; i < ttm->num_pages; i++) { | |
8e7e7052 JG |
1447 | if (ttm_dma->dma_address[i]) { |
1448 | pci_unmap_page(dev->pdev, ttm_dma->dma_address[i], | |
3230cfc3 KRW |
1449 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
1450 | } | |
1451 | } | |
1452 | ||
1453 | ttm_pool_unpopulate(ttm); | |
1454 | } | |
1455 | ||
875ac34a BS |
1456 | void |
1457 | nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence) | |
1458 | { | |
1459 | struct nouveau_fence *old_fence = NULL; | |
1460 | ||
1461 | if (likely(fence)) | |
1462 | nouveau_fence_ref(fence); | |
1463 | ||
1464 | spin_lock(&nvbo->bo.bdev->fence_lock); | |
1465 | old_fence = nvbo->bo.sync_obj; | |
1466 | nvbo->bo.sync_obj = fence; | |
1467 | spin_unlock(&nvbo->bo.bdev->fence_lock); | |
1468 | ||
1469 | nouveau_fence_unref(&old_fence); | |
1470 | } | |
1471 | ||
1472 | static void | |
1473 | nouveau_bo_fence_unref(void **sync_obj) | |
1474 | { | |
1475 | nouveau_fence_unref((struct nouveau_fence **)sync_obj); | |
1476 | } | |
1477 | ||
1478 | static void * | |
1479 | nouveau_bo_fence_ref(void *sync_obj) | |
1480 | { | |
1481 | return nouveau_fence_ref(sync_obj); | |
1482 | } | |
1483 | ||
1484 | static bool | |
dedfdffd | 1485 | nouveau_bo_fence_signalled(void *sync_obj) |
875ac34a | 1486 | { |
d375e7d5 | 1487 | return nouveau_fence_done(sync_obj); |
875ac34a BS |
1488 | } |
1489 | ||
1490 | static int | |
dedfdffd | 1491 | nouveau_bo_fence_wait(void *sync_obj, bool lazy, bool intr) |
875ac34a BS |
1492 | { |
1493 | return nouveau_fence_wait(sync_obj, lazy, intr); | |
1494 | } | |
1495 | ||
1496 | static int | |
dedfdffd | 1497 | nouveau_bo_fence_flush(void *sync_obj) |
875ac34a BS |
1498 | { |
1499 | return 0; | |
1500 | } | |
1501 | ||
6ee73861 | 1502 | struct ttm_bo_driver nouveau_bo_driver = { |
649bf3ca | 1503 | .ttm_tt_create = &nouveau_ttm_tt_create, |
3230cfc3 KRW |
1504 | .ttm_tt_populate = &nouveau_ttm_tt_populate, |
1505 | .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate, | |
6ee73861 BS |
1506 | .invalidate_caches = nouveau_bo_invalidate_caches, |
1507 | .init_mem_type = nouveau_bo_init_mem_type, | |
1508 | .evict_flags = nouveau_bo_evict_flags, | |
a4154bbf | 1509 | .move_notify = nouveau_bo_move_ntfy, |
6ee73861 BS |
1510 | .move = nouveau_bo_move, |
1511 | .verify_access = nouveau_bo_verify_access, | |
875ac34a BS |
1512 | .sync_obj_signaled = nouveau_bo_fence_signalled, |
1513 | .sync_obj_wait = nouveau_bo_fence_wait, | |
1514 | .sync_obj_flush = nouveau_bo_fence_flush, | |
1515 | .sync_obj_unref = nouveau_bo_fence_unref, | |
1516 | .sync_obj_ref = nouveau_bo_fence_ref, | |
f32f02fd JG |
1517 | .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify, |
1518 | .io_mem_reserve = &nouveau_ttm_io_mem_reserve, | |
1519 | .io_mem_free = &nouveau_ttm_io_mem_free, | |
6ee73861 BS |
1520 | }; |
1521 | ||
fd2871af BS |
1522 | struct nouveau_vma * |
1523 | nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm) | |
1524 | { | |
1525 | struct nouveau_vma *vma; | |
1526 | list_for_each_entry(vma, &nvbo->vma_list, head) { | |
1527 | if (vma->vm == vm) | |
1528 | return vma; | |
1529 | } | |
1530 | ||
1531 | return NULL; | |
1532 | } | |
1533 | ||
1534 | int | |
1535 | nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm, | |
1536 | struct nouveau_vma *vma) | |
1537 | { | |
1538 | const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT; | |
1539 | struct nouveau_mem *node = nvbo->bo.mem.mm_node; | |
1540 | int ret; | |
1541 | ||
1542 | ret = nouveau_vm_get(vm, size, nvbo->page_shift, | |
1543 | NV_MEM_ACCESS_RW, vma); | |
1544 | if (ret) | |
1545 | return ret; | |
1546 | ||
1547 | if (nvbo->bo.mem.mem_type == TTM_PL_VRAM) | |
1548 | nouveau_vm_map(vma, nvbo->bo.mem.mm_node); | |
22b33e8e DA |
1549 | else if (nvbo->bo.mem.mem_type == TTM_PL_TT) { |
1550 | if (node->sg) | |
1551 | nouveau_vm_map_sg_table(vma, 0, size, node); | |
1552 | else | |
1553 | nouveau_vm_map_sg(vma, 0, size, node); | |
1554 | } | |
fd2871af BS |
1555 | |
1556 | list_add_tail(&vma->head, &nvbo->vma_list); | |
2fd3db6f | 1557 | vma->refcount = 1; |
fd2871af BS |
1558 | return 0; |
1559 | } | |
1560 | ||
1561 | void | |
1562 | nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma) | |
1563 | { | |
1564 | if (vma->node) { | |
c4c7044f | 1565 | if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM) |
fd2871af | 1566 | nouveau_vm_unmap(vma); |
fd2871af BS |
1567 | nouveau_vm_put(vma); |
1568 | list_del(&vma->head); | |
1569 | } | |
1570 | } |