[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_chan.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <nvif/os.h>
#include <nvif/class.h>

/*XXX*/
#include <core/client.h>

#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nouveau_bo.h"
#include "nouveau_chan.h"
#include "nouveau_fence.h"
#include "nouveau_abi16.h"

MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
int nouveau_vram_pushbuf;
module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);

int
nouveau_channel_idle(struct nouveau_channel *chan)
{
	struct nouveau_cli *cli = (void *)nvif_client(chan->object);
	struct nouveau_fence *fence = NULL;
	int ret;

	ret = nouveau_fence_new(chan, false, &fence);
	if (!ret) {
		ret = nouveau_fence_wait(fence, false, false);
		nouveau_fence_unref(&fence);
	}

	if (ret)
		NV_PRINTK(error, cli, "failed to idle channel 0x%08x [%s]\n",
			  chan->object->handle, nvkm_client(&cli->base)->name);
	return ret;
}

void
nouveau_channel_del(struct nouveau_channel **pchan)
{
	struct nouveau_channel *chan = *pchan;
	if (chan) {
		if (chan->fence) {
			nouveau_channel_idle(chan);
			nouveau_fence(chan->drm)->context_del(chan);
		}
		nvif_object_fini(&chan->nvsw);
		nvif_object_fini(&chan->gart);
		nvif_object_fini(&chan->vram);
		nvif_object_ref(NULL, &chan->object);
		nvif_object_fini(&chan->push.ctxdma);
		nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
		nouveau_bo_unmap(chan->push.buffer);
		if (chan->push.buffer && chan->push.buffer->pin_refcnt)
			nouveau_bo_unpin(chan->push.buffer);
		nouveau_bo_ref(NULL, &chan->push.buffer);
		nvif_device_ref(NULL, &chan->device);
		kfree(chan);
	}
	*pchan = NULL;
}

static int
nouveau_channel_prep(struct nouveau_drm *drm, struct nvif_device *device,
		     u32 handle, u32 size, struct nouveau_channel **pchan)
{
	struct nouveau_cli *cli = (void *)nvif_client(&device->base);
	struct nouveau_vmmgr *vmm = nvkm_vmmgr(device);
	struct nv_dma_v0 args = {};
	struct nouveau_channel *chan;
	u32 target;
	int ret;

	chan = *pchan = kzalloc(sizeof(*chan), GFP_KERNEL);
	if (!chan)
		return -ENOMEM;

	nvif_device_ref(device, &chan->device);
	chan->drm = drm;

	/* allocate memory for dma push buffer */
	target = TTM_PL_FLAG_TT;
	if (nouveau_vram_pushbuf)
		target = TTM_PL_FLAG_VRAM;

	ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL,
			    &chan->push.buffer);
	if (ret == 0) {
		ret = nouveau_bo_pin(chan->push.buffer, target);
		if (ret == 0)
			ret = nouveau_bo_map(chan->push.buffer);
	}

	if (ret) {
		nouveau_channel_del(pchan);
		return ret;
	}

	/* create dma object covering the *entire* memory space that the
	 * pushbuf lives in, this is because the GEM code requires that
	 * we be able to call out to other (indirect) push buffers
	 */
	chan->push.vma.offset = chan->push.buffer->bo.offset;

	if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
		ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
					&chan->push.vma);
		if (ret) {
			nouveau_channel_del(pchan);
			return ret;
		}

		args.target = NV_DMA_V0_TARGET_VM;
		args.access = NV_DMA_V0_ACCESS_VM;
		args.start = 0;
		args.limit = cli->vm->vmm->limit - 1;
	} else
	if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
		if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
			/* nv04 vram pushbuf hack, retarget to its location in
			 * the framebuffer bar rather than direct vram access..
			 * nfi why this exists, it came from the -nv ddx.
			 */
			args.target = NV_DMA_V0_TARGET_PCI;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = nv_device_resource_start(nvkm_device(device), 1);
			args.limit = args.start + device->info.ram_user - 1;
		} else {
			args.target = NV_DMA_V0_TARGET_VRAM;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = 0;
			args.limit = device->info.ram_user - 1;
		}
	} else {
		if (chan->drm->agp.stat == ENABLED) {
			args.target = NV_DMA_V0_TARGET_AGP;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = chan->drm->agp.base;
			args.limit = chan->drm->agp.base +
				     chan->drm->agp.size - 1;
		} else {
			args.target = NV_DMA_V0_TARGET_VM;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = 0;
			args.limit = vmm->limit - 1;
		}
	}

	ret = nvif_object_init(nvif_object(device), NULL, NVDRM_PUSH |
			       (handle & 0xffff), NV_DMA_FROM_MEMORY,
			       &args, sizeof(args), &chan->push.ctxdma);
	if (ret) {
		nouveau_channel_del(pchan);
		return ret;
	}

	return 0;
}

static int
nouveau_channel_ind(struct nouveau_drm *drm, struct nvif_device *device,
		    u32 handle, u32 engine, struct nouveau_channel **pchan)
{
	static const u16 oclasses[] = { KEPLER_CHANNEL_GPFIFO_A,
					FERMI_CHANNEL_GPFIFO,
					G82_CHANNEL_GPFIFO,
					NV50_CHANNEL_GPFIFO,
					0 };
	const u16 *oclass = oclasses;
	union {
		struct nv50_channel_gpfifo_v0 nv50;
		struct kepler_channel_gpfifo_a_v0 kepler;
	} args, *retn;
	struct nouveau_channel *chan;
	u32 size;
	int ret;

	/* allocate dma push buffer */
	ret = nouveau_channel_prep(drm, device, handle, 0x12000, &chan);
	*pchan = chan;
	if (ret)
		return ret;

	/* create channel object */
	do {
		if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
			args.kepler.version = 0;
			args.kepler.engine  = engine;
			args.kepler.pushbuf = chan->push.ctxdma.handle;
			args.kepler.ilength = 0x02000;
			args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
			size = sizeof(args.kepler);
		} else {
			args.nv50.version = 0;
			args.nv50.pushbuf = chan->push.ctxdma.handle;
			args.nv50.ilength = 0x02000;
			args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
			size = sizeof(args.nv50);
		}

		ret = nvif_object_new(nvif_object(device), handle, *oclass++,
				      &args, size, &chan->object);
		if (ret == 0) {
			retn = chan->object->data;
			if (chan->object->oclass >= KEPLER_CHANNEL_GPFIFO_A)
				chan->chid = retn->kepler.chid;
			else
				chan->chid = retn->nv50.chid;
			return ret;
		}
	} while (*oclass);

	nouveau_channel_del(pchan);
	return ret;
}

static int
nouveau_channel_dma(struct nouveau_drm *drm, struct nvif_device *device,
		    u32 handle, struct nouveau_channel **pchan)
{
	static const u16 oclasses[] = { NV40_CHANNEL_DMA,
					NV17_CHANNEL_DMA,
					NV10_CHANNEL_DMA,
					NV03_CHANNEL_DMA,
					0 };
	const u16 *oclass = oclasses;
	struct nv03_channel_dma_v0 args, *retn;
	struct nouveau_channel *chan;
	int ret;

	/* allocate dma push buffer */
	ret = nouveau_channel_prep(drm, device, handle, 0x10000, &chan);
	*pchan = chan;
	if (ret)
		return ret;

	/* create channel object */
	args.version = 0;
	args.pushbuf = chan->push.ctxdma.handle;
	args.offset = chan->push.vma.offset;

	do {
		ret = nvif_object_new(nvif_object(device), handle, *oclass++,
				      &args, sizeof(args), &chan->object);
		if (ret == 0) {
			retn = chan->object->data;
			chan->chid = retn->chid;
			return ret;
		}
	} while (ret && *oclass);

	nouveau_channel_del(pchan);
	return ret;
}

static int
nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
{
	struct nvif_device *device = chan->device;
	struct nouveau_cli *cli = (void *)nvif_client(&device->base);
	struct nouveau_vmmgr *vmm = nvkm_vmmgr(device);
	struct nouveau_software_chan *swch;
	struct nv_dma_v0 args = {};
	int ret, i;
	bool save;

	nvif_object_map(chan->object);

	/* allocate dma objects to cover all allowed vram, and gart */
	if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
		if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
			args.target = NV_DMA_V0_TARGET_VM;
			args.access = NV_DMA_V0_ACCESS_VM;
			args.start = 0;
			args.limit = cli->vm->vmm->limit - 1;
		} else {
			args.target = NV_DMA_V0_TARGET_VRAM;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = 0;
			args.limit = device->info.ram_user - 1;
		}

		ret = nvif_object_init(chan->object, NULL, vram,
				       NV_DMA_IN_MEMORY, &args,
				       sizeof(args), &chan->vram);
		if (ret)
			return ret;

		if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
			args.target = NV_DMA_V0_TARGET_VM;
			args.access = NV_DMA_V0_ACCESS_VM;
			args.start = 0;
			args.limit = cli->vm->vmm->limit - 1;
		} else
		if (chan->drm->agp.stat == ENABLED) {
			args.target = NV_DMA_V0_TARGET_AGP;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = chan->drm->agp.base;
			args.limit = chan->drm->agp.base +
				     chan->drm->agp.size - 1;
		} else {
			args.target = NV_DMA_V0_TARGET_VM;
			args.access = NV_DMA_V0_ACCESS_RDWR;
			args.start = 0;
			args.limit = vmm->limit - 1;
		}

		ret = nvif_object_init(chan->object, NULL, gart,
				       NV_DMA_IN_MEMORY, &args,
				       sizeof(args), &chan->gart);
		if (ret)
			return ret;
	}

	/* initialise dma tracking parameters */
	switch (chan->object->oclass & 0x00ff) {
	case 0x006b:
	case 0x006e:
		chan->user_put = 0x40;
		chan->user_get = 0x44;
		chan->dma.max = (0x10000 / 4) - 2;
		break;
	default:
		chan->user_put = 0x40;
		chan->user_get = 0x44;
		chan->user_get_hi = 0x60;
		chan->dma.ib_base =  0x10000 / 4;
		chan->dma.ib_max  = (0x02000 / 8) - 1;
		chan->dma.ib_put  = 0;
		chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
		chan->dma.max = chan->dma.ib_base;
		break;
	}

	chan->dma.put = 0;
	chan->dma.cur = chan->dma.put;
	chan->dma.free = chan->dma.max - chan->dma.cur;

	ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
	if (ret)
		return ret;

	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
		OUT_RING(chan, 0x00000000);

	/* allocate software object class (used for fences on <= nv05) */
	if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
		ret = nvif_object_init(chan->object, NULL, 0x006e, 0x006e,
				       NULL, 0, &chan->nvsw);
		if (ret)
			return ret;

		swch = (void *)nvkm_object(&chan->nvsw)->parent;
		swch->flip = nouveau_flip_complete;
		swch->flip_data = chan;

		ret = RING_SPACE(chan, 2);
		if (ret)
			return ret;

		BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
		OUT_RING  (chan, chan->nvsw.handle);
		FIRE_RING (chan);
	}

	/* initialise synchronisation */
	save = cli->base.super;
	cli->base.super = true; /* hack until fencenv50 fixed */
	ret = nouveau_fence(chan->drm)->context_new(chan);
	cli->base.super = save;
	return ret;
}

int
nouveau_channel_new(struct nouveau_drm *drm, struct nvif_device *device,
		    u32 handle, u32 arg0, u32 arg1,
		    struct nouveau_channel **pchan)
{
	struct nouveau_cli *cli = (void *)nvif_client(&device->base);
	bool super;
	int ret;

	/* hack until fencenv50 is fixed, and agp access relaxed */
	super = cli->base.super;
	cli->base.super = true;

	ret = nouveau_channel_ind(drm, device, handle, arg0, pchan);
	if (ret) {
		NV_PRINTK(debug, cli, "ib channel create, %d\n", ret);
		ret = nouveau_channel_dma(drm, device, handle, pchan);
		if (ret) {
			NV_PRINTK(debug, cli, "dma channel create, %d\n", ret);
			goto done;
		}
	}

	ret = nouveau_channel_init(*pchan, arg0, arg1);
	if (ret) {
		NV_PRINTK(error, cli, "channel failed to initialise, %d\n", ret);
		nouveau_channel_del(pchan);
	}

done:
	cli->base.super = super;
	return ret;
}
Commit	Line	Data
ebb945a9 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
fdb751ef BS	25	#include <nvif/os.h>
	26	#include <nvif/class.h>
	27
	28	/XXX/
ebb945a9	29	#include <core/client.h>
ebb945a9	30
ebb945a9 BS	31	#include "nouveau_drm.h"
	32	#include "nouveau_dma.h"
	33	#include "nouveau_bo.h"
	34	#include "nouveau_chan.h"
	35	#include "nouveau_fence.h"
	36	#include "nouveau_abi16.h"
	37
	38	MODULE_PARM_DESC(vram_pushbuf, "Create DMA push buffers in VRAM");
703fa264	39	int nouveau_vram_pushbuf;
ebb945a9 BS	40	module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400);
	41
	42	int
	43	nouveau_channel_idle(struct nouveau_channel *chan)
	44	{
0ad72863	45	struct nouveau_cli cli = (void )nvif_client(chan->object);
ebb945a9 BS	46	struct nouveau_fence *fence = NULL;
	47	int ret;
	48
264ce192	49	ret = nouveau_fence_new(chan, false, &fence);
ebb945a9 BS	50	if (!ret) {
	51	ret = nouveau_fence_wait(fence, false, false);
	52	nouveau_fence_unref(&fence);
	53	}
	54
	55	if (ret)
fa2bade9	56	NV_PRINTK(error, cli, "failed to idle channel 0x%08x [%s]\n",
0ad72863	57	chan->object->handle, nvkm_client(&cli->base)->name);
ebb945a9 BS	58	return ret;
	59	}
	60
	61	void
	62	nouveau_channel_del(struct nouveau_channel **pchan)
	63	{
	64	struct nouveau_channel chan = pchan;
	65	if (chan) {
ebb945a9 BS	66	if (chan->fence) {
	67	nouveau_channel_idle(chan);
	68	nouveau_fence(chan->drm)->context_del(chan);
	69	}
0ad72863 BS	70	nvif_object_fini(&chan->nvsw);
	71	nvif_object_fini(&chan->gart);
	72	nvif_object_fini(&chan->vram);
	73	nvif_object_ref(NULL, &chan->object);
	74	nvif_object_fini(&chan->push.ctxdma);
ebb945a9 BS	75	nouveau_bo_vma_del(chan->push.buffer, &chan->push.vma);
ebb945a9 BS	76	nouveau_bo_unmap(chan->push.buffer);
124ea297 MS	77	if (chan->push.buffer && chan->push.buffer->pin_refcnt)
124ea297 MS	78	nouveau_bo_unpin(chan->push.buffer);
ebb945a9	79	nouveau_bo_ref(NULL, &chan->push.buffer);
0ad72863	80	nvif_device_ref(NULL, &chan->device);
ebb945a9 BS	81	kfree(chan);
	82	}
	83	*pchan = NULL;
	84	}
	85
	86	static int
0ad72863 BS	87	nouveau_channel_prep(struct nouveau_drm drm, struct nvif_device device,
0ad72863 BS	88	u32 handle, u32 size, struct nouveau_channel **pchan)
ebb945a9	89	{
0ad72863	90	struct nouveau_cli cli = (void )nvif_client(&device->base);
967e7bde	91	struct nouveau_vmmgr *vmm = nvkm_vmmgr(device);
4acfd707	92	struct nv_dma_v0 args = {};
ebb945a9	93	struct nouveau_channel *chan;
ebb945a9 BS	94	u32 target;
	95	int ret;
	96
	97	chan = pchan = kzalloc(sizeof(chan), GFP_KERNEL);
	98	if (!chan)
	99	return -ENOMEM;
	100
0ad72863	101	nvif_device_ref(device, &chan->device);
ebb945a9	102	chan->drm = drm;
ebb945a9 BS	103
	104	/* allocate memory for dma push buffer */
	105	target = TTM_PL_FLAG_TT;
	106	if (nouveau_vram_pushbuf)
	107	target = TTM_PL_FLAG_VRAM;
	108
bb6178b0	109	ret = nouveau_bo_new(drm->dev, size, 0, target, 0, 0, NULL, NULL,
ebb945a9 BS	110	&chan->push.buffer);
	111	if (ret == 0) {
	112	ret = nouveau_bo_pin(chan->push.buffer, target);
	113	if (ret == 0)
	114	ret = nouveau_bo_map(chan->push.buffer);
	115	}
	116
	117	if (ret) {
	118	nouveau_channel_del(pchan);
	119	return ret;
	120	}
	121
	122	/* create dma object covering the entire memory space that the
	123	* pushbuf lives in, this is because the GEM code requires that
	124	* we be able to call out to other (indirect) push buffers
	125	*/
	126	chan->push.vma.offset = chan->push.buffer->bo.offset;
ebb945a9	127
967e7bde	128	if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
0ad72863	129	ret = nouveau_bo_vma_add(chan->push.buffer, cli->vm,
ebb945a9 BS	130	&chan->push.vma);
	131	if (ret) {
	132	nouveau_channel_del(pchan);
	133	return ret;
	134	}
	135
4acfd707 BS	136	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	137	args.access = NV_DMA_V0_ACCESS_VM;
ebb945a9	138	args.start = 0;
0ad72863	139	args.limit = cli->vm->vmm->limit - 1;
ebb945a9 BS	140	} else
ebb945a9 BS	141	if (chan->push.buffer->bo.mem.mem_type == TTM_PL_VRAM) {
967e7bde	142	if (device->info.family == NV_DEVICE_INFO_V0_TNT) {
ebb945a9 BS	143	/* nv04 vram pushbuf hack, retarget to its location in
	144	* the framebuffer bar rather than direct vram access..
	145	* nfi why this exists, it came from the -nv ddx.
	146	*/
4acfd707 BS	147	args.target = NV_DMA_V0_TARGET_PCI;
4acfd707 BS	148	args.access = NV_DMA_V0_ACCESS_RDWR;
967e7bde	149	args.start = nv_device_resource_start(nvkm_device(device), 1);
f392ec4b	150	args.limit = args.start + device->info.ram_user - 1;
ebb945a9	151	} else {
4acfd707 BS	152	args.target = NV_DMA_V0_TARGET_VRAM;
4acfd707 BS	153	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9	154	args.start = 0;
f392ec4b	155	args.limit = device->info.ram_user - 1;
ebb945a9 BS	156	}
	157	} else {
	158	if (chan->drm->agp.stat == ENABLED) {
4acfd707 BS	159	args.target = NV_DMA_V0_TARGET_AGP;
4acfd707 BS	160	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9 BS	161	args.start = chan->drm->agp.base;
	162	args.limit = chan->drm->agp.base +
	163	chan->drm->agp.size - 1;
	164	} else {
4acfd707 BS	165	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	166	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9 BS	167	args.start = 0;
	168	args.limit = vmm->limit - 1;
	169	}
	170	}
	171
0ad72863	172	ret = nvif_object_init(nvif_object(device), NULL, NVDRM_PUSH \|
4acfd707	173	(handle & 0xffff), NV_DMA_FROM_MEMORY,
0ad72863	174	&args, sizeof(args), &chan->push.ctxdma);
ebb945a9 BS	175	if (ret) {
	176	nouveau_channel_del(pchan);
	177	return ret;
	178	}
	179
	180	return 0;
	181	}
	182
5b8a43ae	183	static int
0ad72863 BS	184	nouveau_channel_ind(struct nouveau_drm drm, struct nvif_device device,
0ad72863 BS	185	u32 handle, u32 engine, struct nouveau_channel **pchan)
ebb945a9	186	{
bbf8906b BS	187	static const u16 oclasses[] = { KEPLER_CHANNEL_GPFIFO_A,
	188	FERMI_CHANNEL_GPFIFO,
	189	G82_CHANNEL_GPFIFO,
	190	NV50_CHANNEL_GPFIFO,
c97f8c92	191	0 };
ebb945a9	192	const u16 *oclass = oclasses;
bbf8906b BS	193	union {
	194	struct nv50_channel_gpfifo_v0 nv50;
	195	struct kepler_channel_gpfifo_a_v0 kepler;
	196	} args, *retn;
ebb945a9	197	struct nouveau_channel *chan;
bbf8906b	198	u32 size;
ebb945a9 BS	199	int ret;
	200
	201	/* allocate dma push buffer */
0ad72863	202	ret = nouveau_channel_prep(drm, device, handle, 0x12000, &chan);
ebb945a9 BS	203	*pchan = chan;
	204	if (ret)
	205	return ret;
	206
	207	/* create channel object */
ebb945a9	208	do {
bbf8906b BS	209	if (oclass[0] >= KEPLER_CHANNEL_GPFIFO_A) {
	210	args.kepler.version = 0;
	211	args.kepler.engine = engine;
	212	args.kepler.pushbuf = chan->push.ctxdma.handle;
	213	args.kepler.ilength = 0x02000;
	214	args.kepler.ioffset = 0x10000 + chan->push.vma.offset;
	215	size = sizeof(args.kepler);
	216	} else {
	217	args.nv50.version = 0;
	218	args.nv50.pushbuf = chan->push.ctxdma.handle;
	219	args.nv50.ilength = 0x02000;
	220	args.nv50.ioffset = 0x10000 + chan->push.vma.offset;
	221	size = sizeof(args.nv50);
	222	}
	223
0ad72863	224	ret = nvif_object_new(nvif_object(device), handle, *oclass++,
bbf8906b BS	225	&args, size, &chan->object);
	226	if (ret == 0) {
	227	retn = chan->object->data;
	228	if (chan->object->oclass >= KEPLER_CHANNEL_GPFIFO_A)
	229	chan->chid = retn->kepler.chid;
	230	else
	231	chan->chid = retn->nv50.chid;
ebb945a9	232	return ret;
bbf8906b	233	}
ebb945a9 BS	234	} while (*oclass);
	235
	236	nouveau_channel_del(pchan);
	237	return ret;
	238	}
	239
	240	static int
0ad72863 BS	241	nouveau_channel_dma(struct nouveau_drm drm, struct nvif_device device,
0ad72863 BS	242	u32 handle, struct nouveau_channel **pchan)
ebb945a9	243	{
bbf8906b BS	244	static const u16 oclasses[] = { NV40_CHANNEL_DMA,
	245	NV17_CHANNEL_DMA,
	246	NV10_CHANNEL_DMA,
	247	NV03_CHANNEL_DMA,
c97f8c92	248	0 };
ebb945a9	249	const u16 *oclass = oclasses;
bbf8906b	250	struct nv03_channel_dma_v0 args, *retn;
ebb945a9 BS	251	struct nouveau_channel *chan;
	252	int ret;
	253
	254	/* allocate dma push buffer */
0ad72863	255	ret = nouveau_channel_prep(drm, device, handle, 0x10000, &chan);
ebb945a9 BS	256	*pchan = chan;
	257	if (ret)
	258	return ret;
	259
	260	/* create channel object */
bbf8906b	261	args.version = 0;
0ad72863	262	args.pushbuf = chan->push.ctxdma.handle;
ebb945a9 BS	263	args.offset = chan->push.vma.offset;
	264
	265	do {
0ad72863	266	ret = nvif_object_new(nvif_object(device), handle, *oclass++,
bbf8906b BS	267	&args, sizeof(args), &chan->object);
	268	if (ret == 0) {
	269	retn = chan->object->data;
	270	chan->chid = retn->chid;
ebb945a9	271	return ret;
bbf8906b	272	}
ebb945a9 BS	273	} while (ret && *oclass);
	274
	275	nouveau_channel_del(pchan);
	276	return ret;
	277	}
	278
	279	static int
	280	nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart)
	281	{
0ad72863 BS	282	struct nvif_device *device = chan->device;
0ad72863 BS	283	struct nouveau_cli cli = (void )nvif_client(&device->base);
967e7bde	284	struct nouveau_vmmgr *vmm = nvkm_vmmgr(device);
ebb945a9	285	struct nouveau_software_chan *swch;
4acfd707	286	struct nv_dma_v0 args = {};
ebb945a9	287	int ret, i;
f2f9a2cb	288	bool save;
ebb945a9	289
6c6ae061 BS	290	nvif_object_map(chan->object);
6c6ae061 BS	291
ebb945a9	292	/* allocate dma objects to cover all allowed vram, and gart */
967e7bde BS	293	if (device->info.family < NV_DEVICE_INFO_V0_FERMI) {
967e7bde BS	294	if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
4acfd707 BS	295	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	296	args.access = NV_DMA_V0_ACCESS_VM;
ebb945a9	297	args.start = 0;
0ad72863	298	args.limit = cli->vm->vmm->limit - 1;
ebb945a9	299	} else {
4acfd707 BS	300	args.target = NV_DMA_V0_TARGET_VRAM;
4acfd707 BS	301	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9	302	args.start = 0;
f392ec4b	303	args.limit = device->info.ram_user - 1;
ebb945a9 BS	304	}
ebb945a9 BS	305
0ad72863	306	ret = nvif_object_init(chan->object, NULL, vram,
4acfd707	307	NV_DMA_IN_MEMORY, &args,
0ad72863	308	sizeof(args), &chan->vram);
ebb945a9 BS	309	if (ret)
	310	return ret;
	311
967e7bde	312	if (device->info.family >= NV_DEVICE_INFO_V0_TESLA) {
4acfd707 BS	313	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	314	args.access = NV_DMA_V0_ACCESS_VM;
ebb945a9	315	args.start = 0;
0ad72863	316	args.limit = cli->vm->vmm->limit - 1;
ebb945a9 BS	317	} else
ebb945a9 BS	318	if (chan->drm->agp.stat == ENABLED) {
4acfd707 BS	319	args.target = NV_DMA_V0_TARGET_AGP;
4acfd707 BS	320	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9 BS	321	args.start = chan->drm->agp.base;
	322	args.limit = chan->drm->agp.base +
	323	chan->drm->agp.size - 1;
	324	} else {
4acfd707 BS	325	args.target = NV_DMA_V0_TARGET_VM;
4acfd707 BS	326	args.access = NV_DMA_V0_ACCESS_RDWR;
ebb945a9 BS	327	args.start = 0;
	328	args.limit = vmm->limit - 1;
	329	}
	330
0ad72863	331	ret = nvif_object_init(chan->object, NULL, gart,
4acfd707	332	NV_DMA_IN_MEMORY, &args,
0ad72863	333	sizeof(args), &chan->gart);
ebb945a9 BS	334	if (ret)
	335	return ret;
	336	}
	337
	338	/* initialise dma tracking parameters */
0ad72863	339	switch (chan->object->oclass & 0x00ff) {
503b0f1c	340	case 0x006b:
ebb945a9 BS	341	case 0x006e:
	342	chan->user_put = 0x40;
	343	chan->user_get = 0x44;
	344	chan->dma.max = (0x10000 / 4) - 2;
	345	break;
	346	default:
	347	chan->user_put = 0x40;
	348	chan->user_get = 0x44;
	349	chan->user_get_hi = 0x60;
	350	chan->dma.ib_base = 0x10000 / 4;
	351	chan->dma.ib_max = (0x02000 / 8) - 1;
	352	chan->dma.ib_put = 0;
	353	chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
	354	chan->dma.max = chan->dma.ib_base;
	355	break;
	356	}
	357
	358	chan->dma.put = 0;
	359	chan->dma.cur = chan->dma.put;
	360	chan->dma.free = chan->dma.max - chan->dma.cur;
	361
	362	ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
	363	if (ret)
	364	return ret;
	365
	366	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
	367	OUT_RING(chan, 0x00000000);
	368
69a6146d	369	/* allocate software object class (used for fences on <= nv05) */
967e7bde	370	if (device->info.family < NV_DEVICE_INFO_V0_CELSIUS) {
f45f55c4	371	ret = nvif_object_init(chan->object, NULL, 0x006e, 0x006e,
0ad72863	372	NULL, 0, &chan->nvsw);
49981046 BS	373	if (ret)
49981046 BS	374	return ret;
ebb945a9	375
0ad72863	376	swch = (void *)nvkm_object(&chan->nvsw)->parent;
49981046 BS	377	swch->flip = nouveau_flip_complete;
49981046 BS	378	swch->flip_data = chan;
ebb945a9	379
ebb945a9 BS	380	ret = RING_SPACE(chan, 2);
	381	if (ret)
	382	return ret;
	383
	384	BEGIN_NV04(chan, NvSubSw, 0x0000, 1);
f45f55c4	385	OUT_RING (chan, chan->nvsw.handle);
ebb945a9 BS	386	FIRE_RING (chan);
	387	}
	388
	389	/* initialise synchronisation */
f2f9a2cb BS	390	save = cli->base.super;
	391	cli->base.super = true; /* hack until fencenv50 fixed */
	392	ret = nouveau_fence(chan->drm)->context_new(chan);
	393	cli->base.super = save;
	394	return ret;
ebb945a9 BS	395	}
	396
	397	int
0ad72863 BS	398	nouveau_channel_new(struct nouveau_drm drm, struct nvif_device device,
0ad72863 BS	399	u32 handle, u32 arg0, u32 arg1,
ebb945a9 BS	400	struct nouveau_channel **pchan)
ebb945a9 BS	401	{
0ad72863	402	struct nouveau_cli cli = (void )nvif_client(&device->base);
67e26e41	403	bool super;
ebb945a9 BS	404	int ret;
ebb945a9 BS	405
67e26e41 BS	406	/* hack until fencenv50 is fixed, and agp access relaxed */
	407	super = cli->base.super;
	408	cli->base.super = true;
	409
0ad72863	410	ret = nouveau_channel_ind(drm, device, handle, arg0, pchan);
ebb945a9	411	if (ret) {
fa2bade9	412	NV_PRINTK(debug, cli, "ib channel create, %d\n", ret);
0ad72863	413	ret = nouveau_channel_dma(drm, device, handle, pchan);
ebb945a9	414	if (ret) {
fa2bade9	415	NV_PRINTK(debug, cli, "dma channel create, %d\n", ret);
67e26e41	416	goto done;
ebb945a9 BS	417	}
	418	}
	419
49981046	420	ret = nouveau_channel_init(*pchan, arg0, arg1);
ebb945a9	421	if (ret) {
fa2bade9	422	NV_PRINTK(error, cli, "channel failed to initialise, %d\n", ret);
ebb945a9	423	nouveau_channel_del(pchan);
ebb945a9 BS	424	}
ebb945a9 BS	425
67e26e41 BS	426	done:
	427	cli->base.super = super;
	428	return ret;
ebb945a9	429	}