[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_dp.c

/*
 * Copyright 2009 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"
#include "drm_dp_helper.h"

#include "nouveau_drv.h"
#include "nouveau_connector.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"

u8 *
nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry)
{
	struct bit_entry d;
	u8 *table;
	int i;

	if (bit_table(dev, 'd', &d)) {
		NV_ERROR(dev, "BIT 'd' table not found\n");
		return NULL;
	}

	if (d.version != 1) {
		NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version);
		return NULL;
	}

	table = ROMPTR(dev, d.data[0]);
	if (!table) {
		NV_ERROR(dev, "displayport table pointer invalid\n");
		return NULL;
	}

	switch (table[0]) {
	case 0x20:
	case 0x21:
	case 0x30:
	case 0x40:
		break;
	default:
		NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]);
		return NULL;
	}

	for (i = 0; i < table[3]; i++) {
		*entry = ROMPTR(dev, table[table[1] + (i * table[2])]);
		if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
			return table;
	}

	NV_ERROR(dev, "displayport encoder table not found\n");
	return NULL;
}

/******************************************************************************
 * link training
 *****************************************************************************/
struct dp_state {
	struct nouveau_i2c_port *auxch;
	struct dp_train_func *func;
	struct dcb_output *dcb;
	int crtc;
	u8 *dpcd;
	int link_nr;
	u32 link_bw;
	u8  stat[6];
	u8  conf[4];
};

static void
dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
{
	u8 sink[2];

	NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);

	/* set desired link configuration on the source */
	dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
			   dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);

	/* inform the sink of the new configuration */
	sink[0] = dp->link_bw / 27000;
	sink[1] = dp->link_nr;
	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
		sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	auxch_wr(dev, dp->auxch, DP_LINK_BW_SET, sink, 2);
}

static void
dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
{
	u8 sink_tp;

	NV_DEBUG_KMS(dev, "training pattern %d\n", pattern);

	dp->func->train_set(dev, dp->dcb, pattern);

	auxch_rd(dev, dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
	sink_tp |= pattern;
	auxch_wr(dev, dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
}

static int
dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
{
	int i;

	for (i = 0; i < dp->link_nr; i++) {
		u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
		u8 lpre = (lane & 0x0c) >> 2;
		u8 lvsw = (lane & 0x03) >> 0;

		dp->conf[i] = (lpre << 3) | lvsw;
		if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
			dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
		if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
			dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

		NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
		dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
	}

	return auxch_wr(dev, dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
}

static int
dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
{
	int ret;

	udelay(delay);

	ret = auxch_rd(dev, dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
	if (ret)
		return ret;

	NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
		     dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
		     dp->stat[4], dp->stat[5]);
	return 0;
}

static int
dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
{
	bool cr_done = false, abort = false;
	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);

	do {
		if (dp_link_train_commit(dev, dp) ||
		    dp_link_train_update(dev, dp, 100))
			break;

		cr_done = true;
		for (i = 0; i < dp->link_nr; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE)) {
				cr_done = false;
				if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
					abort = true;
				break;
			}
		}

		if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
			voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
			tries = 0;
		}
	} while (!cr_done && !abort && ++tries < 5);

	return cr_done ? 0 : -1;
}

static int
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
{
	bool eq_done, cr_done = true;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);

	do {
		if (dp_link_train_update(dev, dp, 400))
			break;

		eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
		for (i = 0; i < dp->link_nr && eq_done; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE))
				cr_done = false;
			if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
			    !(lane & DP_LANE_SYMBOL_LOCKED))
				eq_done = false;
		}

		if (dp_link_train_commit(dev, dp))
			break;
	} while (!eq_done && cr_done && ++tries <= 5);

	return eq_done ? 0 : -1;
}

static void
dp_set_downspread(struct drm_device *dev, struct dp_state *dp, bool enable)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30) {
			if (enable) script = ROM16(entry[12]);
			else        script = ROM16(entry[14]);
		} else
		if (table[0] == 0x40) {
			if (enable) script = ROM16(entry[11]);
			else        script = ROM16(entry[13]);
		}
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

static void
dp_link_train_init(struct drm_device *dev, struct dp_state *dp)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30)
			script = ROM16(entry[6]);
		else
		if (table[0] == 0x40)
			script = ROM16(entry[5]);
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

static void
dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30)
			script = ROM16(entry[8]);
		else
		if (table[0] == 0x40)
			script = ROM16(entry[7]);
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

bool
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
		      struct dp_train_func *func)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nouveau_connector *nv_connector =
		nouveau_encoder_connector_get(nv_encoder);
	struct drm_device *dev = encoder->dev;
	const u32 bw_list[] = { 270000, 162000, 0 };
	const u32 *link_bw = bw_list;
	struct dp_state dp;

	dp.auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	if (!dp.auxch)
		return false;

	dp.func = func;
	dp.dcb = nv_encoder->dcb;
	dp.crtc = nv_crtc->index;
	dp.dpcd = nv_encoder->dp.dpcd;

	/* adjust required bandwidth for 8B/10B coding overhead */
	datarate = (datarate / 8) * 10;

	/* some sinks toggle hotplug in response to some of the actions
	 * we take during link training (DP_SET_POWER is one), we need
	 * to ignore them for the moment to avoid races.
	 */
	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false);

	/* enable down-spreading, if possible */
	dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);

	/* execute pre-train script from vbios */
	dp_link_train_init(dev, &dp);

	/* start off at highest link rate supported by encoder and display */
	while (*link_bw > nv_encoder->dp.link_bw)
		link_bw++;

	while (link_bw[0]) {
		/* find minimum required lane count at this link rate */
		dp.link_nr = nv_encoder->dp.link_nr;
		while ((dp.link_nr >> 1) * link_bw[0] > datarate)
			dp.link_nr >>= 1;

		/* drop link rate to minimum with this lane count */
		while ((link_bw[1] * dp.link_nr) > datarate)
			link_bw++;
		dp.link_bw = link_bw[0];

		/* program selected link configuration */
		dp_set_link_config(dev, &dp);

		/* attempt to train the link at this configuration */
		memset(dp.stat, 0x00, sizeof(dp.stat));
		if (!dp_link_train_cr(dev, &dp) &&
		    !dp_link_train_eq(dev, &dp))
			break;

		/* retry at lower rate */
		link_bw++;
	}

	/* finish link training */
	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);

	/* execute post-train script from vbios */
	dp_link_train_fini(dev, &dp);

	/* re-enable hotplug detect */
	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true);
	return true;
}

void
nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
		struct dp_train_func *func)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_i2c_port *auxch;
	u8 status;

	auxch = nouveau_i2c_find(encoder->dev, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return;

	if (mode == DRM_MODE_DPMS_ON)
		status = DP_SET_POWER_D0;
	else
		status = DP_SET_POWER_D3;

	auxch_wr(encoder->dev, auxch, DP_SET_POWER, &status, 1);

	if (mode == DRM_MODE_DPMS_ON)
		nouveau_dp_link_train(encoder, datarate, func);
}

static void
nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch,
		     u8 *dpcd)
{
	u8 buf[3];

	if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

	if (!auxch_rd(dev, auxch, DP_SINK_OUI, buf, 3))
		NV_DEBUG_KMS(dev, "Sink OUI: %02hx%02hx%02hx\n",
			     buf[0], buf[1], buf[2]);

	if (!auxch_rd(dev, auxch, DP_BRANCH_OUI, buf, 3))
		NV_DEBUG_KMS(dev, "Branch OUI: %02hx%02hx%02hx\n",
			     buf[0], buf[1], buf[2]);

}

bool
nouveau_dp_detect(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_i2c_port *auxch;
	u8 *dpcd = nv_encoder->dp.dpcd;
	int ret;

	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return false;

	ret = auxch_rd(dev, auxch, DP_DPCD_REV, dpcd, 8);
	if (ret)
		return false;

	nv_encoder->dp.link_bw = 27000 * dpcd[1];
	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;

	NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
	NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
		     nv_encoder->dcb->dpconf.link_nr,
		     nv_encoder->dcb->dpconf.link_bw);

	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
		nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
		nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;

	NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);

	nouveau_dp_probe_oui(dev, auxch, dpcd);

	return true;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2009 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
4196faa8	26	#include "drm_dp_helper.h"
b01f0608	27
6ee73861	28	#include "nouveau_drv.h"
b01f0608	29	#include "nouveau_connector.h"
6ee73861	30	#include "nouveau_encoder.h"
27a45987	31	#include "nouveau_crtc.h"
6ee73861	32
5f1800bd	33	u8 *
cb75d97e	34	nouveau_dp_bios_data(struct drm_device dev, struct dcb_output dcb, u8 **entry)
5f1800bd	35	{
5f1800bd BS	36	struct bit_entry d;
	37	u8 *table;
	38	int i;
	39
	40	if (bit_table(dev, 'd', &d)) {
	41	NV_ERROR(dev, "BIT 'd' table not found\n");
	42	return NULL;
	43	}
	44
	45	if (d.version != 1) {
	46	NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version);
	47	return NULL;
	48	}
	49
f9f9f536	50	table = ROMPTR(dev, d.data[0]);
5f1800bd BS	51	if (!table) {
	52	NV_ERROR(dev, "displayport table pointer invalid\n");
	53	return NULL;
	54	}
	55
	56	switch (table[0]) {
	57	case 0x20:
	58	case 0x21:
c16a3a35	59	case 0x30:
65445992	60	case 0x40:
5f1800bd BS	61	break;
	62	default:
	63	NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]);
	64	return NULL;
	65	}
	66
	67	for (i = 0; i < table[3]; i++) {
f9f9f536	68	entry = ROMPTR(dev, table[table[1] + (i table[2])]);
5f1800bd BS	69	if (entry && bios_encoder_match(dcb, ROM32((entry)[0])))
	70	return table;
	71	}
	72
	73	NV_ERROR(dev, "displayport encoder table not found\n");
	74	return NULL;
	75	}
	76
27a45987 BS	77	/******************************************************************************
	78	* link training
	79	*****************************************************************************/
	80	struct dp_state {
4196faa8	81	struct nouveau_i2c_port *auxch;
8663bc7c	82	struct dp_train_func *func;
cb75d97e	83	struct dcb_output *dcb;
27a45987	84	int crtc;
52e0d0ec	85	u8 *dpcd;
27a45987 BS	86	int link_nr;
	87	u32 link_bw;
	88	u8 stat[6];
	89	u8 conf[4];
	90	};
6ee73861	91
27a45987 BS	92	static void
27a45987 BS	93	dp_set_link_config(struct drm_device dev, struct dp_state dp)
6ee73861	94	{
8663bc7c	95	u8 sink[2];
6ee73861	96
27a45987	97	NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
6ee73861	98
8663bc7c BS	99	/* set desired link configuration on the source */
	100	dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
	101	dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);
28e2d124	102
8663bc7c BS	103	/* inform the sink of the new configuration */
8663bc7c BS	104	sink[0] = dp->link_bw / 27000;
27a45987	105	sink[1] = dp->link_nr;
8663bc7c	106	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
27a45987	107	sink[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
6ee73861	108
4196faa8	109	auxch_wr(dev, dp->auxch, DP_LINK_BW_SET, sink, 2);
6ee73861 BS	110	}
6ee73861 BS	111
27a45987	112	static void
8663bc7c	113	dp_set_training_pattern(struct drm_device dev, struct dp_state dp, u8 pattern)
6ee73861	114	{
5b3eb95f BS	115	u8 sink_tp;
5b3eb95f BS	116
8663bc7c	117	NV_DEBUG_KMS(dev, "training pattern %d\n", pattern);
5b3eb95f	118
8663bc7c	119	dp->func->train_set(dev, dp->dcb, pattern);
5b3eb95f	120
4196faa8	121	auxch_rd(dev, dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
5b3eb95f	122	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
8663bc7c	123	sink_tp \|= pattern;
4196faa8	124	auxch_wr(dev, dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
6ee73861 BS	125	}
	126
	127	static int
27a45987	128	dp_link_train_commit(struct drm_device dev, struct dp_state dp)
6ee73861	129	{
27a45987 BS	130	int i;
27a45987 BS	131
27a45987	132	for (i = 0; i < dp->link_nr; i++) {
c16a3a35 BS	133	u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
	134	u8 lpre = (lane & 0x0c) >> 2;
	135	u8 lvsw = (lane & 0x03) >> 0;
6ee73861	136
c16a3a35 BS	137	dp->conf[i] = (lpre << 3) \| lvsw;
c16a3a35 BS	138	if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
27a45987	139	dp->conf[i] \|= DP_TRAIN_MAX_SWING_REACHED;
44ab8cc5	140	if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
27a45987	141	dp->conf[i] \|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
6ee73861	142
27a45987	143	NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
8663bc7c	144	dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
6ee73861 BS	145	}
6ee73861 BS	146
4196faa8	147	return auxch_wr(dev, dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
6ee73861 BS	148	}
6ee73861 BS	149
27a45987 BS	150	static int
27a45987 BS	151	dp_link_train_update(struct drm_device dev, struct dp_state dp, u32 delay)
6ee73861	152	{
27a45987	153	int ret;
6ee73861	154
27a45987	155	udelay(delay);
6ee73861	156
4196faa8	157	ret = auxch_rd(dev, dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
6ee73861	158	if (ret)
27a45987	159	return ret;
6ee73861	160
27a45987 BS	161	NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
	162	dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
	163	dp->stat[4], dp->stat[5]);
	164	return 0;
	165	}
6ee73861	166
27a45987 BS	167	static int
	168	dp_link_train_cr(struct drm_device dev, struct dp_state dp)
	169	{
	170	bool cr_done = false, abort = false;
	171	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	172	int tries = 0, i;
6ee73861	173
27a45987	174	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
6ee73861	175
27a45987 BS	176	do {
	177	if (dp_link_train_commit(dev, dp) \|\|
	178	dp_link_train_update(dev, dp, 100))
	179	break;
6ee73861	180
27a45987 BS	181	cr_done = true;
	182	for (i = 0; i < dp->link_nr; i++) {
	183	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	184	if (!(lane & DP_LANE_CR_DONE)) {
	185	cr_done = false;
	186	if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
	187	abort = true;
	188	break;
	189	}
	190	}
6ee73861	191
27a45987 BS	192	if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
	193	voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	194	tries = 0;
	195	}
	196	} while (!cr_done && !abort && ++tries < 5);
6ee73861	197
27a45987	198	return cr_done ? 0 : -1;
6ee73861 BS	199	}
6ee73861 BS	200
27a45987 BS	201	static int
27a45987 BS	202	dp_link_train_eq(struct drm_device dev, struct dp_state dp)
6ee73861	203	{
27a45987 BS	204	bool eq_done, cr_done = true;
27a45987 BS	205	int tries = 0, i;
6ee73861	206
27a45987	207	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
6ee73861	208
27a45987 BS	209	do {
27a45987 BS	210	if (dp_link_train_update(dev, dp, 400))
6ee73861	211	break;
6ee73861	212
27a45987 BS	213	eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
	214	for (i = 0; i < dp->link_nr && eq_done; i++) {
	215	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	216	if (!(lane & DP_LANE_CR_DONE))
	217	cr_done = false;
	218	if (!(lane & DP_LANE_CHANNEL_EQ_DONE) \|\|
	219	!(lane & DP_LANE_SYMBOL_LOCKED))
	220	eq_done = false;
	221	}
6ee73861	222
27a45987 BS	223	if (dp_link_train_commit(dev, dp))
	224	break;
	225	} while (!eq_done && cr_done && ++tries <= 5);
	226
	227	return eq_done ? 0 : -1;
6ee73861 BS	228	}
6ee73861 BS	229
8c1dcb65 BS	230	static void
	231	dp_set_downspread(struct drm_device dev, struct dp_state dp, bool enable)
	232	{
	233	u16 script = 0x0000;
	234	u8 entry, table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	235	if (table) {
	236	if (table[0] >= 0x20 && table[0] <= 0x30) {
6e83fda2 BS	237	if (enable) script = ROM16(entry[12]);
6e83fda2 BS	238	else script = ROM16(entry[14]);
65445992 BS	239	} else
	240	if (table[0] == 0x40) {
	241	if (enable) script = ROM16(entry[11]);
	242	else script = ROM16(entry[13]);
8c1dcb65 BS	243	}
	244	}
	245
	246	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	247	}
	248
	249	static void
	250	dp_link_train_init(struct drm_device dev, struct dp_state dp)
	251	{
	252	u16 script = 0x0000;
	253	u8 entry, table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	254	if (table) {
	255	if (table[0] >= 0x20 && table[0] <= 0x30)
	256	script = ROM16(entry[6]);
65445992 BS	257	else
	258	if (table[0] == 0x40)
	259	script = ROM16(entry[5]);
8c1dcb65 BS	260	}
	261
	262	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	263	}
	264
	265	static void
	266	dp_link_train_fini(struct drm_device dev, struct dp_state dp)
	267	{
	268	u16 script = 0x0000;
	269	u8 entry, table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	270	if (table) {
	271	if (table[0] >= 0x20 && table[0] <= 0x30)
	272	script = ROM16(entry[8]);
65445992 BS	273	else
	274	if (table[0] == 0x40)
	275	script = ROM16(entry[7]);
8c1dcb65 BS	276	}
	277
	278	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	279	}
	280
6ee73861	281	bool
8663bc7c BS	282	nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
8663bc7c BS	283	struct dp_train_func *func)
6ee73861	284	{
6ee73861	285	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
27a45987 BS	286	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	287	struct nouveau_connector *nv_connector =
	288	nouveau_encoder_connector_get(nv_encoder);
	289	struct drm_device *dev = encoder->dev;
27a45987 BS	290	const u32 bw_list[] = { 270000, 162000, 0 };
	291	const u32 *link_bw = bw_list;
	292	struct dp_state dp;
6ee73861	293
4196faa8 BS	294	dp.auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
4196faa8 BS	295	if (!dp.auxch)
6ee73861 BS	296	return false;
6ee73861 BS	297
8663bc7c	298	dp.func = func;
27a45987 BS	299	dp.dcb = nv_encoder->dcb;
27a45987 BS	300	dp.crtc = nv_crtc->index;
52e0d0ec	301	dp.dpcd = nv_encoder->dp.dpcd;
6ee73861	302
6860dc82 BS	303	/* adjust required bandwidth for 8B/10B coding overhead */
	304	datarate = (datarate / 8) * 10;
	305
27a45987 BS	306	/* some sinks toggle hotplug in response to some of the actions
	307	* we take during link training (DP_SET_POWER is one), we need
	308	* to ignore them for the moment to avoid races.
	309	*/
a0b25635	310	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false);
6ee73861	311
52e0d0ec	312	/* enable down-spreading, if possible */
8c1dcb65	313	dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
52e0d0ec	314
27a45987	315	/* execute pre-train script from vbios */
8c1dcb65	316	dp_link_train_init(dev, &dp);
6ee73861	317
27a45987	318	/* start off at highest link rate supported by encoder and display */
75a1fccf	319	while (*link_bw > nv_encoder->dp.link_bw)
27a45987	320	link_bw++;
6ee73861	321
27a45987 BS	322	while (link_bw[0]) {
	323	/* find minimum required lane count at this link rate */
	324	dp.link_nr = nv_encoder->dp.link_nr;
	325	while ((dp.link_nr >> 1) * link_bw[0] > datarate)
	326	dp.link_nr >>= 1;
6ee73861	327
27a45987 BS	328	/* drop link rate to minimum with this lane count */
	329	while ((link_bw[1] * dp.link_nr) > datarate)
	330	link_bw++;
	331	dp.link_bw = link_bw[0];
6ee73861	332
27a45987 BS	333	/* program selected link configuration */
27a45987 BS	334	dp_set_link_config(dev, &dp);
6ee73861	335
27a45987 BS	336	/* attempt to train the link at this configuration */
	337	memset(dp.stat, 0x00, sizeof(dp.stat));
	338	if (!dp_link_train_cr(dev, &dp) &&
	339	!dp_link_train_eq(dev, &dp))
6ee73861 BS	340	break;
6ee73861 BS	341
27a45987 BS	342	/* retry at lower rate */
27a45987 BS	343	link_bw++;
6ee73861 BS	344	}
6ee73861 BS	345
27a45987 BS	346	/* finish link training */
27a45987 BS	347	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
6ee73861	348
27a45987	349	/* execute post-train script from vbios */
8c1dcb65	350	dp_link_train_fini(dev, &dp);
ea4718d1	351
b01f0608	352	/* re-enable hotplug detect */
a0b25635	353	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true);
27a45987	354	return true;
6ee73861 BS	355	}
6ee73861 BS	356
f14d9a4d BS	357	void
	358	nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
	359	struct dp_train_func *func)
	360	{
	361	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
4196faa8	362	struct nouveau_i2c_port *auxch;
f14d9a4d BS	363	u8 status;
	364
	365	auxch = nouveau_i2c_find(encoder->dev, nv_encoder->dcb->i2c_index);
	366	if (!auxch)
	367	return;
	368
	369	if (mode == DRM_MODE_DPMS_ON)
	370	status = DP_SET_POWER_D0;
	371	else
	372	status = DP_SET_POWER_D3;
	373
4196faa8	374	auxch_wr(encoder->dev, auxch, DP_SET_POWER, &status, 1);
f14d9a4d BS	375
	376	if (mode == DRM_MODE_DPMS_ON)
	377	nouveau_dp_link_train(encoder, datarate, func);
	378	}
	379
6225ee05	380	static void
4196faa8	381	nouveau_dp_probe_oui(struct drm_device dev, struct nouveau_i2c_port auxch,
6225ee05 AJ	382	u8 *dpcd)
	383	{
	384	u8 buf[3];
	385
	386	if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
	387	return;
	388
4196faa8	389	if (!auxch_rd(dev, auxch, DP_SINK_OUI, buf, 3))
6225ee05 AJ	390	NV_DEBUG_KMS(dev, "Sink OUI: %02hx%02hx%02hx\n",
	391	buf[0], buf[1], buf[2]);
	392
4196faa8	393	if (!auxch_rd(dev, auxch, DP_BRANCH_OUI, buf, 3))
6225ee05 AJ	394	NV_DEBUG_KMS(dev, "Branch OUI: %02hx%02hx%02hx\n",
	395	buf[0], buf[1], buf[2]);
	396
	397	}
	398
6ee73861 BS	399	bool
	400	nouveau_dp_detect(struct drm_encoder *encoder)
	401	{
	402	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	403	struct drm_device *dev = encoder->dev;
4196faa8	404	struct nouveau_i2c_port *auxch;
52e0d0ec	405	u8 *dpcd = nv_encoder->dp.dpcd;
6ee73861 BS	406	int ret;
6ee73861 BS	407
52e0d0ec BS	408	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	409	if (!auxch)
	410	return false;
	411
4196faa8	412	ret = auxch_rd(dev, auxch, DP_DPCD_REV, dpcd, 8);
6ee73861 BS	413	if (ret)
	414	return false;
	415
75a1fccf BS	416	nv_encoder->dp.link_bw = 27000 * dpcd[1];
75a1fccf BS	417	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
6ee73861	418
75a1fccf BS	419	NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
	420	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
	421	NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
	422	nv_encoder->dcb->dpconf.link_nr,
	423	nv_encoder->dcb->dpconf.link_bw);
6ee73861	424
75a1fccf	425	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
6ee73861	426	nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
75a1fccf BS	427	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
75a1fccf BS	428	nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
6ee73861	429
75a1fccf BS	430	NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
75a1fccf BS	431	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
fe224bb7	432
6225ee05 AJ	433	nouveau_dp_probe_oui(dev, auxch, dpcd);
6225ee05 AJ	434
6ee73861 BS	435	return true;
6ee73861 BS	436	}