[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_dp.c

/*
 * Copyright 2009 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"

#include "nouveau_drv.h"
#include "nouveau_i2c.h"
#include "nouveau_connector.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"

/******************************************************************************
 * aux channel util functions
 *****************************************************************************/
#define AUX_DBG(fmt, args...) do {                                             \
	if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) {                     \
		NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args);     \
	}                                                                      \
} while (0)
#define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)

static void
auxch_fini(struct drm_device *dev, int ch)
{
	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
}

static int
auxch_init(struct drm_device *dev, int ch)
{
	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
	const u32 urep = unksel ? 0x01000000 : 0x02000000;
	u32 ctrl, timeout;

	/* wait up to 1ms for any previous transaction to be done... */
	timeout = 1000;
	do {
		ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
		udelay(1);
		if (!timeout--) {
			AUX_ERR("begin idle timeout 0x%08x", ctrl);
			return -EBUSY;
		}
	} while (ctrl & 0x03010000);

	/* set some magic, and wait up to 1ms for it to appear */
	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
	timeout = 1000;
	do {
		ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
		udelay(1);
		if (!timeout--) {
			AUX_ERR("magic wait 0x%08x\n", ctrl);
			auxch_fini(dev, ch);
			return -EBUSY;
		}
	} while ((ctrl & 0x03000000) != urep);

	return 0;
}

static int
auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
{
	u32 ctrl, stat, timeout, retries;
	u32 xbuf[4] = {};
	int ret, i;

	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);

	ret = auxch_init(dev, ch);
	if (ret)
		goto out;

	stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
	if (!(stat & 0x10000000)) {
		AUX_DBG("sink not detected\n");
		ret = -ENXIO;
		goto out;
	}

	if (!(type & 1)) {
		memcpy(xbuf, data, size);
		for (i = 0; i < 16; i += 4) {
			AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
			nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
		}
	}

	ctrl  = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
	ctrl &= ~0x0001f0ff;
	ctrl |= type << 12;
	ctrl |= size - 1;
	nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);

	/* retry transaction a number of times on failure... */
	ret = -EREMOTEIO;
	for (retries = 0; retries < 32; retries++) {
		/* reset, and delay a while if this is a retry */
		nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
		nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
		if (retries)
			udelay(400);

		/* transaction request, wait up to 1ms for it to complete */
		nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);

		timeout = 1000;
		do {
			ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
			udelay(1);
			if (!timeout--) {
				AUX_ERR("tx req timeout 0x%08x\n", ctrl);
				goto out;
			}
		} while (ctrl & 0x00010000);

		/* read status, and check if transaction completed ok */
		stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
		if (!(stat & 0x000f0f00)) {
			ret = 0;
			break;
		}

		AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
	}

	if (type & 1) {
		for (i = 0; i < 16; i += 4) {
			xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
			AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
		}
		memcpy(data, xbuf, size);
	}

out:
	auxch_fini(dev, ch);
	return ret;
}

static int
auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
{
	struct drm_device *dev = encoder->dev;
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_i2c_chan *auxch;
	int ret;

	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return -ENODEV;

	ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
	if (ret)
		return ret;

	return 0;
}

static u32
dp_link_bw_get(struct drm_device *dev, int or, int link)
{
	u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
	if (!(ctrl & 0x000c0000))
		return 162000;
	return 270000;
}

static int
dp_lane_count_get(struct drm_device *dev, int or, int link)
{
	u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
	switch (ctrl & 0x000f0000) {
	case 0x00010000: return 1;
	case 0x00030000: return 2;
	default:
		return 4;
	}
}

void
nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
{
	const u32 symbol = 100000;
	int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
	int TU, VTUi, VTUf, VTUa;
	u64 link_data_rate, link_ratio, unk;
	u32 best_diff = 64 * symbol;
	u32 link_nr, link_bw, r;

	/* calculate packed data rate for each lane */
	link_nr = dp_lane_count_get(dev, or, link);
	link_data_rate = (clk * bpp / 8) / link_nr;

	/* calculate ratio of packed data rate to link symbol rate */
	link_bw = dp_link_bw_get(dev, or, link);
	link_ratio = link_data_rate * symbol;
	r = do_div(link_ratio, link_bw);

	for (TU = 64; TU >= 32; TU--) {
		/* calculate average number of valid symbols in each TU */
		u32 tu_valid = link_ratio * TU;
		u32 calc, diff;

		/* find a hw representation for the fraction.. */
		VTUi = tu_valid / symbol;
		calc = VTUi * symbol;
		diff = tu_valid - calc;
		if (diff) {
			if (diff >= (symbol / 2)) {
				VTUf = symbol / (symbol - diff);
				if (symbol - (VTUf * diff))
					VTUf++;

				if (VTUf <= 15) {
					VTUa  = 1;
					calc += symbol - (symbol / VTUf);
				} else {
					VTUa  = 0;
					VTUf  = 1;
					calc += symbol;
				}
			} else {
				VTUa  = 0;
				VTUf  = min((int)(symbol / diff), 15);
				calc += symbol / VTUf;
			}

			diff = calc - tu_valid;
		} else {
			/* no remainder, but the hw doesn't like the fractional
			 * part to be zero.  decrement the integer part and
			 * have the fraction add a whole symbol back
			 */
			VTUa = 0;
			VTUf = 1;
			VTUi--;
		}

		if (diff < best_diff) {
			best_diff = diff;
			bestTU = TU;
			bestVTUa = VTUa;
			bestVTUf = VTUf;
			bestVTUi = VTUi;
			if (diff == 0)
				break;
		}
	}

	if (!bestTU) {
		NV_ERROR(dev, "DP: unable to find suitable config\n");
		return;
	}

	/* XXX close to vbios numbers, but not right */
	unk  = (symbol - link_ratio) * bestTU;
	unk *= link_ratio;
	r = do_div(unk, symbol);
	r = do_div(unk, symbol);
	unk += 6;

	nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
	nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 |
							     bestVTUf << 16 |
							     bestVTUi << 8 |
							     unk);
}

/******************************************************************************
 * link training
 *****************************************************************************/
struct dp_state {
	struct dcb_entry *dcb;
	int auxch;
	int crtc;
	int or;
	int link;
	int enh_frame;
	int link_nr;
	u32 link_bw;
	u8  stat[6];
	u8  conf[4];
};

static void
dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int or = dp->or, link = dp->link;
	u8 *bios, headerlen, sink[2];
	u32 dp_ctrl;

	NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);

	/* set selected link rate on source */
	switch (dp->link_bw) {
	case 270000:
		nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000);
		sink[0] = DP_LINK_BW_2_7;
		break;
	default:
		nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000);
		sink[0] = DP_LINK_BW_1_62;
		break;
	}

	/* offset +0x0a of each dp encoder table entry is a pointer to another
	 * table, that has (among other things) pointers to more scripts that
	 * need to be executed, this time depending on link speed.
	 */
	bios = nouveau_bios_dp_table(dev, dp->dcb, &headerlen);
	if (bios && (bios = ROMPTR(&dev_priv->vbios, bios[10]))) {
		u16 script = ROM16(bios[2]);
		if (dp->link_bw != 270000)
			script = ROM16(bios[6]);

		nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	}

	/* configure lane count on the source */
	dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
	sink[1] = dp->link_nr;
	if (dp->enh_frame) {
		dp_ctrl |= 0x00004000;
		sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	}

	nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);

	/* inform the sink of the new configuration */
	auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
}

static void
dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp)
{
	NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
	nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
	auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &tp, 1);
}

static int
dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
{
	u32 mask = 0, drv = 0, pre = 0, unk = 0;
	u8  shifts[4] = { 16, 8, 0, 24 };
	u8  *bios, *last, headerlen;
	int link = dp->link;
	int or = dp->or;
	int i;

	bios = nouveau_bios_dp_table(dev, dp->dcb, &headerlen);
	last = bios + headerlen + (bios[4] * 5);
	for (i = 0; i < dp->link_nr; i++) {
		u8  lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
		u8 *conf = bios + headerlen;

		while (conf < last) {
			if ((lane  & 3) == conf[0] &&
			    (lane >> 2) == conf[1])
				break;
			conf += 5;
		}

		if (conf == last)
			return -EINVAL;

		dp->conf[i] = (conf[1] << 3) | conf[0];
		if (conf[0] == DP_TRAIN_VOLTAGE_SWING_1200)
			dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
		if (conf[1] == DP_TRAIN_PRE_EMPHASIS_9_5)
			dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

		NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);

		mask |= 0xff << shifts[i];
		drv  |= conf[2] << shifts[i];
		pre  |= conf[3] << shifts[i];
		unk   = (unk & ~0x0000ff00) | (conf[4] << 8);
		unk  |= 1 << (shifts[i] >> 3);
	}

	nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
	nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
	nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);

	return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
}

static int
dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
{
	int ret;

	udelay(delay);

	ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
	if (ret)
		return ret;

	NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
		     dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
		     dp->stat[4], dp->stat[5]);
	return 0;
}

static int
dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
{
	bool cr_done = false, abort = false;
	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);

	do {
		if (dp_link_train_commit(dev, dp) ||
		    dp_link_train_update(dev, dp, 100))
			break;

		cr_done = true;
		for (i = 0; i < dp->link_nr; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE)) {
				cr_done = false;
				if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
					abort = true;
				break;
			}
		}

		if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
			voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
			tries = 0;
		}
	} while (!cr_done && !abort && ++tries < 5);

	return cr_done ? 0 : -1;
}

static int
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
{
	bool eq_done, cr_done = true;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);

	do {
		if (dp_link_train_update(dev, dp, 400))
			break;

		eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
		for (i = 0; i < dp->link_nr && eq_done; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE))
				cr_done = false;
			if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
			    !(lane & DP_LANE_SYMBOL_LOCKED))
				eq_done = false;
		}

		if (dp_link_train_commit(dev, dp))
			break;
	} while (!eq_done && cr_done && ++tries <= 5);

	return eq_done ? 0 : -1;
}

bool
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
{
	struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
	struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nouveau_connector *nv_connector =
		nouveau_encoder_connector_get(nv_encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_i2c_chan *auxch;
	const u32 bw_list[] = { 270000, 162000, 0 };
	const u32 *link_bw = bw_list;
	struct dp_state dp;
	u8 *bios, headerlen;
	u16 script;

	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return false;

	bios = nouveau_bios_dp_table(dev, nv_encoder->dcb, &headerlen);
	if (!bios)
		return -EINVAL;

	dp.dcb = nv_encoder->dcb;
	dp.crtc = nv_crtc->index;
	dp.auxch = auxch->rd;
	dp.or = nv_encoder->or;
	dp.link = !(nv_encoder->dcb->sorconf.link & 1);
	dp.enh_frame = nv_encoder->dp.enhanced_frame;

	/* some sinks toggle hotplug in response to some of the actions
	 * we take during link training (DP_SET_POWER is one), we need
	 * to ignore them for the moment to avoid races.
	 */
	pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);

	/* execute pre-train script from vbios */
	nouveau_bios_run_init_table(dev, ROM16(bios[6]), dp.dcb, dp.crtc);

	/* start off at highest link rate supported by encoder and display */
	while (*link_bw > nv_encoder->dp.link_bw)
		link_bw++;

	while (link_bw[0]) {
		/* find minimum required lane count at this link rate */
		dp.link_nr = nv_encoder->dp.link_nr;
		while ((dp.link_nr >> 1) * link_bw[0] > datarate)
			dp.link_nr >>= 1;

		/* drop link rate to minimum with this lane count */
		while ((link_bw[1] * dp.link_nr) > datarate)
			link_bw++;
		dp.link_bw = link_bw[0];

		/* program selected link configuration */
		dp_set_link_config(dev, &dp);

		/* attempt to train the link at this configuration */
		memset(dp.stat, 0x00, sizeof(dp.stat));
		if (!dp_link_train_cr(dev, &dp) &&
		    !dp_link_train_eq(dev, &dp))
			break;

		/* retry at lower rate */
		link_bw++;
	}

	/* finish link training */
	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);

	/* execute post-train script from vbios */
	nouveau_bios_run_init_table(dev, ROM16(bios[8]), dp.dcb, dp.crtc);

	/* re-enable hotplug detect */
	pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true);
	return true;
}

bool
nouveau_dp_detect(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_device *dev = encoder->dev;
	uint8_t dpcd[4];
	int ret;

	ret = auxch_rd(encoder, 0x0000, dpcd, 4);
	if (ret)
		return false;

	nv_encoder->dp.dpcd_version = dpcd[0];
	nv_encoder->dp.link_bw = 27000 * dpcd[1];
	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
	nv_encoder->dp.enhanced_frame = dpcd[2] & DP_ENHANCED_FRAME_CAP;

	NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
	NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
		     nv_encoder->dcb->dpconf.link_nr,
		     nv_encoder->dcb->dpconf.link_bw);

	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
		nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
		nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;

	NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);

	return true;
}

int
nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
		 uint8_t *data, int data_nr)
{
	return auxch_tx(auxch->dev, auxch->rd, cmd, addr, data, data_nr);
}

static int
nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
	struct i2c_msg *msg = msgs;
	int ret, mcnt = num;

	while (mcnt--) {
		u8 remaining = msg->len;
		u8 *ptr = msg->buf;

		while (remaining) {
			u8 cnt = (remaining > 16) ? 16 : remaining;
			u8 cmd;

			if (msg->flags & I2C_M_RD)
				cmd = AUX_I2C_READ;
			else
				cmd = AUX_I2C_WRITE;

			if (mcnt || remaining > 16)
				cmd |= AUX_I2C_MOT;

			ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
			if (ret < 0)
				return ret;

			ptr += cnt;
			remaining -= cnt;
		}

		msg++;
	}

	return num;
}

static u32
nouveau_dp_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

const struct i2c_algorithm nouveau_dp_i2c_algo = {
	.master_xfer = nouveau_dp_i2c_xfer,
	.functionality = nouveau_dp_i2c_func
};
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2009 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
b01f0608	26
6ee73861 BS	27	#include "nouveau_drv.h"
6ee73861 BS	28	#include "nouveau_i2c.h"
b01f0608	29	#include "nouveau_connector.h"
6ee73861	30	#include "nouveau_encoder.h"
27a45987	31	#include "nouveau_crtc.h"
6ee73861	32
43720133 BS	33	/******************************************************************************
	34	* aux channel util functions
	35	*****************************************************************************/
	36	#define AUX_DBG(fmt, args...) do { \
	37	if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) { \
	38	NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args); \
	39	} \
	40	} while (0)
	41	#define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)
	42
	43	static void
	44	auxch_fini(struct drm_device *dev, int ch)
	45	{
	46	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
	47	}
	48
	49	static int
	50	auxch_init(struct drm_device *dev, int ch)
	51	{
	52	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
	53	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
	54	const u32 urep = unksel ? 0x01000000 : 0x02000000;
	55	u32 ctrl, timeout;
	56
	57	/* wait up to 1ms for any previous transaction to be done... */
	58	timeout = 1000;
	59	do {
	60	ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
	61	udelay(1);
	62	if (!timeout--) {
	63	AUX_ERR("begin idle timeout 0x%08x", ctrl);
	64	return -EBUSY;
	65	}
	66	} while (ctrl & 0x03010000);
	67
	68	/* set some magic, and wait up to 1ms for it to appear */
	69	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
	70	timeout = 1000;
	71	do {
	72	ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
	73	udelay(1);
	74	if (!timeout--) {
	75	AUX_ERR("magic wait 0x%08x\n", ctrl);
	76	auxch_fini(dev, ch);
	77	return -EBUSY;
	78	}
	79	} while ((ctrl & 0x03000000) != urep);
	80
	81	return 0;
	82	}
	83
	84	static int
	85	auxch_tx(struct drm_device dev, int ch, u8 type, u32 addr, u8 data, u8 size)
	86	{
	87	u32 ctrl, stat, timeout, retries;
	88	u32 xbuf[4] = {};
	89	int ret, i;
	90
	91	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
	92
	93	ret = auxch_init(dev, ch);
	94	if (ret)
	95	goto out;
	96
97	stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
98	if (!(stat & 0x10000000)) {
99	AUX_DBG("sink not detected\n");
100	ret = -ENXIO;
101	goto out;
102	}
103
104	if (!(type & 1)) {
105	memcpy(xbuf, data, size);
106	for (i = 0; i < 16; i += 4) {
107	AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
108	nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
109	}
110	}
111
112	ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
113	ctrl &= ~0x0001f0ff;
114	ctrl \|= type << 12;
115	ctrl \|= size - 1;
116	nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);
117
118	/* retry transaction a number of times on failure... */
119	ret = -EREMOTEIO;
120	for (retries = 0; retries < 32; retries++) {
121	/* reset, and delay a while if this is a retry */
122	nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 \| ctrl);
123	nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 \| ctrl);
124	if (retries)
125	udelay(400);
126
127	/* transaction request, wait up to 1ms for it to complete */
128	nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 \| ctrl);
129
130	timeout = 1000;
131	do {
132	ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
133	udelay(1);
134	if (!timeout--) {
135	AUX_ERR("tx req timeout 0x%08x\n", ctrl);
136	goto out;
137	}
138	} while (ctrl & 0x00010000);
139
140	/* read status, and check if transaction completed ok */
141	stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
142	if (!(stat & 0x000f0f00)) {
143	ret = 0;
144	break;
145	}
146
147	AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
148	}
149
150	if (type & 1) {
151	for (i = 0; i < 16; i += 4) {
152	xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
153	AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
154	}
155	memcpy(data, xbuf, size);
156	}
157
158	out:
159	auxch_fini(dev, ch);
160	return ret;
161	}
162
6ee73861 BS	163	static int
	164	auxch_rd(struct drm_encoder encoder, int address, uint8_t buf, int size)
	165	{
	166	struct drm_device *dev = encoder->dev;
	167	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	168	struct nouveau_i2c_chan *auxch;
	169	int ret;
	170
	171	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	172	if (!auxch)
	173	return -ENODEV;
	174
	175	ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
	176	if (ret)
	177	return ret;
	178
	179	return 0;
	180	}
	181
46959b77 BS	182	static u32
	183	dp_link_bw_get(struct drm_device *dev, int or, int link)
	184	{
	185	u32 ctrl = nv_rd32(dev, 0x614300 + (or * 0x800));
	186	if (!(ctrl & 0x000c0000))
	187	return 162000;
	188	return 270000;
	189	}
	190
	191	static int
	192	dp_lane_count_get(struct drm_device *dev, int or, int link)
	193	{
	194	u32 ctrl = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
	195	switch (ctrl & 0x000f0000) {
	196	case 0x00010000: return 1;
	197	case 0x00030000: return 2;
	198	default:
	199	return 4;
	200	}
	201	}
	202
	203	void
	204	nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
	205	{
	206	const u32 symbol = 100000;
	207	int bestTU = 0, bestVTUi = 0, bestVTUf = 0, bestVTUa = 0;
	208	int TU, VTUi, VTUf, VTUa;
	209	u64 link_data_rate, link_ratio, unk;
	210	u32 best_diff = 64 * symbol;
	211	u32 link_nr, link_bw, r;
	212
	213	/* calculate packed data rate for each lane */
	214	link_nr = dp_lane_count_get(dev, or, link);
	215	link_data_rate = (clk * bpp / 8) / link_nr;
	216
	217	/* calculate ratio of packed data rate to link symbol rate */
	218	link_bw = dp_link_bw_get(dev, or, link);
	219	link_ratio = link_data_rate * symbol;
	220	r = do_div(link_ratio, link_bw);
	221
	222	for (TU = 64; TU >= 32; TU--) {
	223	/* calculate average number of valid symbols in each TU */
	224	u32 tu_valid = link_ratio * TU;
	225	u32 calc, diff;
	226
	227	/* find a hw representation for the fraction.. */
	228	VTUi = tu_valid / symbol;
	229	calc = VTUi * symbol;
	230	diff = tu_valid - calc;
	231	if (diff) {
	232	if (diff >= (symbol / 2)) {
	233	VTUf = symbol / (symbol - diff);
	234	if (symbol - (VTUf * diff))
	235	VTUf++;
	236
	237	if (VTUf <= 15) {
	238	VTUa = 1;
	239	calc += symbol - (symbol / VTUf);
	240	} else {
	241	VTUa = 0;
	242	VTUf = 1;
	243	calc += symbol;
	244	}
	245	} else {
246	VTUa = 0;
247	VTUf = min((int)(symbol / diff), 15);
248	calc += symbol / VTUf;
249	}
250
251	diff = calc - tu_valid;
252	} else {
253	/* no remainder, but the hw doesn't like the fractional
254	* part to be zero. decrement the integer part and
255	* have the fraction add a whole symbol back
256	*/
257	VTUa = 0;
258	VTUf = 1;
259	VTUi--;
260	}
261
262	if (diff < best_diff) {
263	best_diff = diff;
264	bestTU = TU;
265	bestVTUa = VTUa;
266	bestVTUf = VTUf;
267	bestVTUi = VTUi;
268	if (diff == 0)
269	break;
270	}
271	}
272
273	if (!bestTU) {
274	NV_ERROR(dev, "DP: unable to find suitable config\n");
275	return;
276	}
277
278	/* XXX close to vbios numbers, but not right */
279	unk = (symbol - link_ratio) * bestTU;
280	unk *= link_ratio;
281	r = do_div(unk, symbol);
282	r = do_div(unk, symbol);
283	unk += 6;
284
285	nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x000001fc, bestTU << 2);
286	nv_mask(dev, NV50_SOR_DP_SCFG(or, link), 0x010f7f3f, bestVTUa << 24 \|
287	bestVTUf << 16 \|
288	bestVTUi << 8 \|
289	unk);
290	}
291
27a45987 BS	292	/******************************************************************************
	293	* link training
	294	*****************************************************************************/
	295	struct dp_state {
	296	struct dcb_entry *dcb;
	297	int auxch;
	298	int crtc;
	299	int or;
	300	int link;
	301	int enh_frame;
	302	int link_nr;
	303	u32 link_bw;
	304	u8 stat[6];
	305	u8 conf[4];
	306	};
6ee73861	307
27a45987 BS	308	static void
27a45987 BS	309	dp_set_link_config(struct drm_device dev, struct dp_state dp)
6ee73861	310	{
28e2d124	311	struct drm_nouveau_private *dev_priv = dev->dev_private;
27a45987	312	int or = dp->or, link = dp->link;
28e2d124 BS	313	u8 *bios, headerlen, sink[2];
28e2d124 BS	314	u32 dp_ctrl;
6ee73861	315
27a45987	316	NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
6ee73861	317
28e2d124	318	/* set selected link rate on source */
27a45987 BS	319	switch (dp->link_bw) {
27a45987 BS	320	case 270000:
28e2d124	321	nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00040000);
27a45987 BS	322	sink[0] = DP_LINK_BW_2_7;
	323	break;
	324	default:
28e2d124	325	nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, 0x00000000);
27a45987 BS	326	sink[0] = DP_LINK_BW_1_62;
	327	break;
	328	}
6ee73861	329
28e2d124 BS	330	/* offset +0x0a of each dp encoder table entry is a pointer to another
	331	* table, that has (among other things) pointers to more scripts that
	332	* need to be executed, this time depending on link speed.
	333	*/
	334	bios = nouveau_bios_dp_table(dev, dp->dcb, &headerlen);
	335	if (bios && (bios = ROMPTR(&dev_priv->vbios, bios[10]))) {
	336	u16 script = ROM16(bios[2]);
	337	if (dp->link_bw != 270000)
	338	script = ROM16(bios[6]);
	339
	340	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	341	}
	342
	343	/* configure lane count on the source */
27a45987 BS	344	dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
	345	sink[1] = dp->link_nr;
	346	if (dp->enh_frame) {
	347	dp_ctrl \|= 0x00004000;
	348	sink[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	349	}
6ee73861	350
27a45987	351	nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);
6ee73861	352
28e2d124	353	/* inform the sink of the new configuration */
27a45987	354	auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
6ee73861 BS	355	}
6ee73861 BS	356
27a45987 BS	357	static void
27a45987 BS	358	dp_set_training_pattern(struct drm_device dev, struct dp_state dp, u8 tp)
6ee73861	359	{
27a45987 BS	360	NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
	361	nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
	362	auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &tp, 1);
6ee73861 BS	363	}
	364
	365	static int
27a45987	366	dp_link_train_commit(struct drm_device dev, struct dp_state dp)
6ee73861	367	{
27a45987 BS	368	u32 mask = 0, drv = 0, pre = 0, unk = 0;
	369	u8 shifts[4] = { 16, 8, 0, 24 };
	370	u8 bios, last, headerlen;
	371	int link = dp->link;
	372	int or = dp->or;
	373	int i;
	374
	375	bios = nouveau_bios_dp_table(dev, dp->dcb, &headerlen);
	376	last = bios + headerlen + (bios[4] * 5);
	377	for (i = 0; i < dp->link_nr; i++) {
	378	u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
	379	u8 *conf = bios + headerlen;
	380
	381	while (conf < last) {
	382	if ((lane & 3) == conf[0] &&
	383	(lane >> 2) == conf[1])
	384	break;
	385	conf += 5;
	386	}
6ee73861	387
27a45987 BS	388	if (conf == last)
27a45987 BS	389	return -EINVAL;
6ee73861	390
27a45987 BS	391	dp->conf[i] = (conf[1] << 3) \| conf[0];
	392	if (conf[0] == DP_TRAIN_VOLTAGE_SWING_1200)
	393	dp->conf[i] \|= DP_TRAIN_MAX_SWING_REACHED;
	394	if (conf[1] == DP_TRAIN_PRE_EMPHASIS_9_5)
	395	dp->conf[i] \|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
6ee73861	396
27a45987 BS	397	NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
	398
	399	mask \|= 0xff << shifts[i];
	400	drv \|= conf[2] << shifts[i];
	401	pre \|= conf[3] << shifts[i];
	402	unk = (unk & ~0x0000ff00) \| (conf[4] << 8);
	403	unk \|= 1 << (shifts[i] >> 3);
6ee73861 BS	404	}
6ee73861 BS	405
27a45987 BS	406	nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
	407	nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
	408	nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);
	409
	410	return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
6ee73861 BS	411	}
6ee73861 BS	412
27a45987 BS	413	static int
27a45987 BS	414	dp_link_train_update(struct drm_device dev, struct dp_state dp, u32 delay)
6ee73861	415	{
27a45987	416	int ret;
6ee73861	417
27a45987	418	udelay(delay);
6ee73861	419
27a45987	420	ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
6ee73861	421	if (ret)
27a45987	422	return ret;
6ee73861	423
27a45987 BS	424	NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
	425	dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
	426	dp->stat[4], dp->stat[5]);
	427	return 0;
	428	}
6ee73861	429
27a45987 BS	430	static int
	431	dp_link_train_cr(struct drm_device dev, struct dp_state dp)
	432	{
	433	bool cr_done = false, abort = false;
	434	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	435	int tries = 0, i;
6ee73861	436
27a45987	437	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
6ee73861	438
27a45987 BS	439	do {
	440	if (dp_link_train_commit(dev, dp) \|\|
	441	dp_link_train_update(dev, dp, 100))
	442	break;
6ee73861	443
27a45987 BS	444	cr_done = true;
	445	for (i = 0; i < dp->link_nr; i++) {
	446	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	447	if (!(lane & DP_LANE_CR_DONE)) {
	448	cr_done = false;
	449	if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
	450	abort = true;
	451	break;
	452	}
	453	}
6ee73861	454
27a45987 BS	455	if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
	456	voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	457	tries = 0;
	458	}
	459	} while (!cr_done && !abort && ++tries < 5);
6ee73861	460
27a45987	461	return cr_done ? 0 : -1;
6ee73861 BS	462	}
6ee73861 BS	463
27a45987 BS	464	static int
27a45987 BS	465	dp_link_train_eq(struct drm_device dev, struct dp_state dp)
6ee73861	466	{
27a45987 BS	467	bool eq_done, cr_done = true;
27a45987 BS	468	int tries = 0, i;
6ee73861	469
27a45987	470	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
6ee73861	471
27a45987 BS	472	do {
27a45987 BS	473	if (dp_link_train_update(dev, dp, 400))
6ee73861	474	break;
6ee73861	475
27a45987 BS	476	eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
	477	for (i = 0; i < dp->link_nr && eq_done; i++) {
	478	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	479	if (!(lane & DP_LANE_CR_DONE))
	480	cr_done = false;
	481	if (!(lane & DP_LANE_CHANNEL_EQ_DONE) \|\|
	482	!(lane & DP_LANE_SYMBOL_LOCKED))
	483	eq_done = false;
	484	}
6ee73861	485
27a45987 BS	486	if (dp_link_train_commit(dev, dp))
	487	break;
	488	} while (!eq_done && cr_done && ++tries <= 5);
	489
	490	return eq_done ? 0 : -1;
6ee73861 BS	491	}
	492
	493	bool
a002fece	494	nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
6ee73861	495	{
27a45987	496	struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
ee2e0131	497	struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
6ee73861	498	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
27a45987 BS	499	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	500	struct nouveau_connector *nv_connector =
	501	nouveau_encoder_connector_get(nv_encoder);
	502	struct drm_device *dev = encoder->dev;
	503	struct nouveau_i2c_chan *auxch;
	504	const u32 bw_list[] = { 270000, 162000, 0 };
	505	const u32 *link_bw = bw_list;
	506	struct dp_state dp;
	507	u8 *bios, headerlen;
	508	u16 script;
6ee73861	509
27a45987 BS	510	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
27a45987 BS	511	if (!auxch)
6ee73861 BS	512	return false;
6ee73861 BS	513
27a45987 BS	514	bios = nouveau_bios_dp_table(dev, nv_encoder->dcb, &headerlen);
	515	if (!bios)
	516	return -EINVAL;
6ee73861	517
27a45987 BS	518	dp.dcb = nv_encoder->dcb;
	519	dp.crtc = nv_crtc->index;
	520	dp.auxch = auxch->rd;
	521	dp.or = nv_encoder->or;
	522	dp.link = !(nv_encoder->dcb->sorconf.link & 1);
	523	dp.enh_frame = nv_encoder->dp.enhanced_frame;
6ee73861	524
27a45987 BS	525	/* some sinks toggle hotplug in response to some of the actions
	526	* we take during link training (DP_SET_POWER is one), we need
	527	* to ignore them for the moment to avoid races.
	528	*/
	529	pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
6ee73861	530
27a45987 BS	531	/* execute pre-train script from vbios */
27a45987 BS	532	nouveau_bios_run_init_table(dev, ROM16(bios[6]), dp.dcb, dp.crtc);
6ee73861	533
27a45987	534	/* start off at highest link rate supported by encoder and display */
75a1fccf	535	while (*link_bw > nv_encoder->dp.link_bw)
27a45987	536	link_bw++;
6ee73861	537
27a45987 BS	538	while (link_bw[0]) {
	539	/* find minimum required lane count at this link rate */
	540	dp.link_nr = nv_encoder->dp.link_nr;
	541	while ((dp.link_nr >> 1) * link_bw[0] > datarate)
	542	dp.link_nr >>= 1;
6ee73861	543
27a45987 BS	544	/* drop link rate to minimum with this lane count */
	545	while ((link_bw[1] * dp.link_nr) > datarate)
	546	link_bw++;
	547	dp.link_bw = link_bw[0];
6ee73861	548
27a45987 BS	549	/* program selected link configuration */
27a45987 BS	550	dp_set_link_config(dev, &dp);
6ee73861	551
27a45987 BS	552	/* attempt to train the link at this configuration */
	553	memset(dp.stat, 0x00, sizeof(dp.stat));
	554	if (!dp_link_train_cr(dev, &dp) &&
	555	!dp_link_train_eq(dev, &dp))
6ee73861 BS	556	break;
6ee73861 BS	557
27a45987 BS	558	/* retry at lower rate */
27a45987 BS	559	link_bw++;
6ee73861 BS	560	}
6ee73861 BS	561
27a45987 BS	562	/* finish link training */
27a45987 BS	563	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
6ee73861	564
27a45987 BS	565	/* execute post-train script from vbios */
27a45987 BS	566	nouveau_bios_run_init_table(dev, ROM16(bios[8]), dp.dcb, dp.crtc);
ea4718d1	567
b01f0608	568	/* re-enable hotplug detect */
27a45987 BS	569	pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true);
27a45987 BS	570	return true;
6ee73861 BS	571	}
	572
	573	bool
	574	nouveau_dp_detect(struct drm_encoder *encoder)
	575	{
	576	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	577	struct drm_device *dev = encoder->dev;
	578	uint8_t dpcd[4];
	579	int ret;
	580
	581	ret = auxch_rd(encoder, 0x0000, dpcd, 4);
	582	if (ret)
	583	return false;
	584
6ee73861	585	nv_encoder->dp.dpcd_version = dpcd[0];
75a1fccf BS	586	nv_encoder->dp.link_bw = 27000 * dpcd[1];
	587	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
	588	nv_encoder->dp.enhanced_frame = dpcd[2] & DP_ENHANCED_FRAME_CAP;
6ee73861	589
75a1fccf BS	590	NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
	591	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
	592	NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
	593	nv_encoder->dcb->dpconf.link_nr,
	594	nv_encoder->dcb->dpconf.link_bw);
6ee73861	595
75a1fccf	596	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
6ee73861	597	nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
75a1fccf BS	598	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
75a1fccf BS	599	nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
6ee73861	600
75a1fccf BS	601	NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
75a1fccf BS	602	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
fe224bb7	603
6ee73861 BS	604	return true;
	605	}
	606
	607	int
	608	nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
	609	uint8_t *data, int data_nr)
	610	{
43720133	611	return auxch_tx(auxch->dev, auxch->rd, cmd, addr, data, data_nr);
6ee73861 BS	612	}
6ee73861 BS	613
c020c9a8 BS	614	static int
c020c9a8 BS	615	nouveau_dp_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
6ee73861	616	{
c020c9a8	617	struct nouveau_i2c_chan auxch = (struct nouveau_i2c_chan )adap;
c020c9a8 BS	618	struct i2c_msg *msg = msgs;
c020c9a8 BS	619	int ret, mcnt = num;
6ee73861	620
c020c9a8 BS	621	while (mcnt--) {
	622	u8 remaining = msg->len;
	623	u8 *ptr = msg->buf;
6ee73861	624
c020c9a8 BS	625	while (remaining) {
	626	u8 cnt = (remaining > 16) ? 16 : remaining;
	627	u8 cmd;
6ee73861	628
c020c9a8 BS	629	if (msg->flags & I2C_M_RD)
	630	cmd = AUX_I2C_READ;
	631	else
	632	cmd = AUX_I2C_WRITE;
	633
	634	if (mcnt \|\| remaining > 16)
	635	cmd \|= AUX_I2C_MOT;
	636
	637	ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
	638	if (ret < 0)
	639	return ret;
	640
c020c9a8 BS	641	ptr += cnt;
c020c9a8 BS	642	remaining -= cnt;
6ee73861	643	}
c020c9a8 BS	644
c020c9a8 BS	645	msg++;
6ee73861	646	}
c020c9a8 BS	647
	648	return num;
	649	}
	650
	651	static u32
	652	nouveau_dp_i2c_func(struct i2c_adapter *adap)
	653	{
	654	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
6ee73861 BS	655	}
6ee73861 BS	656
c020c9a8 BS	657	const struct i2c_algorithm nouveau_dp_i2c_algo = {
	658	.master_xfer = nouveau_dp_i2c_xfer,
	659	.functionality = nouveau_dp_i2c_func
	660	};