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drm/nouveau: kick vram functions out into an "engine"
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
274fec93 57#include "nouveau_util.h"
f869ef88 58
054b93e4 59struct nouveau_grctx;
f869ef88
BS		 60struct nouveau_vram;
61#include "nouveau_vm.h"
6ee73861
BS		 62
63#define MAX_NUM_DCB_ENTRIES 16
64
65#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 66#define NOUVEAU_MAX_TILE_NR 15
6ee73861 67
573a2a37
BS		 68struct nouveau_vram {
69 struct drm_device *dev;
70
f869ef88
BS		 71 struct nouveau_vma bar_vma;
72
573a2a37
BS		 73 struct list_head regions;
74 u32 memtype;
75 u64 offset;
76 u64 size;
77};
78
a0af9add 79struct nouveau_tile_reg {
a0af9add 80 bool used;
a5cf68b0
FJ		 81 uint32_t addr;
82 uint32_t limit;
83 uint32_t pitch;
87a326a3
FJ		 84 uint32_t zcomp;
85 struct drm_mm_node *tag_mem;
a5cf68b0 86 struct nouveau_fence *fence;
a0af9add
FJ		 87};
88
6ee73861
BS		 89struct nouveau_bo {
90 struct ttm_buffer_object bo;
91 struct ttm_placement placement;
92 u32 placements[3];
78ad0f7b 93 u32 busy_placements[3];
6ee73861
BS		 94 struct ttm_bo_kmap_obj kmap;
95 struct list_head head;
96
97 /* protected by ttm_bo_reserve() */
98 struct drm_file *reserved_by;
99 struct list_head entry;
100 int pbbo_index;
a1606a95 101 bool validate_mapped;
6ee73861
BS		 102
103 struct nouveau_channel *channel;
104
4c136142 105 struct nouveau_vma vma;
6ee73861
BS		 106 bool mappable;
107 bool no_vm;
108
109 uint32_t tile_mode;
110 uint32_t tile_flags;
a0af9add 111 struct nouveau_tile_reg *tile;
6ee73861
BS		 112
113 struct drm_gem_object *gem;
6ee73861
BS		 114 int pin_refcnt;
115};
116
f13b3263
FJ		 117#define nouveau_bo_tile_layout(nvbo) \
118 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
119
6ee73861
BS		 120static inline struct nouveau_bo *
121nouveau_bo(struct ttm_buffer_object *bo)
122{
123 return container_of(bo, struct nouveau_bo, bo);
124}
125
126static inline struct nouveau_bo *
127nouveau_gem_object(struct drm_gem_object *gem)
128{
129 return gem ? gem->driver_private : NULL;
130}
131
132/* TODO: submit equivalent to TTM generic API upstream? */
133static inline void __iomem *
134nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
135{
136 bool is_iomem;
137 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
138 &nvbo->kmap, &is_iomem);
139 WARN_ON_ONCE(ioptr && !is_iomem);
140 return ioptr;
141}
142
6ee73861
BS		 143enum nouveau_flags {
144 NV_NFORCE = 0x10000000,
145 NV_NFORCE2 = 0x20000000
146};
147
148#define NVOBJ_ENGINE_SW 0
149#define NVOBJ_ENGINE_GR 1
bd2e597d
BS		 150#define NVOBJ_ENGINE_PPP 2
151#define NVOBJ_ENGINE_COPY 3
152#define NVOBJ_ENGINE_VP 4
153#define NVOBJ_ENGINE_CRYPT 5
154#define NVOBJ_ENGINE_BSP 6
50536946 155#define NVOBJ_ENGINE_DISPLAY 0xcafe0001
6ee73861
BS		 156#define NVOBJ_ENGINE_INT 0xdeadbeef
157
a11c3198 158#define NVOBJ_FLAG_DONT_MAP (1 << 0)
6ee73861
BS		 159#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
160#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
34cf01bc 161#define NVOBJ_FLAG_VM (1 << 3)
e41115d0
BS		 162
163#define NVOBJ_CINST_GLOBAL 0xdeadbeef
164
6ee73861 165struct nouveau_gpuobj {
b3beb167 166 struct drm_device *dev;
eb9bcbdc 167 struct kref refcount;
6ee73861
BS		 168 struct list_head list;
169
e41115d0 170 void *node;
dc1e5c0d 171 u32 *suspend;
6ee73861
BS		 172
173 uint32_t flags;
6ee73861 174
43efc9ce 175 u32 size;
de3a6c0a
BS		 176 u32 pinst;
177 u32 cinst;
178 u64 vinst;
179
6ee73861
BS		 180 uint32_t engine;
181 uint32_t class;
182
183 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
184 void *priv;
185};
186
332b242f
FJ		 187struct nouveau_page_flip_state {
188 struct list_head head;
189 struct drm_pending_vblank_event *event;
190 int crtc, bpp, pitch, x, y;
191 uint64_t offset;
192};
193
e419cf09
FJ		 194enum nouveau_channel_mutex_class {
195 NOUVEAU_UCHANNEL_MUTEX,
196 NOUVEAU_KCHANNEL_MUTEX
197};
198
6ee73861
BS		 199struct nouveau_channel {
200 struct drm_device *dev;
201 int id;
202
f091a3d4
FJ		 203 /* references to the channel data structure */
204 struct kref ref;
205 /* users of the hardware channel resources, the hardware
206 * context will be kicked off when it reaches zero. */
207 atomic_t users;
6a6b73f2
BS		 208 struct mutex mutex;
209
6ee73861
BS		 210 /* owner of this fifo */
211 struct drm_file *file_priv;
212 /* mapping of the fifo itself */
213 struct drm_local_map *map;
214
215 /* mapping of the regs controling the fifo */
216 void __iomem *user;
217 uint32_t user_get;
218 uint32_t user_put;
219
220 /* Fencing */
221 struct {
222 /* lock protects the pending list only */
223 spinlock_t lock;
224 struct list_head pending;
225 uint32_t sequence;
226 uint32_t sequence_ack;
047d1d3c 227 atomic_t last_sequence_irq;
6ee73861
BS		 228 } fence;
229
230 /* DMA push buffer */
a8eaebc6
BS		 231 struct nouveau_gpuobj *pushbuf;
232 struct nouveau_bo *pushbuf_bo;
233 uint32_t pushbuf_base;
6ee73861
BS		 234
235 /* Notifier memory */
236 struct nouveau_bo *notifier_bo;
b833ac26 237 struct drm_mm notifier_heap;
6ee73861
BS		 238
239 /* PFIFO context */
a8eaebc6
BS		 240 struct nouveau_gpuobj *ramfc;
241 struct nouveau_gpuobj *cache;
6ee73861
BS		 242
243 /* PGRAPH context */
244 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 245 struct nouveau_gpuobj *ramin_grctx;
bd2e597d 246 struct nouveau_gpuobj *crypt_ctx;
6ee73861
BS		 247 void *pgraph_ctx;
248
249 /* NV50 VM */
f869ef88 250 struct nouveau_vm *vm;
a8eaebc6 251 struct nouveau_gpuobj *vm_pd;
6ee73861
BS		 252
253 /* Objects */
a8eaebc6
BS		 254 struct nouveau_gpuobj *ramin; /* Private instmem */
255 struct drm_mm ramin_heap; /* Private PRAMIN heap */
256 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 257
258 /* GPU object info for stuff used in-kernel (mm_enabled) */
259 uint32_t m2mf_ntfy;
260 uint32_t vram_handle;
261 uint32_t gart_handle;
262 bool accel_done;
263
264 /* Push buffer state (only for drm's channel on !mm_enabled) */
265 struct {
266 int max;
267 int free;
268 int cur;
269 int put;
270 /* access via pushbuf_bo */
9a391ad8
BS		 271
272 int ib_base;
273 int ib_max;
274 int ib_free;
275 int ib_put;
6ee73861
BS		 276 } dma;
277
278 uint32_t sw_subchannel[8];
279
280 struct {
281 struct nouveau_gpuobj *vblsem;
1f6d2de2 282 uint32_t vblsem_head;
6ee73861
BS		 283 uint32_t vblsem_offset;
284 uint32_t vblsem_rval;
285 struct list_head vbl_wait;
332b242f 286 struct list_head flip;
6ee73861
BS		 287 } nvsw;
288
289 struct {
290 bool active;
291 char name[32];
292 struct drm_info_list info;
293 } debugfs;
294};
295
296struct nouveau_instmem_engine {
297 void *priv;
298
299 int (*init)(struct drm_device *dev);
300 void (*takedown)(struct drm_device *dev);
301 int (*suspend)(struct drm_device *dev);
302 void (*resume)(struct drm_device *dev);
303
e41115d0
BS		 304 int (*get)(struct nouveau_gpuobj *, u32 size, u32 align);
305 void (*put)(struct nouveau_gpuobj *);
306 int (*map)(struct nouveau_gpuobj *);
307 void (*unmap)(struct nouveau_gpuobj *);
308
f56cb86f 309 void (*flush)(struct drm_device *);
6ee73861
BS		 310};
311
312struct nouveau_mc_engine {
313 int (*init)(struct drm_device *dev);
314 void (*takedown)(struct drm_device *dev);
315};
316
317struct nouveau_timer_engine {
318 int (*init)(struct drm_device *dev);
319 void (*takedown)(struct drm_device *dev);
320 uint64_t (*read)(struct drm_device *dev);
321};
322
323struct nouveau_fb_engine {
cb00f7c1 324 int num_tiles;
87a326a3 325 struct drm_mm tag_heap;
20f63afe 326 void *priv;
cb00f7c1 327
6ee73861
BS		 328 int (*init)(struct drm_device *dev);
329 void (*takedown)(struct drm_device *dev);
cb00f7c1 330
a5cf68b0
FJ		 331 void (*init_tile_region)(struct drm_device *dev, int i,
332 uint32_t addr, uint32_t size,
333 uint32_t pitch, uint32_t flags);
334 void (*set_tile_region)(struct drm_device *dev, int i);
335 void (*free_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 336};
337
338struct nouveau_fifo_engine {
6ee73861
BS		 339 int channels;
340
a8eaebc6 341 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 342 int cur_playlist;
343
6ee73861
BS		 344 int (*init)(struct drm_device *);
345 void (*takedown)(struct drm_device *);
346
347 void (*disable)(struct drm_device *);
348 void (*enable)(struct drm_device *);
349 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 350 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 351
352 int (*channel_id)(struct drm_device *);
353
354 int (*create_context)(struct nouveau_channel *);
355 void (*destroy_context)(struct nouveau_channel *);
356 int (*load_context)(struct nouveau_channel *);
357 int (*unload_context)(struct drm_device *);
56ac7475 358 void (*tlb_flush)(struct drm_device *dev);
6ee73861
BS		 359};
360
6ee73861 361struct nouveau_pgraph_engine {
6ee73861 362 bool accel_blocked;
b8c157d3 363 bool registered;
054b93e4 364 int grctx_size;
6ee73861 365
c50a5681 366 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 367 struct nouveau_gpuobj *ctx_table;
c50a5681 368
6ee73861
BS		 369 int (*init)(struct drm_device *);
370 void (*takedown)(struct drm_device *);
371
372 void (*fifo_access)(struct drm_device *, bool);
373
374 struct nouveau_channel *(*channel)(struct drm_device *);
375 int (*create_context)(struct nouveau_channel *);
376 void (*destroy_context)(struct nouveau_channel *);
377 int (*load_context)(struct nouveau_channel *);
378 int (*unload_context)(struct drm_device *);
56ac7475 379 void (*tlb_flush)(struct drm_device *dev);
cb00f7c1 380
a5cf68b0 381 void (*set_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 382};
383
c88c2e06
FJ		 384struct nouveau_display_engine {
385 int (*early_init)(struct drm_device *);
386 void (*late_takedown)(struct drm_device *);
387 int (*create)(struct drm_device *);
388 int (*init)(struct drm_device *);
389 void (*destroy)(struct drm_device *);
390};
391
ee2e0131 392struct nouveau_gpio_engine {
fce2bad0
BS		 393 void *priv;
394
ee2e0131
BS		 395 int (*init)(struct drm_device *);
396 void (*takedown)(struct drm_device *);
397
398 int (*get)(struct drm_device *, enum dcb_gpio_tag);
399 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
400
fce2bad0
BS		 401 int (*irq_register)(struct drm_device *, enum dcb_gpio_tag,
402 void (*)(void *, int), void *);
403 void (*irq_unregister)(struct drm_device *, enum dcb_gpio_tag,
404 void (*)(void *, int), void *);
405 bool (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
ee2e0131
BS		 406};
407
330c5988
BS		 408struct nouveau_pm_voltage_level {
409 u8 voltage;
410 u8 vid;
411};
412
413struct nouveau_pm_voltage {
414 bool supported;
415 u8 vid_mask;
416
417 struct nouveau_pm_voltage_level *level;
418 int nr_level;
419};
420
421#define NOUVEAU_PM_MAX_LEVEL 8
422struct nouveau_pm_level {
423 struct device_attribute dev_attr;
424 char name[32];
425 int id;
426
427 u32 core;
428 u32 memory;
429 u32 shader;
430 u32 unk05;
431
432 u8 voltage;
433 u8 fanspeed;
aee582de
BS		 434
435 u16 memscript;
330c5988
BS		 436};
437
34e9d85a
MP		 438struct nouveau_pm_temp_sensor_constants {
439 u16 offset_constant;
440 s16 offset_mult;
441 u16 offset_div;
442 u16 slope_mult;
443 u16 slope_div;
444};
445
446struct nouveau_pm_threshold_temp {
447 s16 critical;
448 s16 down_clock;
449 s16 fan_boost;
450};
451
7760fcb0
RS		 452struct nouveau_pm_memtiming {
453 u32 reg_100220;
454 u32 reg_100224;
455 u32 reg_100228;
456 u32 reg_10022c;
457 u32 reg_100230;
458 u32 reg_100234;
459 u32 reg_100238;
460 u32 reg_10023c;
461};
462
463struct nouveau_pm_memtimings {
464 bool supported;
465 struct nouveau_pm_memtiming *timing;
466 int nr_timing;
467};
468
330c5988
BS		 469struct nouveau_pm_engine {
470 struct nouveau_pm_voltage voltage;
471 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
472 int nr_perflvl;
7760fcb0 473 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 474 struct nouveau_pm_temp_sensor_constants sensor_constants;
475 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 476
477 struct nouveau_pm_level boot;
478 struct nouveau_pm_level *cur;
479
8155cac4 480 struct device *hwmon;
6032649d 481 struct notifier_block acpi_nb;
8155cac4 482
330c5988 483 int (*clock_get)(struct drm_device *, u32 id);
5c6dc657
BS		 484 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
485 u32 id, int khz);
330c5988
BS		 486 void (*clock_set)(struct drm_device *, void *);
487 int (*voltage_get)(struct drm_device *);
488 int (*voltage_set)(struct drm_device *, int voltage);
489 int (*fanspeed_get)(struct drm_device *);
490 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 491 int (*temp_get)(struct drm_device *);
330c5988
BS		 492};
493
bd2e597d
BS		 494struct nouveau_crypt_engine {
495 bool registered;
496
497 int (*init)(struct drm_device *);
498 void (*takedown)(struct drm_device *);
499 int (*create_context)(struct nouveau_channel *);
500 void (*destroy_context)(struct nouveau_channel *);
501 void (*tlb_flush)(struct drm_device *dev);
502};
503
60d2a88a
BS		 504struct nouveau_vram_engine {
505 int (*init)(struct drm_device *);
506 int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
507 u32 type, struct nouveau_vram **);
508 void (*put)(struct drm_device *, struct nouveau_vram **);
509
510 bool (*flags_valid)(struct drm_device *, u32 tile_flags);
511};
512
6ee73861
BS		 513struct nouveau_engine {
514 struct nouveau_instmem_engine instmem;
515 struct nouveau_mc_engine mc;
516 struct nouveau_timer_engine timer;
517 struct nouveau_fb_engine fb;
518 struct nouveau_pgraph_engine graph;
519 struct nouveau_fifo_engine fifo;
c88c2e06 520 struct nouveau_display_engine display;
ee2e0131 521 struct nouveau_gpio_engine gpio;
330c5988 522 struct nouveau_pm_engine pm;
bd2e597d 523 struct nouveau_crypt_engine crypt;
60d2a88a 524 struct nouveau_vram_engine vram;
6ee73861
BS		 525};
526
527struct nouveau_pll_vals {
528 union {
529 struct {
530#ifdef __BIG_ENDIAN
531 uint8_t N1, M1, N2, M2;
532#else
533 uint8_t M1, N1, M2, N2;
534#endif
535 };
536 struct {
537 uint16_t NM1, NM2;
538 } __attribute__((packed));
539 };
540 int log2P;
541
542 int refclk;
543};
544
545enum nv04_fp_display_regs {
546 FP_DISPLAY_END,
547 FP_TOTAL,
548 FP_CRTC,
549 FP_SYNC_START,
550 FP_SYNC_END,
551 FP_VALID_START,
552 FP_VALID_END
553};
554
555struct nv04_crtc_reg {
cbab95db 556 unsigned char MiscOutReg;
4a9f822f 557 uint8_t CRTC[0xa0];
6ee73861
BS		 558 uint8_t CR58[0x10];
559 uint8_t Sequencer[5];
560 uint8_t Graphics[9];
561 uint8_t Attribute[21];
cbab95db 562 unsigned char DAC[768];
6ee73861
BS		 563
564 /* PCRTC regs */
565 uint32_t fb_start;
566 uint32_t crtc_cfg;
567 uint32_t cursor_cfg;
568 uint32_t gpio_ext;
569 uint32_t crtc_830;
570 uint32_t crtc_834;
571 uint32_t crtc_850;
572 uint32_t crtc_eng_ctrl;
573
574 /* PRAMDAC regs */
575 uint32_t nv10_cursync;
576 struct nouveau_pll_vals pllvals;
577 uint32_t ramdac_gen_ctrl;
578 uint32_t ramdac_630;
579 uint32_t ramdac_634;
580 uint32_t tv_setup;
581 uint32_t tv_vtotal;
582 uint32_t tv_vskew;
583 uint32_t tv_vsync_delay;
584 uint32_t tv_htotal;
585 uint32_t tv_hskew;
586 uint32_t tv_hsync_delay;
587 uint32_t tv_hsync_delay2;
588 uint32_t fp_horiz_regs[7];
589 uint32_t fp_vert_regs[7];
590 uint32_t dither;
591 uint32_t fp_control;
592 uint32_t dither_regs[6];
593 uint32_t fp_debug_0;
594 uint32_t fp_debug_1;
595 uint32_t fp_debug_2;
596 uint32_t fp_margin_color;
597 uint32_t ramdac_8c0;
598 uint32_t ramdac_a20;
599 uint32_t ramdac_a24;
600 uint32_t ramdac_a34;
601 uint32_t ctv_regs[38];
602};
603
604struct nv04_output_reg {
605 uint32_t output;
606 int head;
607};
608
609struct nv04_mode_state {
cbab95db 610 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS		 611 uint32_t pllsel;
612 uint32_t sel_clk;
6ee73861
BS		 613};
614
615enum nouveau_card_type {
616 NV_04 = 0x00,
617 NV_10 = 0x10,
618 NV_20 = 0x20,
619 NV_30 = 0x30,
620 NV_40 = 0x40,
621 NV_50 = 0x50,
4b223eef 622 NV_C0 = 0xc0,
6ee73861
BS		 623};
624
625struct drm_nouveau_private {
626 struct drm_device *dev;
6ee73861
BS		 627
628 /* the card type, takes NV_* as values */
629 enum nouveau_card_type card_type;
630 /* exact chipset, derived from NV_PMC_BOOT_0 */
631 int chipset;
632 int flags;
633
634 void __iomem *mmio;
5125bfd8 635
e05d7eae 636 spinlock_t ramin_lock;
6ee73861 637 void __iomem *ramin;
5125bfd8
BS		 638 u32 ramin_size;
639 u32 ramin_base;
640 bool ramin_available;
e05d7eae
BS		 641 struct drm_mm ramin_heap;
642 struct list_head gpuobj_list;
b8c157d3 643 struct list_head classes;
6ee73861 644
ac8fb975
BS		 645 struct nouveau_bo *vga_ram;
646
35fa2f2a 647 /* interrupt handling */
8f8a5448 648 void (*irq_handler[32])(struct drm_device *);
35fa2f2a 649 bool msi_enabled;
6ee73861
BS		 650 struct workqueue_struct *wq;
651 struct work_struct irq_work;
ab838338 652
6ee73861
BS		 653 struct list_head vbl_waiting;
654
655 struct {
ba4420c2 656 struct drm_global_reference mem_global_ref;
6ee73861
BS		 657 struct ttm_bo_global_ref bo_global_ref;
658 struct ttm_bo_device bdev;
6ee73861
BS		 659 atomic_t validate_sequence;
660 } ttm;
661
0c6c1c2f
FJ		 662 struct {
663 spinlock_t lock;
664 struct drm_mm heap;
665 struct nouveau_bo *bo;
666 } fence;
667
cff5c133
BS		 668 struct {
669 spinlock_t lock;
670 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
671 } channels;
6ee73861
BS		 672
673 struct nouveau_engine engine;
674 struct nouveau_channel *channel;
675
ff9e5279
MM		 676 /* For PFIFO and PGRAPH. */
677 spinlock_t context_switch_lock;
678
6ee73861 679 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 680 struct nouveau_ramht *ramht;
681 struct nouveau_gpuobj *ramfc;
682 struct nouveau_gpuobj *ramro;
683
6ee73861 684 uint32_t ramin_rsvd_vram;
6ee73861 685
6ee73861
BS		 686 struct {
687 enum {
688 NOUVEAU_GART_NONE = 0,
689 NOUVEAU_GART_AGP,
690 NOUVEAU_GART_SGDMA
691 } type;
692 uint64_t aper_base;
693 uint64_t aper_size;
694 uint64_t aper_free;
695
696 struct nouveau_gpuobj *sg_ctxdma;
b571fe21 697 struct nouveau_vma vma;
6ee73861
BS		 698 } gart_info;
699
a0af9add 700 /* nv10-nv40 tiling regions */
a5cf68b0
FJ		 701 struct {
702 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
703 spinlock_t lock;
704 } tile;
a0af9add 705
a76fb4e8
BS		 706 /* VRAM/fb configuration */
707 uint64_t vram_size;
708 uint64_t vram_sys_base;
6c3d7ef2 709 u32 vram_rblock_size;
a76fb4e8
BS		 710
711 uint64_t fb_phys;
712 uint64_t fb_available_size;
713 uint64_t fb_mappable_pages;
714 uint64_t fb_aper_free;
715 int fb_mtrr;
716
f869ef88
BS		 717 /* BAR control (NV50-) */
718 struct nouveau_vm *bar1_vm;
719 struct nouveau_vm *bar3_vm;
720
6ee73861 721 /* G8x/G9x virtual address space */
4c136142 722 struct nouveau_vm *chan_vm;
6ee73861 723
04a39c57 724 struct nvbios vbios;
6ee73861
BS		 725
726 struct nv04_mode_state mode_reg;
727 struct nv04_mode_state saved_reg;
728 uint32_t saved_vga_font[4][16384];
729 uint32_t crtc_owner;
730 uint32_t dac_users[4];
731
732 struct nouveau_suspend_resume {
6ee73861 733 uint32_t *ramin_copy;
6ee73861
BS		 734 } susres;
735
736 struct backlight_device *backlight;
6ee73861
BS		 737
738 struct nouveau_channel *evo;
1e96268a 739 u32 evo_alloc;
87c0e0e5
BS		 740 struct {
741 struct dcb_entry *dcb;
742 u16 script;
743 u32 pclk;
744 } evo_irq;
6ee73861
BS		 745
746 struct {
747 struct dentry *channel_root;
748 } debugfs;
38651674 749
8be48d92 750 struct nouveau_fbdev *nfbdev;
06415c56 751 struct apertures_struct *apertures;
6ee73861
BS		 752};
753
2730723b
FJ		 754static inline struct drm_nouveau_private *
755nouveau_private(struct drm_device *dev)
756{
757 return dev->dev_private;
758}
759
6ee73861
BS		 760static inline struct drm_nouveau_private *
761nouveau_bdev(struct ttm_bo_device *bd)
762{
763 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
764}
765
766static inline int
767nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
768{
769 struct nouveau_bo *prev;
770
771 if (!pnvbo)
772 return -EINVAL;
773 prev = *pnvbo;
774
775 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
776 if (prev) {
777 struct ttm_buffer_object *bo = &prev->bo;
778
779 ttm_bo_unref(&bo);
780 }
781
782 return 0;
783}
784
6ee73861 785/* nouveau_drv.c */
de5899bd 786extern int nouveau_agpmode;
6ee73861
BS		 787extern int nouveau_duallink;
788extern int nouveau_uscript_lvds;
789extern int nouveau_uscript_tmds;
790extern int nouveau_vram_pushbuf;
791extern int nouveau_vram_notify;
792extern int nouveau_fbpercrtc;
f4053509 793extern int nouveau_tv_disable;
6ee73861
BS		 794extern char *nouveau_tv_norm;
795extern int nouveau_reg_debug;
796extern char *nouveau_vbios;
a1470890 797extern int nouveau_ignorelid;
a32ed69d
MK		 798extern int nouveau_nofbaccel;
799extern int nouveau_noaccel;
0cba1b76 800extern int nouveau_force_post;
da647d5b 801extern int nouveau_override_conntype;
6f876986
BS		 802extern char *nouveau_perflvl;
803extern int nouveau_perflvl_wr;
35fa2f2a 804extern int nouveau_msi;
6ee73861 805
6a9ee8af
DA		 806extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
807extern int nouveau_pci_resume(struct pci_dev *pdev);
808
6ee73861
BS		 809/* nouveau_state.c */
810extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
811extern int nouveau_load(struct drm_device *, unsigned long flags);
812extern int nouveau_firstopen(struct drm_device *);
813extern void nouveau_lastclose(struct drm_device *);
814extern int nouveau_unload(struct drm_device *);
815extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
816 struct drm_file *);
817extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
818 struct drm_file *);
12fb9525
BS		 819extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
820 uint32_t reg, uint32_t mask, uint32_t val);
821extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
822 uint32_t reg, uint32_t mask, uint32_t val);
6ee73861
BS		 823extern bool nouveau_wait_for_idle(struct drm_device *);
824extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 825
826/* nouveau_mem.c */
fbd2895e
BS		 827extern int nouveau_mem_vram_init(struct drm_device *);
828extern void nouveau_mem_vram_fini(struct drm_device *);
829extern int nouveau_mem_gart_init(struct drm_device *);
830extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 831extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 832extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 833extern void nouveau_mem_close(struct drm_device *);
60d2a88a
BS		 834extern int nouveau_mem_detect(struct drm_device *);
835extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
a5cf68b0
FJ		 836extern struct nouveau_tile_reg *nv10_mem_set_tiling(
837 struct drm_device *dev, uint32_t addr, uint32_t size,
838 uint32_t pitch, uint32_t flags);
839extern void nv10_mem_put_tile_region(struct drm_device *dev,
840 struct nouveau_tile_reg *tile,
841 struct nouveau_fence *fence);
573a2a37 842extern const struct ttm_mem_type_manager_func nouveau_vram_manager;
6ee73861
BS		 843
844/* nouveau_notifier.c */
845extern int nouveau_notifier_init_channel(struct nouveau_channel *);
846extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
847extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
848 int cout, uint32_t *offset);
849extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
850extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
851 struct drm_file *);
852extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
853 struct drm_file *);
854
855/* nouveau_channel.c */
856extern struct drm_ioctl_desc nouveau_ioctls[];
857extern int nouveau_max_ioctl;
858extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
6ee73861
BS		 859extern int nouveau_channel_alloc(struct drm_device *dev,
860 struct nouveau_channel **chan,
861 struct drm_file *file_priv,
862 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
cff5c133 863extern struct nouveau_channel *
feeb0aec
FJ		 864nouveau_channel_get_unlocked(struct nouveau_channel *);
865extern struct nouveau_channel *
cff5c133 866nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
feeb0aec 867extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
cff5c133 868extern void nouveau_channel_put(struct nouveau_channel **);
f091a3d4
FJ		 869extern void nouveau_channel_ref(struct nouveau_channel *chan,
870 struct nouveau_channel **pchan);
6dccd311 871extern void nouveau_channel_idle(struct nouveau_channel *chan);
6ee73861
BS		 872
873/* nouveau_object.c */
b8c157d3
BS		 874#define NVOBJ_CLASS(d,c,e) do { \
875 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
876 if (ret) \
877 return ret; \
878} while(0)
879
880#define NVOBJ_MTHD(d,c,m,e) do { \
881 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
882 if (ret) \
883 return ret; \
884} while(0)
885
6ee73861
BS		 886extern int nouveau_gpuobj_early_init(struct drm_device *);
887extern int nouveau_gpuobj_init(struct drm_device *);
888extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861 889extern int nouveau_gpuobj_suspend(struct drm_device *dev);
6ee73861 890extern void nouveau_gpuobj_resume(struct drm_device *dev);
b8c157d3
BS		 891extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
892extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
893 int (*exec)(struct nouveau_channel *,
894 u32 class, u32 mthd, u32 data));
895extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
274fec93 896extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
6ee73861
BS		 897extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
898 uint32_t vram_h, uint32_t tt_h);
899extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
900extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
901 uint32_t size, int align, uint32_t flags,
902 struct nouveau_gpuobj **);
a8eaebc6
BS		 903extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
904 struct nouveau_gpuobj **);
43efc9ce
BS		 905extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
906 u32 size, u32 flags,
a8eaebc6 907 struct nouveau_gpuobj **);
6ee73861
BS		 908extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
909 uint64_t offset, uint64_t size, int access,
910 int target, struct nouveau_gpuobj **);
ceac3099 911extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class);
7f4a195f
BS		 912extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base,
913 u64 size, int target, int access, u32 type,
914 u32 comp, struct nouveau_gpuobj **pobj);
915extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset,
916 int class, u64 base, u64 size, int target,
917 int access, u32 type, u32 comp);
6ee73861
BS		 918extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
919 struct drm_file *);
920extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
921 struct drm_file *);
922
923/* nouveau_irq.c */
35fa2f2a
BS		 924extern int nouveau_irq_init(struct drm_device *);
925extern void nouveau_irq_fini(struct drm_device *);
6ee73861 926extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
8f8a5448
BS		 927extern void nouveau_irq_register(struct drm_device *, int status_bit,
928 void (*)(struct drm_device *));
929extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
6ee73861
BS		 930extern void nouveau_irq_preinstall(struct drm_device *);
931extern int nouveau_irq_postinstall(struct drm_device *);
932extern void nouveau_irq_uninstall(struct drm_device *);
933
934/* nouveau_sgdma.c */
935extern int nouveau_sgdma_init(struct drm_device *);
936extern void nouveau_sgdma_takedown(struct drm_device *);
937extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
938 uint32_t *page);
939extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
940
941/* nouveau_debugfs.c */
942#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
943extern int nouveau_debugfs_init(struct drm_minor *);
944extern void nouveau_debugfs_takedown(struct drm_minor *);
945extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
946extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
947#else
948static inline int
949nouveau_debugfs_init(struct drm_minor *minor)
950{
951 return 0;
952}
953
954static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
955{
956}
957
958static inline int
959nouveau_debugfs_channel_init(struct nouveau_channel *chan)
960{
961 return 0;
962}
963
964static inline void
965nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
966{
967}
968#endif
969
970/* nouveau_dma.c */
75c99da6 971extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 972extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 973extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 974
975/* nouveau_acpi.c */
afeb3e11 976#define ROM_BIOS_PAGE 4096
2f41a7f1 977#if defined(CONFIG_ACPI)
6a9ee8af
DA		 978void nouveau_register_dsm_handler(void);
979void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 980int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
981bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 982int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 983#else
984static inline void nouveau_register_dsm_handler(void) {}
985static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 986static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
987static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 988static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 989#endif
6ee73861
BS		 990
991/* nouveau_backlight.c */
992#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
993extern int nouveau_backlight_init(struct drm_device *);
994extern void nouveau_backlight_exit(struct drm_device *);
995#else
996static inline int nouveau_backlight_init(struct drm_device *dev)
997{
998 return 0;
999}
1000
1001static inline void nouveau_backlight_exit(struct drm_device *dev) { }
1002#endif
1003
1004/* nouveau_bios.c */
1005extern int nouveau_bios_init(struct drm_device *);
1006extern void nouveau_bios_takedown(struct drm_device *dev);
1007extern int nouveau_run_vbios_init(struct drm_device *);
1008extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
1009 struct dcb_entry *);
1010extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
1011 enum dcb_gpio_tag);
1012extern struct dcb_connector_table_entry *
1013nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 1014extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 1015extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
1016 struct pll_lims *);
1017extern int nouveau_bios_run_display_table(struct drm_device *,
1018 struct dcb_entry *,
1019 uint32_t script, int pxclk);
1020extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
1021 int *length);
1022extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
1023extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
1024extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
1025 bool *dl, bool *if_is_24bit);
1026extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1027 int head, int pxclk);
1028extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1029 enum LVDS_script, int pxclk);
1030
1031/* nouveau_ttm.c */
1032int nouveau_ttm_global_init(struct drm_nouveau_private *);
1033void nouveau_ttm_global_release(struct drm_nouveau_private *);
1034int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1035
1036/* nouveau_dp.c */
1037int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1038 uint8_t *data, int data_nr);
1039bool nouveau_dp_detect(struct drm_encoder *);
1040bool nouveau_dp_link_train(struct drm_encoder *);
1041
1042/* nv04_fb.c */
1043extern int nv04_fb_init(struct drm_device *);
1044extern void nv04_fb_takedown(struct drm_device *);
1045
1046/* nv10_fb.c */
1047extern int nv10_fb_init(struct drm_device *);
1048extern void nv10_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1049extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1050 uint32_t addr, uint32_t size,
1051 uint32_t pitch, uint32_t flags);
1052extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1053extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
6ee73861 1054
8bded189
FJ		 1055/* nv30_fb.c */
1056extern int nv30_fb_init(struct drm_device *);
1057extern void nv30_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1058extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1059 uint32_t addr, uint32_t size,
1060 uint32_t pitch, uint32_t flags);
1061extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
8bded189 1062
6ee73861
BS		 1063/* nv40_fb.c */
1064extern int nv40_fb_init(struct drm_device *);
1065extern void nv40_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1066extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1067
304424e1
MK		 1068/* nv50_fb.c */
1069extern int nv50_fb_init(struct drm_device *);
1070extern void nv50_fb_takedown(struct drm_device *);
d96773e7 1071extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 1072
4b223eef
BS		 1073/* nvc0_fb.c */
1074extern int nvc0_fb_init(struct drm_device *);
1075extern void nvc0_fb_takedown(struct drm_device *);
1076
6ee73861
BS		 1077/* nv04_fifo.c */
1078extern int nv04_fifo_init(struct drm_device *);
5178d40d 1079extern void nv04_fifo_fini(struct drm_device *);
6ee73861
BS		 1080extern void nv04_fifo_disable(struct drm_device *);
1081extern void nv04_fifo_enable(struct drm_device *);
1082extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 1083extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 1084extern int nv04_fifo_channel_id(struct drm_device *);
1085extern int nv04_fifo_create_context(struct nouveau_channel *);
1086extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1087extern int nv04_fifo_load_context(struct nouveau_channel *);
1088extern int nv04_fifo_unload_context(struct drm_device *);
5178d40d 1089extern void nv04_fifo_isr(struct drm_device *);
6ee73861
BS		 1090
1091/* nv10_fifo.c */
1092extern int nv10_fifo_init(struct drm_device *);
1093extern int nv10_fifo_channel_id(struct drm_device *);
1094extern int nv10_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1095extern int nv10_fifo_load_context(struct nouveau_channel *);
1096extern int nv10_fifo_unload_context(struct drm_device *);
1097
1098/* nv40_fifo.c */
1099extern int nv40_fifo_init(struct drm_device *);
1100extern int nv40_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1101extern int nv40_fifo_load_context(struct nouveau_channel *);
1102extern int nv40_fifo_unload_context(struct drm_device *);
1103
1104/* nv50_fifo.c */
1105extern int nv50_fifo_init(struct drm_device *);
1106extern void nv50_fifo_takedown(struct drm_device *);
1107extern int nv50_fifo_channel_id(struct drm_device *);
1108extern int nv50_fifo_create_context(struct nouveau_channel *);
1109extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1110extern int nv50_fifo_load_context(struct nouveau_channel *);
1111extern int nv50_fifo_unload_context(struct drm_device *);
56ac7475 1112extern void nv50_fifo_tlb_flush(struct drm_device *dev);
6ee73861 1113
4b223eef
BS		 1114/* nvc0_fifo.c */
1115extern int nvc0_fifo_init(struct drm_device *);
1116extern void nvc0_fifo_takedown(struct drm_device *);
1117extern void nvc0_fifo_disable(struct drm_device *);
1118extern void nvc0_fifo_enable(struct drm_device *);
1119extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1120extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1121extern int nvc0_fifo_channel_id(struct drm_device *);
1122extern int nvc0_fifo_create_context(struct nouveau_channel *);
1123extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1124extern int nvc0_fifo_load_context(struct nouveau_channel *);
1125extern int nvc0_fifo_unload_context(struct drm_device *);
1126
6ee73861 1127/* nv04_graph.c */
6ee73861
BS		 1128extern int nv04_graph_init(struct drm_device *);
1129extern void nv04_graph_takedown(struct drm_device *);
1130extern void nv04_graph_fifo_access(struct drm_device *, bool);
1131extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1132extern int nv04_graph_create_context(struct nouveau_channel *);
1133extern void nv04_graph_destroy_context(struct nouveau_channel *);
1134extern int nv04_graph_load_context(struct nouveau_channel *);
1135extern int nv04_graph_unload_context(struct drm_device *);
332b242f
FJ		 1136extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1137 u32 class, u32 mthd, u32 data);
274fec93 1138extern struct nouveau_bitfield nv04_graph_nsource[];
6ee73861
BS		 1139
1140/* nv10_graph.c */
6ee73861
BS		 1141extern int nv10_graph_init(struct drm_device *);
1142extern void nv10_graph_takedown(struct drm_device *);
1143extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1144extern int nv10_graph_create_context(struct nouveau_channel *);
1145extern void nv10_graph_destroy_context(struct nouveau_channel *);
1146extern int nv10_graph_load_context(struct nouveau_channel *);
1147extern int nv10_graph_unload_context(struct drm_device *);
a5cf68b0 1148extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
274fec93
BS		 1149extern struct nouveau_bitfield nv10_graph_intr[];
1150extern struct nouveau_bitfield nv10_graph_nstatus[];
6ee73861
BS		 1151
1152/* nv20_graph.c */
6ee73861
BS		 1153extern int nv20_graph_create_context(struct nouveau_channel *);
1154extern void nv20_graph_destroy_context(struct nouveau_channel *);
1155extern int nv20_graph_load_context(struct nouveau_channel *);
1156extern int nv20_graph_unload_context(struct drm_device *);
1157extern int nv20_graph_init(struct drm_device *);
1158extern void nv20_graph_takedown(struct drm_device *);
1159extern int nv30_graph_init(struct drm_device *);
a5cf68b0 1160extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1161
1162/* nv40_graph.c */
6ee73861
BS		 1163extern int nv40_graph_init(struct drm_device *);
1164extern void nv40_graph_takedown(struct drm_device *);
1165extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1166extern int nv40_graph_create_context(struct nouveau_channel *);
1167extern void nv40_graph_destroy_context(struct nouveau_channel *);
1168extern int nv40_graph_load_context(struct nouveau_channel *);
1169extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1170extern void nv40_grctx_init(struct nouveau_grctx *);
a5cf68b0 1171extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1172
1173/* nv50_graph.c */
6ee73861
BS		 1174extern int nv50_graph_init(struct drm_device *);
1175extern void nv50_graph_takedown(struct drm_device *);
1176extern void nv50_graph_fifo_access(struct drm_device *, bool);
1177extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1178extern int nv50_graph_create_context(struct nouveau_channel *);
1179extern void nv50_graph_destroy_context(struct nouveau_channel *);
1180extern int nv50_graph_load_context(struct nouveau_channel *);
1181extern int nv50_graph_unload_context(struct drm_device *);
d5f3c90d 1182extern int nv50_grctx_init(struct nouveau_grctx *);
56ac7475
BS		 1183extern void nv50_graph_tlb_flush(struct drm_device *dev);
1184extern void nv86_graph_tlb_flush(struct drm_device *dev);
6ee73861 1185
4b223eef
BS		 1186/* nvc0_graph.c */
1187extern int nvc0_graph_init(struct drm_device *);
1188extern void nvc0_graph_takedown(struct drm_device *);
1189extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1190extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1191extern int nvc0_graph_create_context(struct nouveau_channel *);
1192extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1193extern int nvc0_graph_load_context(struct nouveau_channel *);
1194extern int nvc0_graph_unload_context(struct drm_device *);
1195
bd2e597d
BS		 1196/* nv84_crypt.c */
1197extern int nv84_crypt_init(struct drm_device *dev);
1198extern void nv84_crypt_fini(struct drm_device *dev);
1199extern int nv84_crypt_create_context(struct nouveau_channel *);
1200extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1201extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1202
6ee73861
BS		 1203/* nv04_instmem.c */
1204extern int nv04_instmem_init(struct drm_device *);
1205extern void nv04_instmem_takedown(struct drm_device *);
1206extern int nv04_instmem_suspend(struct drm_device *);
1207extern void nv04_instmem_resume(struct drm_device *);
e41115d0
BS		 1208extern int nv04_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1209extern void nv04_instmem_put(struct nouveau_gpuobj *);
1210extern int nv04_instmem_map(struct nouveau_gpuobj *);
1211extern void nv04_instmem_unmap(struct nouveau_gpuobj *);
f56cb86f 1212extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1213
1214/* nv50_instmem.c */
1215extern int nv50_instmem_init(struct drm_device *);
1216extern void nv50_instmem_takedown(struct drm_device *);
1217extern int nv50_instmem_suspend(struct drm_device *);
1218extern void nv50_instmem_resume(struct drm_device *);
e41115d0
BS		 1219extern int nv50_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1220extern void nv50_instmem_put(struct nouveau_gpuobj *);
1221extern int nv50_instmem_map(struct nouveau_gpuobj *);
1222extern void nv50_instmem_unmap(struct nouveau_gpuobj *);
f56cb86f 1223extern void nv50_instmem_flush(struct drm_device *);
734ee835 1224extern void nv84_instmem_flush(struct drm_device *);
6ee73861 1225
4b223eef
BS		 1226/* nvc0_instmem.c */
1227extern int nvc0_instmem_init(struct drm_device *);
1228extern void nvc0_instmem_takedown(struct drm_device *);
1229extern int nvc0_instmem_suspend(struct drm_device *);
1230extern void nvc0_instmem_resume(struct drm_device *);
e41115d0
BS		 1231extern int nvc0_instmem_get(struct nouveau_gpuobj *, u32 size, u32 align);
1232extern void nvc0_instmem_put(struct nouveau_gpuobj *);
1233extern int nvc0_instmem_map(struct nouveau_gpuobj *);
1234extern void nvc0_instmem_unmap(struct nouveau_gpuobj *);
4b223eef
BS		 1235extern void nvc0_instmem_flush(struct drm_device *);
1236
6ee73861
BS		 1237/* nv04_mc.c */
1238extern int nv04_mc_init(struct drm_device *);
1239extern void nv04_mc_takedown(struct drm_device *);
1240
1241/* nv40_mc.c */
1242extern int nv40_mc_init(struct drm_device *);
1243extern void nv40_mc_takedown(struct drm_device *);
1244
1245/* nv50_mc.c */
1246extern int nv50_mc_init(struct drm_device *);
1247extern void nv50_mc_takedown(struct drm_device *);
1248
1249/* nv04_timer.c */
1250extern int nv04_timer_init(struct drm_device *);
1251extern uint64_t nv04_timer_read(struct drm_device *);
1252extern void nv04_timer_takedown(struct drm_device *);
1253
1254extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1255 unsigned long arg);
1256
1257/* nv04_dac.c */
8f1a6086 1258extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1259extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1260extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1261extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1262extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1263
1264/* nv04_dfp.c */
8f1a6086 1265extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1266extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1267extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1268 int head, bool dl);
1269extern void nv04_dfp_disable(struct drm_device *dev, int head);
1270extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1271
1272/* nv04_tv.c */
1273extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1274extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1275
1276/* nv17_tv.c */
8f1a6086 1277extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1278
1279/* nv04_display.c */
c88c2e06
FJ		 1280extern int nv04_display_early_init(struct drm_device *);
1281extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1282extern int nv04_display_create(struct drm_device *);
c88c2e06 1283extern int nv04_display_init(struct drm_device *);
6ee73861 1284extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1285
1286/* nv04_crtc.c */
1287extern int nv04_crtc_create(struct drm_device *, int index);
1288
1289/* nouveau_bo.c */
1290extern struct ttm_bo_driver nouveau_bo_driver;
1291extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1292 int size, int align, uint32_t flags,
1293 uint32_t tile_mode, uint32_t tile_flags,
1294 bool no_vm, bool mappable, struct nouveau_bo **);
1295extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1296extern int nouveau_bo_unpin(struct nouveau_bo *);
1297extern int nouveau_bo_map(struct nouveau_bo *);
1298extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1299extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1300 uint32_t busy);
6ee73861
BS		 1301extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1302extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1303extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1304extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
332b242f 1305extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
7a45d764
BS		 1306extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible,
1307 bool no_wait_reserve, bool no_wait_gpu);
6ee73861
BS		 1308
1309/* nouveau_fence.c */
1310struct nouveau_fence;
0c6c1c2f
FJ		 1311extern int nouveau_fence_init(struct drm_device *);
1312extern void nouveau_fence_fini(struct drm_device *);
2730723b
FJ		 1313extern int nouveau_fence_channel_init(struct nouveau_channel *);
1314extern void nouveau_fence_channel_fini(struct nouveau_channel *);
6ee73861
BS		 1315extern void nouveau_fence_update(struct nouveau_channel *);
1316extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1317 bool emit);
1318extern int nouveau_fence_emit(struct nouveau_fence *);
8ac3891b
FJ		 1319extern void nouveau_fence_work(struct nouveau_fence *fence,
1320 void (*work)(void *priv, bool signalled),
1321 void *priv);
6ee73861 1322struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
382d62e5
MS		 1323
1324extern bool __nouveau_fence_signalled(void *obj, void *arg);
1325extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1326extern int __nouveau_fence_flush(void *obj, void *arg);
1327extern void __nouveau_fence_unref(void **obj);
1328extern void *__nouveau_fence_ref(void *obj);
1329
1330static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1331{
1332 return __nouveau_fence_signalled(obj, NULL);
1333}
1334static inline int
1335nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1336{
1337 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1338}
2730723b 1339extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
382d62e5
MS		 1340static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1341{
1342 return __nouveau_fence_flush(obj, NULL);
1343}
1344static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1345{
1346 __nouveau_fence_unref((void **)obj);
1347}
1348static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1349{
1350 return __nouveau_fence_ref(obj);
1351}
6ee73861
BS		 1352
1353/* nouveau_gem.c */
1354extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1355 int size, int align, uint32_t flags,
1356 uint32_t tile_mode, uint32_t tile_flags,
1357 bool no_vm, bool mappable, struct nouveau_bo **);
1358extern int nouveau_gem_object_new(struct drm_gem_object *);
1359extern void nouveau_gem_object_del(struct drm_gem_object *);
1360extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1361 struct drm_file *);
1362extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1363 struct drm_file *);
6ee73861
BS		 1364extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1365 struct drm_file *);
1366extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1367 struct drm_file *);
1368extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1369 struct drm_file *);
1370
042206c0
FJ		 1371/* nouveau_display.c */
1372int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1373void nouveau_vblank_disable(struct drm_device *dev, int crtc);
332b242f
FJ		 1374int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1375 struct drm_pending_vblank_event *event);
1376int nouveau_finish_page_flip(struct nouveau_channel *,
1377 struct nouveau_page_flip_state *);
042206c0 1378
ee2e0131
BS		 1379/* nv10_gpio.c */
1380int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1381int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1382
45284162 1383/* nv50_gpio.c */
ee2e0131 1384int nv50_gpio_init(struct drm_device *dev);
2cbd4c81 1385void nv50_gpio_fini(struct drm_device *dev);
45284162
BS		 1386int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1387int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
fce2bad0
BS		 1388int nv50_gpio_irq_register(struct drm_device *, enum dcb_gpio_tag,
1389 void (*)(void *, int), void *);
1390void nv50_gpio_irq_unregister(struct drm_device *, enum dcb_gpio_tag,
1391 void (*)(void *, int), void *);
1392bool nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1393
e9ebb68b
BS		 1394/* nv50_calc. */
1395int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1396 int *N1, int *M1, int *N2, int *M2, int *P);
1397int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1398 int clk, int *N, int *fN, int *M, int *P);
1399
6ee73861
BS		 1400#ifndef ioread32_native
1401#ifdef __BIG_ENDIAN
1402#define ioread16_native ioread16be
1403#define iowrite16_native iowrite16be
1404#define ioread32_native ioread32be
1405#define iowrite32_native iowrite32be
1406#else /* def __BIG_ENDIAN */
1407#define ioread16_native ioread16
1408#define iowrite16_native iowrite16
1409#define ioread32_native ioread32
1410#define iowrite32_native iowrite32
1411#endif /* def __BIG_ENDIAN else */
1412#endif /* !ioread32_native */
1413
1414/* channel control reg access */
1415static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1416{
1417 return ioread32_native(chan->user + reg);
1418}
1419
1420static inline void nvchan_wr32(struct nouveau_channel *chan,
1421 unsigned reg, u32 val)
1422{
1423 iowrite32_native(val, chan->user + reg);
1424}
1425
1426/* register access */
1427static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1428{
1429 struct drm_nouveau_private *dev_priv = dev->dev_private;
1430 return ioread32_native(dev_priv->mmio + reg);
1431}
1432
1433static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1434{
1435 struct drm_nouveau_private *dev_priv = dev->dev_private;
1436 iowrite32_native(val, dev_priv->mmio + reg);
1437}
1438
2a7fdb2b 1439static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1440{
1441 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1442 nv_wr32(dev, reg, (tmp & ~mask) | val);
1443 return tmp;
49eed80a
BS		 1444}
1445
6ee73861
BS		 1446static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1447{
1448 struct drm_nouveau_private *dev_priv = dev->dev_private;
1449 return ioread8(dev_priv->mmio + reg);
1450}
1451
1452static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1453{
1454 struct drm_nouveau_private *dev_priv = dev->dev_private;
1455 iowrite8(val, dev_priv->mmio + reg);
1456}
1457
4b5c152a 1458#define nv_wait(dev, reg, mask, val) \
12fb9525
BS		 1459 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
1460#define nv_wait_ne(dev, reg, mask, val) \
1461 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
6ee73861
BS		 1462
1463/* PRAMIN access */
1464static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1465{
1466 struct drm_nouveau_private *dev_priv = dev->dev_private;
1467 return ioread32_native(dev_priv->ramin + offset);
1468}
1469
1470static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1471{
1472 struct drm_nouveau_private *dev_priv = dev->dev_private;
1473 iowrite32_native(val, dev_priv->ramin + offset);
1474}
1475
1476/* object access */
b3beb167
BS		 1477extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1478extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1479
1480/*
1481 * Logging
1482 * Argument d is (struct drm_device *).
1483 */
1484#define NV_PRINTK(level, d, fmt, arg...) \
1485 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1486 pci_name(d->pdev), ##arg)
1487#ifndef NV_DEBUG_NOTRACE
1488#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1489 if (drm_debug & DRM_UT_DRIVER) { \
1490 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1491 __LINE__, ##arg); \
1492 } \
1493} while (0)
1494#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1495 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1496 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1497 __LINE__, ##arg); \
1498 } \
1499} while (0)
1500#else
1501#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1502 if (drm_debug & DRM_UT_DRIVER) \
1503 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1504} while (0)
1505#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1506 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1507 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1508} while (0)
1509#endif
1510#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1511#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1512#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1513#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1514#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1515
1516/* nouveau_reg_debug bitmask */
1517enum {
1518 NOUVEAU_REG_DEBUG_MC = 0x1,
1519 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1520 NOUVEAU_REG_DEBUG_FB = 0x4,
1521 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1522 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1523 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1524 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1525 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1526 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1527 NOUVEAU_REG_DEBUG_EVO = 0x200,
1528};
1529
1530#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1531 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1532 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1533} while (0)
1534
1535static inline bool
1536nv_two_heads(struct drm_device *dev)
1537{
1538 struct drm_nouveau_private *dev_priv = dev->dev_private;
1539 const int impl = dev->pci_device & 0x0ff0;
1540
1541 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1542 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1543 return true;
1544
1545 return false;
1546}
1547
1548static inline bool
1549nv_gf4_disp_arch(struct drm_device *dev)
1550{
1551 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1552}
1553
1554static inline bool
1555nv_two_reg_pll(struct drm_device *dev)
1556{
1557 struct drm_nouveau_private *dev_priv = dev->dev_private;
1558 const int impl = dev->pci_device & 0x0ff0;
1559
1560 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1561 return true;
1562 return false;
1563}
1564
acae116c
FJ		 1565static inline bool
1566nv_match_device(struct drm_device *dev, unsigned device,
1567 unsigned sub_vendor, unsigned sub_device)
1568{
1569 return dev->pdev->device == device &&
1570 dev->pdev->subsystem_vendor == sub_vendor &&
1571 dev->pdev->subsystem_device == sub_device;
1572}
1573
7f4a195f 1574/* memory type/access flags, do not match hardware values */
a11c3198
BS		 1575#define NV_MEM_ACCESS_RO 1
1576#define NV_MEM_ACCESS_WO 2
7f4a195f 1577#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
a11c3198
BS		 1578#define NV_MEM_ACCESS_SYS 4
1579#define NV_MEM_ACCESS_VM 8
7f4a195f
BS		 1580
1581#define NV_MEM_TARGET_VRAM 0
1582#define NV_MEM_TARGET_PCI 1
1583#define NV_MEM_TARGET_PCI_NOSNOOP 2
1584#define NV_MEM_TARGET_VM 3
1585#define NV_MEM_TARGET_GART 4
1586
1587#define NV_MEM_TYPE_VM 0x7f
1588#define NV_MEM_COMP_VM 0x03
1589
1590/* NV_SW object class */
f03a314b
FJ		 1591#define NV_SW 0x0000506e
1592#define NV_SW_DMA_SEMAPHORE 0x00000060
1593#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1594#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1595#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
8af29ccd 1596#define NV_SW_YIELD 0x00000080
f03a314b
FJ		 1597#define NV_SW_DMA_VBLSEM 0x0000018c
1598#define NV_SW_VBLSEM_OFFSET 0x00000400
1599#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1600#define NV_SW_VBLSEM_RELEASE 0x00000408
332b242f 1601#define NV_SW_PAGE_FLIP 0x00000500
6ee73861
BS		 1602
1603#endif /* __NOUVEAU_DRV_H__ */
Linux kernel - Deliverables
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