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drm/nouveau: Import initial memory timing work
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add
FJ		 68struct nouveau_tile_reg {
69 struct nouveau_fence *fence;
70 uint32_t addr;
71 uint32_t size;
72 bool used;
73};
74
6ee73861
BS		 75struct nouveau_bo {
76 struct ttm_buffer_object bo;
77 struct ttm_placement placement;
78 u32 placements[3];
78ad0f7b 79 u32 busy_placements[3];
6ee73861
BS		 80 struct ttm_bo_kmap_obj kmap;
81 struct list_head head;
82
83 /* protected by ttm_bo_reserve() */
84 struct drm_file *reserved_by;
85 struct list_head entry;
86 int pbbo_index;
a1606a95 87 bool validate_mapped;
6ee73861
BS		 88
89 struct nouveau_channel *channel;
90
91 bool mappable;
92 bool no_vm;
93
94 uint32_t tile_mode;
95 uint32_t tile_flags;
a0af9add 96 struct nouveau_tile_reg *tile;
6ee73861
BS		 97
98 struct drm_gem_object *gem;
99 struct drm_file *cpu_filp;
100 int pin_refcnt;
101};
102
103static inline struct nouveau_bo *
104nouveau_bo(struct ttm_buffer_object *bo)
105{
106 return container_of(bo, struct nouveau_bo, bo);
107}
108
109static inline struct nouveau_bo *
110nouveau_gem_object(struct drm_gem_object *gem)
111{
112 return gem ? gem->driver_private : NULL;
113}
114
115/* TODO: submit equivalent to TTM generic API upstream? */
116static inline void __iomem *
117nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
118{
119 bool is_iomem;
120 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
121 &nvbo->kmap, &is_iomem);
122 WARN_ON_ONCE(ioptr && !is_iomem);
123 return ioptr;
124}
125
6ee73861
BS		 126enum nouveau_flags {
127 NV_NFORCE = 0x10000000,
128 NV_NFORCE2 = 0x20000000
129};
130
131#define NVOBJ_ENGINE_SW 0
132#define NVOBJ_ENGINE_GR 1
133#define NVOBJ_ENGINE_DISPLAY 2
134#define NVOBJ_ENGINE_INT 0xdeadbeef
135
6ee73861
BS		 136#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
137#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 138struct nouveau_gpuobj {
b3beb167 139 struct drm_device *dev;
eb9bcbdc 140 struct kref refcount;
6ee73861
BS		 141 struct list_head list;
142
b833ac26 143 struct drm_mm_node *im_pramin;
6ee73861 144 struct nouveau_bo *im_backing;
6ee73861
BS		 145 uint32_t *im_backing_suspend;
146 int im_bound;
147
148 uint32_t flags;
6ee73861 149
43efc9ce 150 u32 size;
de3a6c0a
BS		 151 u32 pinst;
152 u32 cinst;
153 u64 vinst;
154
6ee73861
BS		 155 uint32_t engine;
156 uint32_t class;
157
158 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
159 void *priv;
160};
161
6ee73861
BS		 162struct nouveau_channel {
163 struct drm_device *dev;
164 int id;
165
166 /* owner of this fifo */
167 struct drm_file *file_priv;
168 /* mapping of the fifo itself */
169 struct drm_local_map *map;
170
171 /* mapping of the regs controling the fifo */
172 void __iomem *user;
173 uint32_t user_get;
174 uint32_t user_put;
175
176 /* Fencing */
177 struct {
178 /* lock protects the pending list only */
179 spinlock_t lock;
180 struct list_head pending;
181 uint32_t sequence;
182 uint32_t sequence_ack;
047d1d3c 183 atomic_t last_sequence_irq;
6ee73861
BS		 184 } fence;
185
186 /* DMA push buffer */
a8eaebc6
BS		 187 struct nouveau_gpuobj *pushbuf;
188 struct nouveau_bo *pushbuf_bo;
189 uint32_t pushbuf_base;
6ee73861
BS		 190
191 /* Notifier memory */
192 struct nouveau_bo *notifier_bo;
b833ac26 193 struct drm_mm notifier_heap;
6ee73861
BS		 194
195 /* PFIFO context */
a8eaebc6
BS		 196 struct nouveau_gpuobj *ramfc;
197 struct nouveau_gpuobj *cache;
6ee73861
BS		 198
199 /* PGRAPH context */
200 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 201 struct nouveau_gpuobj *ramin_grctx;
6ee73861
BS		 202 void *pgraph_ctx;
203
204 /* NV50 VM */
a8eaebc6
BS		 205 struct nouveau_gpuobj *vm_pd;
206 struct nouveau_gpuobj *vm_gart_pt;
207 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 208
209 /* Objects */
a8eaebc6
BS		 210 struct nouveau_gpuobj *ramin; /* Private instmem */
211 struct drm_mm ramin_heap; /* Private PRAMIN heap */
212 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 213
214 /* GPU object info for stuff used in-kernel (mm_enabled) */
215 uint32_t m2mf_ntfy;
216 uint32_t vram_handle;
217 uint32_t gart_handle;
218 bool accel_done;
219
220 /* Push buffer state (only for drm's channel on !mm_enabled) */
221 struct {
222 int max;
223 int free;
224 int cur;
225 int put;
226 /* access via pushbuf_bo */
9a391ad8
BS		 227
228 int ib_base;
229 int ib_max;
230 int ib_free;
231 int ib_put;
6ee73861
BS		 232 } dma;
233
234 uint32_t sw_subchannel[8];
235
236 struct {
237 struct nouveau_gpuobj *vblsem;
238 uint32_t vblsem_offset;
239 uint32_t vblsem_rval;
240 struct list_head vbl_wait;
241 } nvsw;
242
243 struct {
244 bool active;
245 char name[32];
246 struct drm_info_list info;
247 } debugfs;
248};
249
250struct nouveau_instmem_engine {
251 void *priv;
252
253 int (*init)(struct drm_device *dev);
254 void (*takedown)(struct drm_device *dev);
255 int (*suspend)(struct drm_device *dev);
256 void (*resume)(struct drm_device *dev);
257
258 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
259 uint32_t *size);
260 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
261 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
262 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 263 void (*flush)(struct drm_device *);
6ee73861
BS		 264};
265
266struct nouveau_mc_engine {
267 int (*init)(struct drm_device *dev);
268 void (*takedown)(struct drm_device *dev);
269};
270
271struct nouveau_timer_engine {
272 int (*init)(struct drm_device *dev);
273 void (*takedown)(struct drm_device *dev);
274 uint64_t (*read)(struct drm_device *dev);
275};
276
277struct nouveau_fb_engine {
cb00f7c1
FJ		 278 int num_tiles;
279
6ee73861
BS		 280 int (*init)(struct drm_device *dev);
281 void (*takedown)(struct drm_device *dev);
cb00f7c1
FJ		 282
283 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
284 uint32_t size, uint32_t pitch);
6ee73861
BS		 285};
286
287struct nouveau_fifo_engine {
6ee73861
BS		 288 int channels;
289
a8eaebc6 290 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 291 int cur_playlist;
292
6ee73861
BS		 293 int (*init)(struct drm_device *);
294 void (*takedown)(struct drm_device *);
295
296 void (*disable)(struct drm_device *);
297 void (*enable)(struct drm_device *);
298 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 299 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 300
301 int (*channel_id)(struct drm_device *);
302
303 int (*create_context)(struct nouveau_channel *);
304 void (*destroy_context)(struct nouveau_channel *);
305 int (*load_context)(struct nouveau_channel *);
306 int (*unload_context)(struct drm_device *);
307};
308
309struct nouveau_pgraph_object_method {
310 int id;
311 int (*exec)(struct nouveau_channel *chan, int grclass, int mthd,
312 uint32_t data);
313};
314
315struct nouveau_pgraph_object_class {
316 int id;
317 bool software;
318 struct nouveau_pgraph_object_method *methods;
319};
320
321struct nouveau_pgraph_engine {
322 struct nouveau_pgraph_object_class *grclass;
323 bool accel_blocked;
054b93e4 324 int grctx_size;
6ee73861 325
c50a5681 326 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 327 struct nouveau_gpuobj *ctx_table;
c50a5681 328
6ee73861
BS		 329 int (*init)(struct drm_device *);
330 void (*takedown)(struct drm_device *);
331
332 void (*fifo_access)(struct drm_device *, bool);
333
334 struct nouveau_channel *(*channel)(struct drm_device *);
335 int (*create_context)(struct nouveau_channel *);
336 void (*destroy_context)(struct nouveau_channel *);
337 int (*load_context)(struct nouveau_channel *);
338 int (*unload_context)(struct drm_device *);
cb00f7c1
FJ		 339
340 void (*set_region_tiling)(struct drm_device *dev, int i, uint32_t addr,
341 uint32_t size, uint32_t pitch);
6ee73861
BS		 342};
343
c88c2e06
FJ		 344struct nouveau_display_engine {
345 int (*early_init)(struct drm_device *);
346 void (*late_takedown)(struct drm_device *);
347 int (*create)(struct drm_device *);
348 int (*init)(struct drm_device *);
349 void (*destroy)(struct drm_device *);
350};
351
ee2e0131
BS		 352struct nouveau_gpio_engine {
353 int (*init)(struct drm_device *);
354 void (*takedown)(struct drm_device *);
355
356 int (*get)(struct drm_device *, enum dcb_gpio_tag);
357 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
358
359 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
360};
361
330c5988
BS		 362struct nouveau_pm_voltage_level {
363 u8 voltage;
364 u8 vid;
365};
366
367struct nouveau_pm_voltage {
368 bool supported;
369 u8 vid_mask;
370
371 struct nouveau_pm_voltage_level *level;
372 int nr_level;
373};
374
375#define NOUVEAU_PM_MAX_LEVEL 8
376struct nouveau_pm_level {
377 struct device_attribute dev_attr;
378 char name[32];
379 int id;
380
381 u32 core;
382 u32 memory;
383 u32 shader;
384 u32 unk05;
385
386 u8 voltage;
387 u8 fanspeed;
388};
389
34e9d85a
MP		 390struct nouveau_pm_temp_sensor_constants {
391 u16 offset_constant;
392 s16 offset_mult;
393 u16 offset_div;
394 u16 slope_mult;
395 u16 slope_div;
396};
397
398struct nouveau_pm_threshold_temp {
399 s16 critical;
400 s16 down_clock;
401 s16 fan_boost;
402};
403
7760fcb0
RS		 404struct nouveau_pm_memtiming {
405 u32 reg_100220;
406 u32 reg_100224;
407 u32 reg_100228;
408 u32 reg_10022c;
409 u32 reg_100230;
410 u32 reg_100234;
411 u32 reg_100238;
412 u32 reg_10023c;
413};
414
415struct nouveau_pm_memtimings {
416 bool supported;
417 struct nouveau_pm_memtiming *timing;
418 int nr_timing;
419};
420
330c5988
BS		 421struct nouveau_pm_engine {
422 struct nouveau_pm_voltage voltage;
423 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
424 int nr_perflvl;
7760fcb0 425 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 426 struct nouveau_pm_temp_sensor_constants sensor_constants;
427 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 428
429 struct nouveau_pm_level boot;
430 struct nouveau_pm_level *cur;
431
8155cac4
FJ		 432 struct device *hwmon;
433
330c5988
BS		 434 int (*clock_get)(struct drm_device *, u32 id);
435 void *(*clock_pre)(struct drm_device *, u32 id, int khz);
436 void (*clock_set)(struct drm_device *, void *);
437 int (*voltage_get)(struct drm_device *);
438 int (*voltage_set)(struct drm_device *, int voltage);
439 int (*fanspeed_get)(struct drm_device *);
440 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 441 int (*temp_get)(struct drm_device *);
330c5988
BS		 442};
443
6ee73861
BS		 444struct nouveau_engine {
445 struct nouveau_instmem_engine instmem;
446 struct nouveau_mc_engine mc;
447 struct nouveau_timer_engine timer;
448 struct nouveau_fb_engine fb;
449 struct nouveau_pgraph_engine graph;
450 struct nouveau_fifo_engine fifo;
c88c2e06 451 struct nouveau_display_engine display;
ee2e0131 452 struct nouveau_gpio_engine gpio;
330c5988 453 struct nouveau_pm_engine pm;
6ee73861
BS		 454};
455
456struct nouveau_pll_vals {
457 union {
458 struct {
459#ifdef __BIG_ENDIAN
460 uint8_t N1, M1, N2, M2;
461#else
462 uint8_t M1, N1, M2, N2;
463#endif
464 };
465 struct {
466 uint16_t NM1, NM2;
467 } __attribute__((packed));
468 };
469 int log2P;
470
471 int refclk;
472};
473
474enum nv04_fp_display_regs {
475 FP_DISPLAY_END,
476 FP_TOTAL,
477 FP_CRTC,
478 FP_SYNC_START,
479 FP_SYNC_END,
480 FP_VALID_START,
481 FP_VALID_END
482};
483
484struct nv04_crtc_reg {
485 unsigned char MiscOutReg; /* */
4a9f822f 486 uint8_t CRTC[0xa0];
6ee73861
BS		 487 uint8_t CR58[0x10];
488 uint8_t Sequencer[5];
489 uint8_t Graphics[9];
490 uint8_t Attribute[21];
491 unsigned char DAC[768]; /* Internal Colorlookuptable */
492
493 /* PCRTC regs */
494 uint32_t fb_start;
495 uint32_t crtc_cfg;
496 uint32_t cursor_cfg;
497 uint32_t gpio_ext;
498 uint32_t crtc_830;
499 uint32_t crtc_834;
500 uint32_t crtc_850;
501 uint32_t crtc_eng_ctrl;
502
503 /* PRAMDAC regs */
504 uint32_t nv10_cursync;
505 struct nouveau_pll_vals pllvals;
506 uint32_t ramdac_gen_ctrl;
507 uint32_t ramdac_630;
508 uint32_t ramdac_634;
509 uint32_t tv_setup;
510 uint32_t tv_vtotal;
511 uint32_t tv_vskew;
512 uint32_t tv_vsync_delay;
513 uint32_t tv_htotal;
514 uint32_t tv_hskew;
515 uint32_t tv_hsync_delay;
516 uint32_t tv_hsync_delay2;
517 uint32_t fp_horiz_regs[7];
518 uint32_t fp_vert_regs[7];
519 uint32_t dither;
520 uint32_t fp_control;
521 uint32_t dither_regs[6];
522 uint32_t fp_debug_0;
523 uint32_t fp_debug_1;
524 uint32_t fp_debug_2;
525 uint32_t fp_margin_color;
526 uint32_t ramdac_8c0;
527 uint32_t ramdac_a20;
528 uint32_t ramdac_a24;
529 uint32_t ramdac_a34;
530 uint32_t ctv_regs[38];
531};
532
533struct nv04_output_reg {
534 uint32_t output;
535 int head;
536};
537
538struct nv04_mode_state {
539 uint32_t bpp;
540 uint32_t width;
541 uint32_t height;
542 uint32_t interlace;
543 uint32_t repaint0;
544 uint32_t repaint1;
545 uint32_t screen;
546 uint32_t scale;
547 uint32_t dither;
548 uint32_t extra;
549 uint32_t fifo;
550 uint32_t pixel;
551 uint32_t horiz;
552 int arbitration0;
553 int arbitration1;
554 uint32_t pll;
555 uint32_t pllB;
556 uint32_t vpll;
557 uint32_t vpll2;
558 uint32_t vpllB;
559 uint32_t vpll2B;
560 uint32_t pllsel;
561 uint32_t sel_clk;
562 uint32_t general;
563 uint32_t crtcOwner;
564 uint32_t head;
565 uint32_t head2;
566 uint32_t cursorConfig;
567 uint32_t cursor0;
568 uint32_t cursor1;
569 uint32_t cursor2;
570 uint32_t timingH;
571 uint32_t timingV;
572 uint32_t displayV;
573 uint32_t crtcSync;
574
575 struct nv04_crtc_reg crtc_reg[2];
576};
577
578enum nouveau_card_type {
579 NV_04 = 0x00,
580 NV_10 = 0x10,
581 NV_20 = 0x20,
582 NV_30 = 0x30,
583 NV_40 = 0x40,
584 NV_50 = 0x50,
4b223eef 585 NV_C0 = 0xc0,
6ee73861
BS		 586};
587
588struct drm_nouveau_private {
589 struct drm_device *dev;
6ee73861
BS		 590
591 /* the card type, takes NV_* as values */
592 enum nouveau_card_type card_type;
593 /* exact chipset, derived from NV_PMC_BOOT_0 */
594 int chipset;
595 int flags;
596
597 void __iomem *mmio;
5125bfd8 598
e05d7eae 599 spinlock_t ramin_lock;
6ee73861 600 void __iomem *ramin;
5125bfd8
BS		 601 u32 ramin_size;
602 u32 ramin_base;
603 bool ramin_available;
e05d7eae
BS		 604 struct drm_mm ramin_heap;
605 struct list_head gpuobj_list;
6ee73861 606
ac8fb975
BS		 607 struct nouveau_bo *vga_ram;
608
6ee73861
BS		 609 struct workqueue_struct *wq;
610 struct work_struct irq_work;
a5acac66 611 struct work_struct hpd_work;
6ee73861
BS		 612
613 struct list_head vbl_waiting;
614
615 struct {
ba4420c2 616 struct drm_global_reference mem_global_ref;
6ee73861
BS		 617 struct ttm_bo_global_ref bo_global_ref;
618 struct ttm_bo_device bdev;
6ee73861
BS		 619 atomic_t validate_sequence;
620 } ttm;
621
6ee73861
BS		 622 int fifo_alloc_count;
623 struct nouveau_channel *fifos[NOUVEAU_MAX_CHANNEL_NR];
624
625 struct nouveau_engine engine;
626 struct nouveau_channel *channel;
627
ff9e5279
MM		 628 /* For PFIFO and PGRAPH. */
629 spinlock_t context_switch_lock;
630
6ee73861 631 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 632 struct nouveau_ramht *ramht;
633 struct nouveau_gpuobj *ramfc;
634 struct nouveau_gpuobj *ramro;
635
6ee73861 636 uint32_t ramin_rsvd_vram;
6ee73861 637
6ee73861
BS		 638 struct {
639 enum {
640 NOUVEAU_GART_NONE = 0,
641 NOUVEAU_GART_AGP,
642 NOUVEAU_GART_SGDMA
643 } type;
644 uint64_t aper_base;
645 uint64_t aper_size;
646 uint64_t aper_free;
647
648 struct nouveau_gpuobj *sg_ctxdma;
649 struct page *sg_dummy_page;
650 dma_addr_t sg_dummy_bus;
6ee73861
BS		 651 } gart_info;
652
a0af9add 653 /* nv10-nv40 tiling regions */
9f56b126 654 struct nouveau_tile_reg tile[NOUVEAU_MAX_TILE_NR];
a0af9add 655
a76fb4e8
BS		 656 /* VRAM/fb configuration */
657 uint64_t vram_size;
658 uint64_t vram_sys_base;
6c3d7ef2 659 u32 vram_rblock_size;
a76fb4e8
BS		 660
661 uint64_t fb_phys;
662 uint64_t fb_available_size;
663 uint64_t fb_mappable_pages;
664 uint64_t fb_aper_free;
665 int fb_mtrr;
666
6ee73861
BS		 667 /* G8x/G9x virtual address space */
668 uint64_t vm_gart_base;
669 uint64_t vm_gart_size;
670 uint64_t vm_vram_base;
671 uint64_t vm_vram_size;
672 uint64_t vm_end;
673 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
674 int vm_vram_pt_nr;
6ee73861 675
04a39c57 676 struct nvbios vbios;
6ee73861
BS		 677
678 struct nv04_mode_state mode_reg;
679 struct nv04_mode_state saved_reg;
680 uint32_t saved_vga_font[4][16384];
681 uint32_t crtc_owner;
682 uint32_t dac_users[4];
683
684 struct nouveau_suspend_resume {
6ee73861 685 uint32_t *ramin_copy;
6ee73861
BS		 686 } susres;
687
688 struct backlight_device *backlight;
6ee73861
BS		 689
690 struct nouveau_channel *evo;
87c0e0e5
BS		 691 struct {
692 struct dcb_entry *dcb;
693 u16 script;
694 u32 pclk;
695 } evo_irq;
6ee73861
BS		 696
697 struct {
698 struct dentry *channel_root;
699 } debugfs;
38651674 700
8be48d92 701 struct nouveau_fbdev *nfbdev;
06415c56 702 struct apertures_struct *apertures;
6ee73861
BS		 703};
704
705static inline struct drm_nouveau_private *
706nouveau_bdev(struct ttm_bo_device *bd)
707{
708 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
709}
710
711static inline int
712nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
713{
714 struct nouveau_bo *prev;
715
716 if (!pnvbo)
717 return -EINVAL;
718 prev = *pnvbo;
719
720 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
721 if (prev) {
722 struct ttm_buffer_object *bo = &prev->bo;
723
724 ttm_bo_unref(&bo);
725 }
726
727 return 0;
728}
729
6ee73861
BS		 730#define NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(id, cl, ch) do { \
731 struct drm_nouveau_private *nv = dev->dev_private; \
732 if (!nouveau_channel_owner(dev, (cl), (id))) { \
733 NV_ERROR(dev, "pid %d doesn't own channel %d\n", \
734 DRM_CURRENTPID, (id)); \
735 return -EPERM; \
736 } \
737 (ch) = nv->fifos[(id)]; \
738} while (0)
739
740/* nouveau_drv.c */
de5899bd 741extern int nouveau_agpmode;
6ee73861
BS		 742extern int nouveau_duallink;
743extern int nouveau_uscript_lvds;
744extern int nouveau_uscript_tmds;
745extern int nouveau_vram_pushbuf;
746extern int nouveau_vram_notify;
747extern int nouveau_fbpercrtc;
f4053509 748extern int nouveau_tv_disable;
6ee73861
BS		 749extern char *nouveau_tv_norm;
750extern int nouveau_reg_debug;
751extern char *nouveau_vbios;
a1470890 752extern int nouveau_ignorelid;
a32ed69d
MK		 753extern int nouveau_nofbaccel;
754extern int nouveau_noaccel;
da647d5b 755extern int nouveau_override_conntype;
6f876986
BS		 756extern char *nouveau_perflvl;
757extern int nouveau_perflvl_wr;
6ee73861 758
6a9ee8af
DA		 759extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
760extern int nouveau_pci_resume(struct pci_dev *pdev);
761
6ee73861
BS		 762/* nouveau_state.c */
763extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
764extern int nouveau_load(struct drm_device *, unsigned long flags);
765extern int nouveau_firstopen(struct drm_device *);
766extern void nouveau_lastclose(struct drm_device *);
767extern int nouveau_unload(struct drm_device *);
768extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
769 struct drm_file *);
770extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
771 struct drm_file *);
772extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
773 uint32_t reg, uint32_t mask, uint32_t val);
774extern bool nouveau_wait_for_idle(struct drm_device *);
775extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 776
777/* nouveau_mem.c */
fbd2895e
BS		 778extern int nouveau_mem_vram_init(struct drm_device *);
779extern void nouveau_mem_vram_fini(struct drm_device *);
780extern int nouveau_mem_gart_init(struct drm_device *);
781extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 782extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 783extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 784extern void nouveau_mem_close(struct drm_device *);
a0af9add
FJ		 785extern struct nouveau_tile_reg *nv10_mem_set_tiling(struct drm_device *dev,
786 uint32_t addr,
787 uint32_t size,
788 uint32_t pitch);
789extern void nv10_mem_expire_tiling(struct drm_device *dev,
790 struct nouveau_tile_reg *tile,
791 struct nouveau_fence *fence);
6ee73861
BS		 792extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
793 uint32_t size, uint32_t flags,
794 uint64_t phys);
795extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
796 uint32_t size);
797
798/* nouveau_notifier.c */
799extern int nouveau_notifier_init_channel(struct nouveau_channel *);
800extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
801extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
802 int cout, uint32_t *offset);
803extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
804extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
805 struct drm_file *);
806extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
807 struct drm_file *);
808
809/* nouveau_channel.c */
810extern struct drm_ioctl_desc nouveau_ioctls[];
811extern int nouveau_max_ioctl;
812extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
813extern int nouveau_channel_owner(struct drm_device *, struct drm_file *,
814 int channel);
815extern int nouveau_channel_alloc(struct drm_device *dev,
816 struct nouveau_channel **chan,
817 struct drm_file *file_priv,
818 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
819extern void nouveau_channel_free(struct nouveau_channel *);
6ee73861
BS		 820
821/* nouveau_object.c */
822extern int nouveau_gpuobj_early_init(struct drm_device *);
823extern int nouveau_gpuobj_init(struct drm_device *);
824extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861
BS		 825extern int nouveau_gpuobj_suspend(struct drm_device *dev);
826extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
827extern void nouveau_gpuobj_resume(struct drm_device *dev);
828extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
829 uint32_t vram_h, uint32_t tt_h);
830extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
831extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
832 uint32_t size, int align, uint32_t flags,
833 struct nouveau_gpuobj **);
a8eaebc6
BS		 834extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
835 struct nouveau_gpuobj **);
43efc9ce
BS		 836extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
837 u32 size, u32 flags,
a8eaebc6 838 struct nouveau_gpuobj **);
6ee73861
BS		 839extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
840 uint64_t offset, uint64_t size, int access,
841 int target, struct nouveau_gpuobj **);
842extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
843 uint64_t offset, uint64_t size,
844 int access, struct nouveau_gpuobj **,
845 uint32_t *o_ret);
846extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
847 struct nouveau_gpuobj **);
f03a314b
FJ		 848extern int nouveau_gpuobj_sw_new(struct nouveau_channel *, int class,
849 struct nouveau_gpuobj **);
6ee73861
BS		 850extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
851 struct drm_file *);
852extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
853 struct drm_file *);
854
855/* nouveau_irq.c */
856extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
857extern void nouveau_irq_preinstall(struct drm_device *);
858extern int nouveau_irq_postinstall(struct drm_device *);
859extern void nouveau_irq_uninstall(struct drm_device *);
860
861/* nouveau_sgdma.c */
862extern int nouveau_sgdma_init(struct drm_device *);
863extern void nouveau_sgdma_takedown(struct drm_device *);
864extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
865 uint32_t *page);
866extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
867
868/* nouveau_debugfs.c */
869#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
870extern int nouveau_debugfs_init(struct drm_minor *);
871extern void nouveau_debugfs_takedown(struct drm_minor *);
872extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
873extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
874#else
875static inline int
876nouveau_debugfs_init(struct drm_minor *minor)
877{
878 return 0;
879}
880
881static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
882{
883}
884
885static inline int
886nouveau_debugfs_channel_init(struct nouveau_channel *chan)
887{
888 return 0;
889}
890
891static inline void
892nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
893{
894}
895#endif
896
897/* nouveau_dma.c */
75c99da6 898extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 899extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 900extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 901
902/* nouveau_acpi.c */
afeb3e11 903#define ROM_BIOS_PAGE 4096
2f41a7f1 904#if defined(CONFIG_ACPI)
6a9ee8af
DA		 905void nouveau_register_dsm_handler(void);
906void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 907int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
908bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 909int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 910#else
911static inline void nouveau_register_dsm_handler(void) {}
912static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 913static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
914static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 915static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 916#endif
6ee73861
BS		 917
918/* nouveau_backlight.c */
919#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
920extern int nouveau_backlight_init(struct drm_device *);
921extern void nouveau_backlight_exit(struct drm_device *);
922#else
923static inline int nouveau_backlight_init(struct drm_device *dev)
924{
925 return 0;
926}
927
928static inline void nouveau_backlight_exit(struct drm_device *dev) { }
929#endif
930
931/* nouveau_bios.c */
932extern int nouveau_bios_init(struct drm_device *);
933extern void nouveau_bios_takedown(struct drm_device *dev);
934extern int nouveau_run_vbios_init(struct drm_device *);
935extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
936 struct dcb_entry *);
937extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
938 enum dcb_gpio_tag);
939extern struct dcb_connector_table_entry *
940nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 941extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 942extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
943 struct pll_lims *);
944extern int nouveau_bios_run_display_table(struct drm_device *,
945 struct dcb_entry *,
946 uint32_t script, int pxclk);
947extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
948 int *length);
949extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
950extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
951extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
952 bool *dl, bool *if_is_24bit);
953extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
954 int head, int pxclk);
955extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
956 enum LVDS_script, int pxclk);
957
958/* nouveau_ttm.c */
959int nouveau_ttm_global_init(struct drm_nouveau_private *);
960void nouveau_ttm_global_release(struct drm_nouveau_private *);
961int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
962
963/* nouveau_dp.c */
964int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
965 uint8_t *data, int data_nr);
966bool nouveau_dp_detect(struct drm_encoder *);
967bool nouveau_dp_link_train(struct drm_encoder *);
968
969/* nv04_fb.c */
970extern int nv04_fb_init(struct drm_device *);
971extern void nv04_fb_takedown(struct drm_device *);
972
973/* nv10_fb.c */
974extern int nv10_fb_init(struct drm_device *);
975extern void nv10_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 976extern void nv10_fb_set_region_tiling(struct drm_device *, int, uint32_t,
977 uint32_t, uint32_t);
6ee73861 978
8bded189
FJ		 979/* nv30_fb.c */
980extern int nv30_fb_init(struct drm_device *);
981extern void nv30_fb_takedown(struct drm_device *);
982
6ee73861
BS		 983/* nv40_fb.c */
984extern int nv40_fb_init(struct drm_device *);
985extern void nv40_fb_takedown(struct drm_device *);
cb00f7c1
FJ		 986extern void nv40_fb_set_region_tiling(struct drm_device *, int, uint32_t,
987 uint32_t, uint32_t);
304424e1
MK		 988/* nv50_fb.c */
989extern int nv50_fb_init(struct drm_device *);
990extern void nv50_fb_takedown(struct drm_device *);
d96773e7 991extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 992
4b223eef
BS		 993/* nvc0_fb.c */
994extern int nvc0_fb_init(struct drm_device *);
995extern void nvc0_fb_takedown(struct drm_device *);
996
6ee73861
BS		 997/* nv04_fifo.c */
998extern int nv04_fifo_init(struct drm_device *);
999extern void nv04_fifo_disable(struct drm_device *);
1000extern void nv04_fifo_enable(struct drm_device *);
1001extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 1002extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 1003extern int nv04_fifo_channel_id(struct drm_device *);
1004extern int nv04_fifo_create_context(struct nouveau_channel *);
1005extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1006extern int nv04_fifo_load_context(struct nouveau_channel *);
1007extern int nv04_fifo_unload_context(struct drm_device *);
1008
1009/* nv10_fifo.c */
1010extern int nv10_fifo_init(struct drm_device *);
1011extern int nv10_fifo_channel_id(struct drm_device *);
1012extern int nv10_fifo_create_context(struct nouveau_channel *);
1013extern void nv10_fifo_destroy_context(struct nouveau_channel *);
1014extern int nv10_fifo_load_context(struct nouveau_channel *);
1015extern int nv10_fifo_unload_context(struct drm_device *);
1016
1017/* nv40_fifo.c */
1018extern int nv40_fifo_init(struct drm_device *);
1019extern int nv40_fifo_create_context(struct nouveau_channel *);
1020extern void nv40_fifo_destroy_context(struct nouveau_channel *);
1021extern int nv40_fifo_load_context(struct nouveau_channel *);
1022extern int nv40_fifo_unload_context(struct drm_device *);
1023
1024/* nv50_fifo.c */
1025extern int nv50_fifo_init(struct drm_device *);
1026extern void nv50_fifo_takedown(struct drm_device *);
1027extern int nv50_fifo_channel_id(struct drm_device *);
1028extern int nv50_fifo_create_context(struct nouveau_channel *);
1029extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1030extern int nv50_fifo_load_context(struct nouveau_channel *);
1031extern int nv50_fifo_unload_context(struct drm_device *);
1032
4b223eef
BS		 1033/* nvc0_fifo.c */
1034extern int nvc0_fifo_init(struct drm_device *);
1035extern void nvc0_fifo_takedown(struct drm_device *);
1036extern void nvc0_fifo_disable(struct drm_device *);
1037extern void nvc0_fifo_enable(struct drm_device *);
1038extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1039extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1040extern int nvc0_fifo_channel_id(struct drm_device *);
1041extern int nvc0_fifo_create_context(struct nouveau_channel *);
1042extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1043extern int nvc0_fifo_load_context(struct nouveau_channel *);
1044extern int nvc0_fifo_unload_context(struct drm_device *);
1045
6ee73861
BS		 1046/* nv04_graph.c */
1047extern struct nouveau_pgraph_object_class nv04_graph_grclass[];
1048extern int nv04_graph_init(struct drm_device *);
1049extern void nv04_graph_takedown(struct drm_device *);
1050extern void nv04_graph_fifo_access(struct drm_device *, bool);
1051extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1052extern int nv04_graph_create_context(struct nouveau_channel *);
1053extern void nv04_graph_destroy_context(struct nouveau_channel *);
1054extern int nv04_graph_load_context(struct nouveau_channel *);
1055extern int nv04_graph_unload_context(struct drm_device *);
1056extern void nv04_graph_context_switch(struct drm_device *);
1057
1058/* nv10_graph.c */
1059extern struct nouveau_pgraph_object_class nv10_graph_grclass[];
1060extern int nv10_graph_init(struct drm_device *);
1061extern void nv10_graph_takedown(struct drm_device *);
1062extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1063extern int nv10_graph_create_context(struct nouveau_channel *);
1064extern void nv10_graph_destroy_context(struct nouveau_channel *);
1065extern int nv10_graph_load_context(struct nouveau_channel *);
1066extern int nv10_graph_unload_context(struct drm_device *);
1067extern void nv10_graph_context_switch(struct drm_device *);
cb00f7c1
FJ		 1068extern void nv10_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1069 uint32_t, uint32_t);
6ee73861
BS		 1070
1071/* nv20_graph.c */
1072extern struct nouveau_pgraph_object_class nv20_graph_grclass[];
1073extern struct nouveau_pgraph_object_class nv30_graph_grclass[];
1074extern int nv20_graph_create_context(struct nouveau_channel *);
1075extern void nv20_graph_destroy_context(struct nouveau_channel *);
1076extern int nv20_graph_load_context(struct nouveau_channel *);
1077extern int nv20_graph_unload_context(struct drm_device *);
1078extern int nv20_graph_init(struct drm_device *);
1079extern void nv20_graph_takedown(struct drm_device *);
1080extern int nv30_graph_init(struct drm_device *);
cb00f7c1
FJ		 1081extern void nv20_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1082 uint32_t, uint32_t);
6ee73861
BS		 1083
1084/* nv40_graph.c */
1085extern struct nouveau_pgraph_object_class nv40_graph_grclass[];
1086extern int nv40_graph_init(struct drm_device *);
1087extern void nv40_graph_takedown(struct drm_device *);
1088extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1089extern int nv40_graph_create_context(struct nouveau_channel *);
1090extern void nv40_graph_destroy_context(struct nouveau_channel *);
1091extern int nv40_graph_load_context(struct nouveau_channel *);
1092extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1093extern void nv40_grctx_init(struct nouveau_grctx *);
cb00f7c1
FJ		 1094extern void nv40_graph_set_region_tiling(struct drm_device *, int, uint32_t,
1095 uint32_t, uint32_t);
6ee73861
BS		 1096
1097/* nv50_graph.c */
1098extern struct nouveau_pgraph_object_class nv50_graph_grclass[];
1099extern int nv50_graph_init(struct drm_device *);
1100extern void nv50_graph_takedown(struct drm_device *);
1101extern void nv50_graph_fifo_access(struct drm_device *, bool);
1102extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1103extern int nv50_graph_create_context(struct nouveau_channel *);
1104extern void nv50_graph_destroy_context(struct nouveau_channel *);
1105extern int nv50_graph_load_context(struct nouveau_channel *);
1106extern int nv50_graph_unload_context(struct drm_device *);
1107extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1108extern int nv50_grctx_init(struct nouveau_grctx *);
6ee73861 1109
4b223eef
BS		 1110/* nvc0_graph.c */
1111extern int nvc0_graph_init(struct drm_device *);
1112extern void nvc0_graph_takedown(struct drm_device *);
1113extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1114extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1115extern int nvc0_graph_create_context(struct nouveau_channel *);
1116extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1117extern int nvc0_graph_load_context(struct nouveau_channel *);
1118extern int nvc0_graph_unload_context(struct drm_device *);
1119
6ee73861
BS		 1120/* nv04_instmem.c */
1121extern int nv04_instmem_init(struct drm_device *);
1122extern void nv04_instmem_takedown(struct drm_device *);
1123extern int nv04_instmem_suspend(struct drm_device *);
1124extern void nv04_instmem_resume(struct drm_device *);
1125extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1126 uint32_t *size);
1127extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1128extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1129extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1130extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1131
1132/* nv50_instmem.c */
1133extern int nv50_instmem_init(struct drm_device *);
1134extern void nv50_instmem_takedown(struct drm_device *);
1135extern int nv50_instmem_suspend(struct drm_device *);
1136extern void nv50_instmem_resume(struct drm_device *);
1137extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1138 uint32_t *size);
1139extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1140extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1141extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1142extern void nv50_instmem_flush(struct drm_device *);
734ee835 1143extern void nv84_instmem_flush(struct drm_device *);
63187215 1144extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1145
4b223eef
BS		 1146/* nvc0_instmem.c */
1147extern int nvc0_instmem_init(struct drm_device *);
1148extern void nvc0_instmem_takedown(struct drm_device *);
1149extern int nvc0_instmem_suspend(struct drm_device *);
1150extern void nvc0_instmem_resume(struct drm_device *);
1151extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
1152 uint32_t *size);
1153extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1154extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1155extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1156extern void nvc0_instmem_flush(struct drm_device *);
1157
6ee73861
BS		 1158/* nv04_mc.c */
1159extern int nv04_mc_init(struct drm_device *);
1160extern void nv04_mc_takedown(struct drm_device *);
1161
1162/* nv40_mc.c */
1163extern int nv40_mc_init(struct drm_device *);
1164extern void nv40_mc_takedown(struct drm_device *);
1165
1166/* nv50_mc.c */
1167extern int nv50_mc_init(struct drm_device *);
1168extern void nv50_mc_takedown(struct drm_device *);
1169
1170/* nv04_timer.c */
1171extern int nv04_timer_init(struct drm_device *);
1172extern uint64_t nv04_timer_read(struct drm_device *);
1173extern void nv04_timer_takedown(struct drm_device *);
1174
1175extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1176 unsigned long arg);
1177
1178/* nv04_dac.c */
8f1a6086 1179extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1180extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1181extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1182extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1183extern bool nv04_dac_in_use(struct drm_encoder *encoder);
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BS		 1184
1185/* nv04_dfp.c */
8f1a6086 1186extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1187extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1188extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1189 int head, bool dl);
1190extern void nv04_dfp_disable(struct drm_device *dev, int head);
1191extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1192
1193/* nv04_tv.c */
1194extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1195extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1196
1197/* nv17_tv.c */
8f1a6086 1198extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1199
1200/* nv04_display.c */
c88c2e06
FJ		 1201extern int nv04_display_early_init(struct drm_device *);
1202extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1203extern int nv04_display_create(struct drm_device *);
c88c2e06 1204extern int nv04_display_init(struct drm_device *);
6ee73861 1205extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1206
1207/* nv04_crtc.c */
1208extern int nv04_crtc_create(struct drm_device *, int index);
1209
1210/* nouveau_bo.c */
1211extern struct ttm_bo_driver nouveau_bo_driver;
1212extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1213 int size, int align, uint32_t flags,
1214 uint32_t tile_mode, uint32_t tile_flags,
1215 bool no_vm, bool mappable, struct nouveau_bo **);
1216extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1217extern int nouveau_bo_unpin(struct nouveau_bo *);
1218extern int nouveau_bo_map(struct nouveau_bo *);
1219extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1220extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1221 uint32_t busy);
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BS		 1222extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1223extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1224extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1225extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
415e6186 1226extern int nouveau_bo_sync_gpu(struct nouveau_bo *, struct nouveau_channel *);
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BS		 1227
1228/* nouveau_fence.c */
1229struct nouveau_fence;
1230extern int nouveau_fence_init(struct nouveau_channel *);
1231extern void nouveau_fence_fini(struct nouveau_channel *);
1232extern void nouveau_fence_update(struct nouveau_channel *);
1233extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1234 bool emit);
1235extern int nouveau_fence_emit(struct nouveau_fence *);
1236struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
1237extern bool nouveau_fence_signalled(void *obj, void *arg);
1238extern int nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1239extern int nouveau_fence_flush(void *obj, void *arg);
1240extern void nouveau_fence_unref(void **obj);
1241extern void *nouveau_fence_ref(void *obj);
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BS		 1242
1243/* nouveau_gem.c */
1244extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1245 int size, int align, uint32_t flags,
1246 uint32_t tile_mode, uint32_t tile_flags,
1247 bool no_vm, bool mappable, struct nouveau_bo **);
1248extern int nouveau_gem_object_new(struct drm_gem_object *);
1249extern void nouveau_gem_object_del(struct drm_gem_object *);
1250extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1251 struct drm_file *);
1252extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1253 struct drm_file *);
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BS		 1254extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1255 struct drm_file *);
1256extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1257 struct drm_file *);
1258extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1259 struct drm_file *);
1260
ee2e0131
BS		 1261/* nv10_gpio.c */
1262int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1263int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1264
45284162 1265/* nv50_gpio.c */
ee2e0131 1266int nv50_gpio_init(struct drm_device *dev);
45284162
BS		 1267int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1268int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1269void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1270
e9ebb68b
BS		 1271/* nv50_calc. */
1272int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1273 int *N1, int *M1, int *N2, int *M2, int *P);
1274int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1275 int clk, int *N, int *fN, int *M, int *P);
1276
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BS		 1277#ifndef ioread32_native
1278#ifdef __BIG_ENDIAN
1279#define ioread16_native ioread16be
1280#define iowrite16_native iowrite16be
1281#define ioread32_native ioread32be
1282#define iowrite32_native iowrite32be
1283#else /* def __BIG_ENDIAN */
1284#define ioread16_native ioread16
1285#define iowrite16_native iowrite16
1286#define ioread32_native ioread32
1287#define iowrite32_native iowrite32
1288#endif /* def __BIG_ENDIAN else */
1289#endif /* !ioread32_native */
1290
1291/* channel control reg access */
1292static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1293{
1294 return ioread32_native(chan->user + reg);
1295}
1296
1297static inline void nvchan_wr32(struct nouveau_channel *chan,
1298 unsigned reg, u32 val)
1299{
1300 iowrite32_native(val, chan->user + reg);
1301}
1302
1303/* register access */
1304static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1305{
1306 struct drm_nouveau_private *dev_priv = dev->dev_private;
1307 return ioread32_native(dev_priv->mmio + reg);
1308}
1309
1310static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1311{
1312 struct drm_nouveau_private *dev_priv = dev->dev_private;
1313 iowrite32_native(val, dev_priv->mmio + reg);
1314}
1315
2a7fdb2b 1316static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1317{
1318 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1319 nv_wr32(dev, reg, (tmp & ~mask) | val);
1320 return tmp;
49eed80a
BS		 1321}
1322
6ee73861
BS		 1323static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1324{
1325 struct drm_nouveau_private *dev_priv = dev->dev_private;
1326 return ioread8(dev_priv->mmio + reg);
1327}
1328
1329static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1330{
1331 struct drm_nouveau_private *dev_priv = dev->dev_private;
1332 iowrite8(val, dev_priv->mmio + reg);
1333}
1334
4b5c152a 1335#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1336 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1337
1338/* PRAMIN access */
1339static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1340{
1341 struct drm_nouveau_private *dev_priv = dev->dev_private;
1342 return ioread32_native(dev_priv->ramin + offset);
1343}
1344
1345static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1346{
1347 struct drm_nouveau_private *dev_priv = dev->dev_private;
1348 iowrite32_native(val, dev_priv->ramin + offset);
1349}
1350
1351/* object access */
b3beb167
BS		 1352extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1353extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1354
1355/*
1356 * Logging
1357 * Argument d is (struct drm_device *).
1358 */
1359#define NV_PRINTK(level, d, fmt, arg...) \
1360 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1361 pci_name(d->pdev), ##arg)
1362#ifndef NV_DEBUG_NOTRACE
1363#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1364 if (drm_debug & DRM_UT_DRIVER) { \
1365 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1366 __LINE__, ##arg); \
1367 } \
1368} while (0)
1369#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1370 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1371 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1372 __LINE__, ##arg); \
1373 } \
1374} while (0)
1375#else
1376#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1377 if (drm_debug & DRM_UT_DRIVER) \
1378 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1379} while (0)
1380#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1381 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1382 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1383} while (0)
1384#endif
1385#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1386#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1387#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1388#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1389#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1390
1391/* nouveau_reg_debug bitmask */
1392enum {
1393 NOUVEAU_REG_DEBUG_MC = 0x1,
1394 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1395 NOUVEAU_REG_DEBUG_FB = 0x4,
1396 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1397 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1398 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1399 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1400 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1401 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1402 NOUVEAU_REG_DEBUG_EVO = 0x200,
1403};
1404
1405#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1406 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1407 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1408} while (0)
1409
1410static inline bool
1411nv_two_heads(struct drm_device *dev)
1412{
1413 struct drm_nouveau_private *dev_priv = dev->dev_private;
1414 const int impl = dev->pci_device & 0x0ff0;
1415
1416 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1417 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1418 return true;
1419
1420 return false;
1421}
1422
1423static inline bool
1424nv_gf4_disp_arch(struct drm_device *dev)
1425{
1426 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1427}
1428
1429static inline bool
1430nv_two_reg_pll(struct drm_device *dev)
1431{
1432 struct drm_nouveau_private *dev_priv = dev->dev_private;
1433 const int impl = dev->pci_device & 0x0ff0;
1434
1435 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1436 return true;
1437 return false;
1438}
1439
acae116c
FJ		 1440static inline bool
1441nv_match_device(struct drm_device *dev, unsigned device,
1442 unsigned sub_vendor, unsigned sub_device)
1443{
1444 return dev->pdev->device == device &&
1445 dev->pdev->subsystem_vendor == sub_vendor &&
1446 dev->pdev->subsystem_device == sub_device;
1447}
1448
f03a314b
FJ		 1449#define NV_SW 0x0000506e
1450#define NV_SW_DMA_SEMAPHORE 0x00000060
1451#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1452#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1453#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
1454#define NV_SW_DMA_VBLSEM 0x0000018c
1455#define NV_SW_VBLSEM_OFFSET 0x00000400
1456#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1457#define NV_SW_VBLSEM_RELEASE 0x00000408
6ee73861
BS		 1458
1459#endif /* __NOUVEAU_DRV_H__ */
Linux kernel - Deliverables
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