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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #ifndef __NOUVEAU_DRV_H__ | |
26 | #define __NOUVEAU_DRV_H__ | |
27 | ||
28 | #define DRIVER_AUTHOR "Stephane Marchesin" | |
f887c425 | 29 | #define DRIVER_EMAIL "nouveau@lists.freedesktop.org" |
6ee73861 BS |
30 | |
31 | #define DRIVER_NAME "nouveau" | |
32 | #define DRIVER_DESC "nVidia Riva/TNT/GeForce" | |
f887c425 | 33 | #define DRIVER_DATE "20120316" |
6ee73861 | 34 | |
f887c425 | 35 | #define DRIVER_MAJOR 1 |
6ee73861 | 36 | #define DRIVER_MINOR 0 |
f887c425 | 37 | #define DRIVER_PATCHLEVEL 0 |
6ee73861 BS |
38 | |
39 | #define NOUVEAU_FAMILY 0x0000FFFF | |
40 | #define NOUVEAU_FLAGS 0xFFFF0000 | |
41 | ||
42 | #include "ttm/ttm_bo_api.h" | |
43 | #include "ttm/ttm_bo_driver.h" | |
44 | #include "ttm/ttm_placement.h" | |
45 | #include "ttm/ttm_memory.h" | |
46 | #include "ttm/ttm_module.h" | |
47 | ||
48 | struct nouveau_fpriv { | |
3f0a68d8 | 49 | spinlock_t lock; |
e8a863c1 | 50 | struct list_head channels; |
fe32b16e | 51 | struct nouveau_vm *vm; |
6ee73861 BS |
52 | }; |
53 | ||
3f0a68d8 BS |
54 | static inline struct nouveau_fpriv * |
55 | nouveau_fpriv(struct drm_file *file_priv) | |
56 | { | |
57 | return file_priv ? file_priv->driver_priv : NULL; | |
58 | } | |
59 | ||
6ee73861 BS |
60 | #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT) |
61 | ||
62 | #include "nouveau_drm.h" | |
63 | #include "nouveau_reg.h" | |
64 | #include "nouveau_bios.h" | |
274fec93 | 65 | #include "nouveau_util.h" |
f869ef88 | 66 | |
054b93e4 | 67 | struct nouveau_grctx; |
d5f42394 | 68 | struct nouveau_mem; |
f869ef88 | 69 | #include "nouveau_vm.h" |
6ee73861 BS |
70 | |
71 | #define MAX_NUM_DCB_ENTRIES 16 | |
72 | ||
5132f377 | 73 | #define NOUVEAU_MAX_CHANNEL_NR 4096 |
a0af9add | 74 | #define NOUVEAU_MAX_TILE_NR 15 |
6ee73861 | 75 | |
d5f42394 | 76 | struct nouveau_mem { |
573a2a37 BS |
77 | struct drm_device *dev; |
78 | ||
f869ef88 | 79 | struct nouveau_vma bar_vma; |
d2f96666 | 80 | struct nouveau_vma vma[2]; |
4c74eb7f | 81 | u8 page_shift; |
f869ef88 | 82 | |
8f7286f8 | 83 | struct drm_mm_node *tag; |
573a2a37 | 84 | struct list_head regions; |
26c0c9e3 | 85 | dma_addr_t *pages; |
573a2a37 BS |
86 | u32 memtype; |
87 | u64 offset; | |
88 | u64 size; | |
22b33e8e | 89 | struct sg_table *sg; |
573a2a37 BS |
90 | }; |
91 | ||
a0af9add | 92 | struct nouveau_tile_reg { |
a0af9add | 93 | bool used; |
a5cf68b0 FJ |
94 | uint32_t addr; |
95 | uint32_t limit; | |
96 | uint32_t pitch; | |
87a326a3 FJ |
97 | uint32_t zcomp; |
98 | struct drm_mm_node *tag_mem; | |
a5cf68b0 | 99 | struct nouveau_fence *fence; |
a0af9add FJ |
100 | }; |
101 | ||
6ee73861 BS |
102 | struct nouveau_bo { |
103 | struct ttm_buffer_object bo; | |
104 | struct ttm_placement placement; | |
db5c8e29 | 105 | u32 valid_domains; |
6ee73861 | 106 | u32 placements[3]; |
78ad0f7b | 107 | u32 busy_placements[3]; |
6ee73861 BS |
108 | struct ttm_bo_kmap_obj kmap; |
109 | struct list_head head; | |
110 | ||
111 | /* protected by ttm_bo_reserve() */ | |
112 | struct drm_file *reserved_by; | |
113 | struct list_head entry; | |
114 | int pbbo_index; | |
a1606a95 | 115 | bool validate_mapped; |
6ee73861 | 116 | |
fd2871af | 117 | struct list_head vma_list; |
f91bac5b | 118 | unsigned page_shift; |
6ee73861 BS |
119 | |
120 | uint32_t tile_mode; | |
121 | uint32_t tile_flags; | |
a0af9add | 122 | struct nouveau_tile_reg *tile; |
6ee73861 BS |
123 | |
124 | struct drm_gem_object *gem; | |
6ee73861 BS |
125 | int pin_refcnt; |
126 | }; | |
127 | ||
f13b3263 FJ |
128 | #define nouveau_bo_tile_layout(nvbo) \ |
129 | ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK) | |
130 | ||
6ee73861 BS |
131 | static inline struct nouveau_bo * |
132 | nouveau_bo(struct ttm_buffer_object *bo) | |
133 | { | |
134 | return container_of(bo, struct nouveau_bo, bo); | |
135 | } | |
136 | ||
137 | static inline struct nouveau_bo * | |
138 | nouveau_gem_object(struct drm_gem_object *gem) | |
139 | { | |
140 | return gem ? gem->driver_private : NULL; | |
141 | } | |
142 | ||
143 | /* TODO: submit equivalent to TTM generic API upstream? */ | |
144 | static inline void __iomem * | |
145 | nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo) | |
146 | { | |
147 | bool is_iomem; | |
148 | void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual( | |
149 | &nvbo->kmap, &is_iomem); | |
150 | WARN_ON_ONCE(ioptr && !is_iomem); | |
151 | return ioptr; | |
152 | } | |
153 | ||
6ee73861 BS |
154 | enum nouveau_flags { |
155 | NV_NFORCE = 0x10000000, | |
156 | NV_NFORCE2 = 0x20000000 | |
157 | }; | |
158 | ||
159 | #define NVOBJ_ENGINE_SW 0 | |
160 | #define NVOBJ_ENGINE_GR 1 | |
6dfdd7a6 | 161 | #define NVOBJ_ENGINE_CRYPT 2 |
7ff5441e BS |
162 | #define NVOBJ_ENGINE_COPY0 3 |
163 | #define NVOBJ_ENGINE_COPY1 4 | |
a02ccc7f | 164 | #define NVOBJ_ENGINE_MPEG 5 |
8f27c543 BS |
165 | #define NVOBJ_ENGINE_PPP NVOBJ_ENGINE_MPEG |
166 | #define NVOBJ_ENGINE_BSP 6 | |
167 | #define NVOBJ_ENGINE_VP 7 | |
c420b2dc BS |
168 | #define NVOBJ_ENGINE_FIFO 14 |
169 | #define NVOBJ_ENGINE_FENCE 15 | |
6dfdd7a6 | 170 | #define NVOBJ_ENGINE_NR 16 |
c420b2dc | 171 | #define NVOBJ_ENGINE_DISPLAY (NVOBJ_ENGINE_NR + 0) /*XXX*/ |
6ee73861 | 172 | |
a11c3198 | 173 | #define NVOBJ_FLAG_DONT_MAP (1 << 0) |
6ee73861 BS |
174 | #define NVOBJ_FLAG_ZERO_ALLOC (1 << 1) |
175 | #define NVOBJ_FLAG_ZERO_FREE (1 << 2) | |
34cf01bc | 176 | #define NVOBJ_FLAG_VM (1 << 3) |
c906ca0f | 177 | #define NVOBJ_FLAG_VM_USER (1 << 4) |
e41115d0 BS |
178 | |
179 | #define NVOBJ_CINST_GLOBAL 0xdeadbeef | |
180 | ||
6ee73861 | 181 | struct nouveau_gpuobj { |
b3beb167 | 182 | struct drm_device *dev; |
eb9bcbdc | 183 | struct kref refcount; |
6ee73861 BS |
184 | struct list_head list; |
185 | ||
e41115d0 | 186 | void *node; |
dc1e5c0d | 187 | u32 *suspend; |
6ee73861 BS |
188 | |
189 | uint32_t flags; | |
6ee73861 | 190 | |
43efc9ce | 191 | u32 size; |
f8522fc8 BS |
192 | u32 pinst; /* PRAMIN BAR offset */ |
193 | u32 cinst; /* Channel offset */ | |
194 | u64 vinst; /* VRAM address */ | |
195 | u64 linst; /* VM address */ | |
de3a6c0a | 196 | |
6ee73861 BS |
197 | uint32_t engine; |
198 | uint32_t class; | |
199 | ||
200 | void (*dtor)(struct drm_device *, struct nouveau_gpuobj *); | |
201 | void *priv; | |
202 | }; | |
203 | ||
332b242f FJ |
204 | struct nouveau_page_flip_state { |
205 | struct list_head head; | |
206 | struct drm_pending_vblank_event *event; | |
207 | int crtc, bpp, pitch, x, y; | |
208 | uint64_t offset; | |
209 | }; | |
210 | ||
e419cf09 FJ |
211 | enum nouveau_channel_mutex_class { |
212 | NOUVEAU_UCHANNEL_MUTEX, | |
213 | NOUVEAU_KCHANNEL_MUTEX | |
214 | }; | |
215 | ||
6ee73861 BS |
216 | struct nouveau_channel { |
217 | struct drm_device *dev; | |
e8a863c1 | 218 | struct list_head list; |
6ee73861 BS |
219 | int id; |
220 | ||
f091a3d4 FJ |
221 | /* references to the channel data structure */ |
222 | struct kref ref; | |
223 | /* users of the hardware channel resources, the hardware | |
224 | * context will be kicked off when it reaches zero. */ | |
225 | atomic_t users; | |
6a6b73f2 BS |
226 | struct mutex mutex; |
227 | ||
6ee73861 BS |
228 | /* owner of this fifo */ |
229 | struct drm_file *file_priv; | |
230 | /* mapping of the fifo itself */ | |
231 | struct drm_local_map *map; | |
232 | ||
25985edc | 233 | /* mapping of the regs controlling the fifo */ |
6ee73861 BS |
234 | void __iomem *user; |
235 | uint32_t user_get; | |
4e03b4af | 236 | uint32_t user_get_hi; |
6ee73861 BS |
237 | uint32_t user_put; |
238 | ||
6ee73861 | 239 | /* DMA push buffer */ |
a8eaebc6 BS |
240 | struct nouveau_gpuobj *pushbuf; |
241 | struct nouveau_bo *pushbuf_bo; | |
ce163f69 | 242 | struct nouveau_vma pushbuf_vma; |
4e03b4af | 243 | uint64_t pushbuf_base; |
6ee73861 BS |
244 | |
245 | /* Notifier memory */ | |
246 | struct nouveau_bo *notifier_bo; | |
0b718733 | 247 | struct nouveau_vma notifier_vma; |
b833ac26 | 248 | struct drm_mm notifier_heap; |
6ee73861 BS |
249 | |
250 | /* PFIFO context */ | |
a8eaebc6 | 251 | struct nouveau_gpuobj *ramfc; |
6ee73861 | 252 | |
a82dd49f | 253 | /* Execution engine contexts */ |
6dfdd7a6 | 254 | void *engctx[NVOBJ_ENGINE_NR]; |
6ee73861 BS |
255 | |
256 | /* NV50 VM */ | |
f869ef88 | 257 | struct nouveau_vm *vm; |
a8eaebc6 | 258 | struct nouveau_gpuobj *vm_pd; |
6ee73861 BS |
259 | |
260 | /* Objects */ | |
a8eaebc6 BS |
261 | struct nouveau_gpuobj *ramin; /* Private instmem */ |
262 | struct drm_mm ramin_heap; /* Private PRAMIN heap */ | |
263 | struct nouveau_ramht *ramht; /* Hash table */ | |
6ee73861 BS |
264 | |
265 | /* GPU object info for stuff used in-kernel (mm_enabled) */ | |
266 | uint32_t m2mf_ntfy; | |
267 | uint32_t vram_handle; | |
268 | uint32_t gart_handle; | |
269 | bool accel_done; | |
270 | ||
271 | /* Push buffer state (only for drm's channel on !mm_enabled) */ | |
272 | struct { | |
273 | int max; | |
274 | int free; | |
275 | int cur; | |
276 | int put; | |
277 | /* access via pushbuf_bo */ | |
9a391ad8 BS |
278 | |
279 | int ib_base; | |
280 | int ib_max; | |
281 | int ib_free; | |
282 | int ib_put; | |
6ee73861 BS |
283 | } dma; |
284 | ||
6ee73861 BS |
285 | struct { |
286 | bool active; | |
287 | char name[32]; | |
288 | struct drm_info_list info; | |
289 | } debugfs; | |
290 | }; | |
291 | ||
6dfdd7a6 BS |
292 | struct nouveau_exec_engine { |
293 | void (*destroy)(struct drm_device *, int engine); | |
294 | int (*init)(struct drm_device *, int engine); | |
6c320fef | 295 | int (*fini)(struct drm_device *, int engine, bool suspend); |
6dfdd7a6 BS |
296 | int (*context_new)(struct nouveau_channel *, int engine); |
297 | void (*context_del)(struct nouveau_channel *, int engine); | |
298 | int (*object_new)(struct nouveau_channel *, int engine, | |
299 | u32 handle, u16 class); | |
96c50082 | 300 | void (*set_tile_region)(struct drm_device *dev, int i); |
6dfdd7a6 BS |
301 | void (*tlb_flush)(struct drm_device *, int engine); |
302 | }; | |
303 | ||
6ee73861 BS |
304 | struct nouveau_instmem_engine { |
305 | void *priv; | |
306 | ||
307 | int (*init)(struct drm_device *dev); | |
308 | void (*takedown)(struct drm_device *dev); | |
309 | int (*suspend)(struct drm_device *dev); | |
310 | void (*resume)(struct drm_device *dev); | |
311 | ||
6e32fedc BS |
312 | int (*get)(struct nouveau_gpuobj *, struct nouveau_channel *, |
313 | u32 size, u32 align); | |
e41115d0 BS |
314 | void (*put)(struct nouveau_gpuobj *); |
315 | int (*map)(struct nouveau_gpuobj *); | |
316 | void (*unmap)(struct nouveau_gpuobj *); | |
317 | ||
f56cb86f | 318 | void (*flush)(struct drm_device *); |
6ee73861 BS |
319 | }; |
320 | ||
321 | struct nouveau_mc_engine { | |
322 | int (*init)(struct drm_device *dev); | |
323 | void (*takedown)(struct drm_device *dev); | |
324 | }; | |
325 | ||
326 | struct nouveau_timer_engine { | |
327 | int (*init)(struct drm_device *dev); | |
328 | void (*takedown)(struct drm_device *dev); | |
329 | uint64_t (*read)(struct drm_device *dev); | |
330 | }; | |
331 | ||
332 | struct nouveau_fb_engine { | |
cb00f7c1 | 333 | int num_tiles; |
87a326a3 | 334 | struct drm_mm tag_heap; |
20f63afe | 335 | void *priv; |
cb00f7c1 | 336 | |
6ee73861 BS |
337 | int (*init)(struct drm_device *dev); |
338 | void (*takedown)(struct drm_device *dev); | |
cb00f7c1 | 339 | |
a5cf68b0 FJ |
340 | void (*init_tile_region)(struct drm_device *dev, int i, |
341 | uint32_t addr, uint32_t size, | |
342 | uint32_t pitch, uint32_t flags); | |
343 | void (*set_tile_region)(struct drm_device *dev, int i); | |
344 | void (*free_tile_region)(struct drm_device *dev, int i); | |
6ee73861 BS |
345 | }; |
346 | ||
c88c2e06 | 347 | struct nouveau_display_engine { |
ef8389a8 | 348 | void *priv; |
c88c2e06 FJ |
349 | int (*early_init)(struct drm_device *); |
350 | void (*late_takedown)(struct drm_device *); | |
351 | int (*create)(struct drm_device *); | |
c88c2e06 | 352 | void (*destroy)(struct drm_device *); |
2a44e499 BS |
353 | int (*init)(struct drm_device *); |
354 | void (*fini)(struct drm_device *); | |
b29caa58 | 355 | |
de691855 BS |
356 | struct drm_property *dithering_mode; |
357 | struct drm_property *dithering_depth; | |
b29caa58 BS |
358 | struct drm_property *underscan_property; |
359 | struct drm_property *underscan_hborder_property; | |
360 | struct drm_property *underscan_vborder_property; | |
df26bc9c CB |
361 | /* not really hue and saturation: */ |
362 | struct drm_property *vibrant_hue_property; | |
363 | struct drm_property *color_vibrance_property; | |
c88c2e06 FJ |
364 | }; |
365 | ||
ee2e0131 | 366 | struct nouveau_gpio_engine { |
a0b25635 BS |
367 | spinlock_t lock; |
368 | struct list_head isr; | |
369 | int (*init)(struct drm_device *); | |
370 | void (*fini)(struct drm_device *); | |
371 | int (*drive)(struct drm_device *, int line, int dir, int out); | |
372 | int (*sense)(struct drm_device *, int line); | |
373 | void (*irq_enable)(struct drm_device *, int line, bool); | |
ee2e0131 BS |
374 | }; |
375 | ||
330c5988 | 376 | struct nouveau_pm_voltage_level { |
c3450239 BS |
377 | u32 voltage; /* microvolts */ |
378 | u8 vid; | |
330c5988 BS |
379 | }; |
380 | ||
381 | struct nouveau_pm_voltage { | |
382 | bool supported; | |
03ce8d9e | 383 | u8 version; |
330c5988 BS |
384 | u8 vid_mask; |
385 | ||
386 | struct nouveau_pm_voltage_level *level; | |
387 | int nr_level; | |
388 | }; | |
389 | ||
c7c039fd RS |
390 | /* Exclusive upper limits */ |
391 | #define NV_MEM_CL_DDR2_MAX 8 | |
392 | #define NV_MEM_WR_DDR2_MAX 9 | |
393 | #define NV_MEM_CL_DDR3_MAX 17 | |
394 | #define NV_MEM_WR_DDR3_MAX 17 | |
395 | #define NV_MEM_CL_GDDR3_MAX 16 | |
396 | #define NV_MEM_WR_GDDR3_MAX 18 | |
397 | #define NV_MEM_CL_GDDR5_MAX 21 | |
398 | #define NV_MEM_WR_GDDR5_MAX 20 | |
399 | ||
e614b2e7 MP |
400 | struct nouveau_pm_memtiming { |
401 | int id; | |
c7c039fd RS |
402 | |
403 | u32 reg[9]; | |
404 | u32 mr[4]; | |
405 | ||
bfb31465 RS |
406 | u8 tCWL; |
407 | ||
c7c039fd RS |
408 | u8 odt; |
409 | u8 drive_strength; | |
9a782488 RS |
410 | }; |
411 | ||
ddb20055 | 412 | struct nouveau_pm_tbl_header { |
9a782488 RS |
413 | u8 version; |
414 | u8 header_len; | |
415 | u8 entry_cnt; | |
416 | u8 entry_len; | |
417 | }; | |
418 | ||
ddb20055 | 419 | struct nouveau_pm_tbl_entry { |
2228c6fe | 420 | u8 tWR; |
bfb31465 | 421 | u8 tWTR; |
2228c6fe | 422 | u8 tCL; |
bfb31465 | 423 | u8 tRC; |
9a782488 | 424 | u8 empty_4; |
bfb31465 | 425 | u8 tRFC; /* Byte 5 */ |
9a782488 | 426 | u8 empty_6; |
bfb31465 | 427 | u8 tRAS; /* Byte 7 */ |
9a782488 | 428 | u8 empty_8; |
bfb31465 RS |
429 | u8 tRP; /* Byte 9 */ |
430 | u8 tRCDRD; | |
431 | u8 tRCDWR; | |
432 | u8 tRRD; | |
433 | u8 tUNK_13; | |
434 | u8 RAM_FT1; /* 14, a bitmask of random RAM features */ | |
435 | u8 empty_15; | |
436 | u8 tUNK_16; | |
437 | u8 empty_17; | |
438 | u8 tUNK_18; | |
439 | u8 tCWL; | |
440 | u8 tUNK_20, tUNK_21; | |
9a782488 RS |
441 | }; |
442 | ||
8d7bb400 BS |
443 | struct nouveau_pm_profile; |
444 | struct nouveau_pm_profile_func { | |
25c53c10 BS |
445 | void (*destroy)(struct nouveau_pm_profile *); |
446 | void (*init)(struct nouveau_pm_profile *); | |
447 | void (*fini)(struct nouveau_pm_profile *); | |
8d7bb400 BS |
448 | struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *); |
449 | }; | |
450 | ||
451 | struct nouveau_pm_profile { | |
452 | const struct nouveau_pm_profile_func *func; | |
453 | struct list_head head; | |
454 | char name[8]; | |
455 | }; | |
456 | ||
330c5988 BS |
457 | #define NOUVEAU_PM_MAX_LEVEL 8 |
458 | struct nouveau_pm_level { | |
8d7bb400 | 459 | struct nouveau_pm_profile profile; |
330c5988 BS |
460 | struct device_attribute dev_attr; |
461 | char name[32]; | |
462 | int id; | |
463 | ||
8d7bb400 | 464 | struct nouveau_pm_memtiming timing; |
330c5988 | 465 | u32 memory; |
085028ce | 466 | u16 memscript; |
085028ce BS |
467 | |
468 | u32 core; | |
330c5988 | 469 | u32 shader; |
9698b9a6 BS |
470 | u32 rop; |
471 | u32 copy; | |
472 | u32 daemon; | |
4fd2847e | 473 | u32 vdec; |
f3fbaf34 | 474 | u32 dom6; |
9698b9a6 BS |
475 | u32 unka0; /* nva3:nvc0 */ |
476 | u32 hub01; /* nvc0- */ | |
477 | u32 hub06; /* nvc0- */ | |
478 | u32 hub07; /* nvc0- */ | |
330c5988 | 479 | |
3b5565dd BS |
480 | u32 volt_min; /* microvolts */ |
481 | u32 volt_max; | |
c3450239 | 482 | u8 fanspeed; |
330c5988 BS |
483 | }; |
484 | ||
34e9d85a MP |
485 | struct nouveau_pm_temp_sensor_constants { |
486 | u16 offset_constant; | |
487 | s16 offset_mult; | |
40ce4279 EV |
488 | s16 offset_div; |
489 | s16 slope_mult; | |
490 | s16 slope_div; | |
34e9d85a MP |
491 | }; |
492 | ||
493 | struct nouveau_pm_threshold_temp { | |
494 | s16 critical; | |
495 | s16 down_clock; | |
496 | s16 fan_boost; | |
497 | }; | |
498 | ||
11b7d895 | 499 | struct nouveau_pm_fan { |
bc6389e4 | 500 | u32 percent; |
11b7d895 MP |
501 | u32 min_duty; |
502 | u32 max_duty; | |
3f8e11e4 | 503 | u32 pwm_freq; |
b1aa5531 | 504 | u32 pwm_divisor; |
11b7d895 MP |
505 | }; |
506 | ||
330c5988 BS |
507 | struct nouveau_pm_engine { |
508 | struct nouveau_pm_voltage voltage; | |
509 | struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL]; | |
510 | int nr_perflvl; | |
34e9d85a MP |
511 | struct nouveau_pm_temp_sensor_constants sensor_constants; |
512 | struct nouveau_pm_threshold_temp threshold_temp; | |
11b7d895 | 513 | struct nouveau_pm_fan fan; |
330c5988 | 514 | |
8d7bb400 BS |
515 | struct nouveau_pm_profile *profile_ac; |
516 | struct nouveau_pm_profile *profile_dc; | |
25c53c10 | 517 | struct nouveau_pm_profile *profile; |
8d7bb400 BS |
518 | struct list_head profiles; |
519 | ||
330c5988 BS |
520 | struct nouveau_pm_level boot; |
521 | struct nouveau_pm_level *cur; | |
522 | ||
8155cac4 | 523 | struct device *hwmon; |
6032649d | 524 | struct notifier_block acpi_nb; |
8155cac4 | 525 | |
77e7da68 BS |
526 | int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *); |
527 | void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *); | |
dd1da8de | 528 | int (*clocks_set)(struct drm_device *, void *); |
77e7da68 | 529 | |
330c5988 BS |
530 | int (*voltage_get)(struct drm_device *); |
531 | int (*voltage_set)(struct drm_device *, int voltage); | |
675aac03 BS |
532 | int (*pwm_get)(struct drm_device *, int line, u32*, u32*); |
533 | int (*pwm_set)(struct drm_device *, int line, u32, u32); | |
8155cac4 | 534 | int (*temp_get)(struct drm_device *); |
330c5988 BS |
535 | }; |
536 | ||
60d2a88a | 537 | struct nouveau_vram_engine { |
987eec10 | 538 | struct nouveau_mm mm; |
24f246ac | 539 | |
60d2a88a | 540 | int (*init)(struct drm_device *); |
24f246ac | 541 | void (*takedown)(struct drm_device *dev); |
60d2a88a | 542 | int (*get)(struct drm_device *, u64, u32 align, u32 size_nc, |
d5f42394 BS |
543 | u32 type, struct nouveau_mem **); |
544 | void (*put)(struct drm_device *, struct nouveau_mem **); | |
60d2a88a BS |
545 | |
546 | bool (*flags_valid)(struct drm_device *, u32 tile_flags); | |
547 | }; | |
548 | ||
6ee73861 BS |
549 | struct nouveau_engine { |
550 | struct nouveau_instmem_engine instmem; | |
551 | struct nouveau_mc_engine mc; | |
552 | struct nouveau_timer_engine timer; | |
553 | struct nouveau_fb_engine fb; | |
c88c2e06 | 554 | struct nouveau_display_engine display; |
ee2e0131 | 555 | struct nouveau_gpio_engine gpio; |
330c5988 | 556 | struct nouveau_pm_engine pm; |
60d2a88a | 557 | struct nouveau_vram_engine vram; |
6ee73861 BS |
558 | }; |
559 | ||
560 | struct nouveau_pll_vals { | |
561 | union { | |
562 | struct { | |
563 | #ifdef __BIG_ENDIAN | |
564 | uint8_t N1, M1, N2, M2; | |
565 | #else | |
566 | uint8_t M1, N1, M2, N2; | |
567 | #endif | |
568 | }; | |
569 | struct { | |
570 | uint16_t NM1, NM2; | |
571 | } __attribute__((packed)); | |
572 | }; | |
573 | int log2P; | |
574 | ||
575 | int refclk; | |
576 | }; | |
577 | ||
578 | enum nv04_fp_display_regs { | |
579 | FP_DISPLAY_END, | |
580 | FP_TOTAL, | |
581 | FP_CRTC, | |
582 | FP_SYNC_START, | |
583 | FP_SYNC_END, | |
584 | FP_VALID_START, | |
585 | FP_VALID_END | |
586 | }; | |
587 | ||
588 | struct nv04_crtc_reg { | |
cbab95db | 589 | unsigned char MiscOutReg; |
4a9f822f | 590 | uint8_t CRTC[0xa0]; |
6ee73861 BS |
591 | uint8_t CR58[0x10]; |
592 | uint8_t Sequencer[5]; | |
593 | uint8_t Graphics[9]; | |
594 | uint8_t Attribute[21]; | |
cbab95db | 595 | unsigned char DAC[768]; |
6ee73861 BS |
596 | |
597 | /* PCRTC regs */ | |
598 | uint32_t fb_start; | |
599 | uint32_t crtc_cfg; | |
600 | uint32_t cursor_cfg; | |
601 | uint32_t gpio_ext; | |
602 | uint32_t crtc_830; | |
603 | uint32_t crtc_834; | |
604 | uint32_t crtc_850; | |
605 | uint32_t crtc_eng_ctrl; | |
606 | ||
607 | /* PRAMDAC regs */ | |
608 | uint32_t nv10_cursync; | |
609 | struct nouveau_pll_vals pllvals; | |
610 | uint32_t ramdac_gen_ctrl; | |
611 | uint32_t ramdac_630; | |
612 | uint32_t ramdac_634; | |
613 | uint32_t tv_setup; | |
614 | uint32_t tv_vtotal; | |
615 | uint32_t tv_vskew; | |
616 | uint32_t tv_vsync_delay; | |
617 | uint32_t tv_htotal; | |
618 | uint32_t tv_hskew; | |
619 | uint32_t tv_hsync_delay; | |
620 | uint32_t tv_hsync_delay2; | |
621 | uint32_t fp_horiz_regs[7]; | |
622 | uint32_t fp_vert_regs[7]; | |
623 | uint32_t dither; | |
624 | uint32_t fp_control; | |
625 | uint32_t dither_regs[6]; | |
626 | uint32_t fp_debug_0; | |
627 | uint32_t fp_debug_1; | |
628 | uint32_t fp_debug_2; | |
629 | uint32_t fp_margin_color; | |
630 | uint32_t ramdac_8c0; | |
631 | uint32_t ramdac_a20; | |
632 | uint32_t ramdac_a24; | |
633 | uint32_t ramdac_a34; | |
634 | uint32_t ctv_regs[38]; | |
635 | }; | |
636 | ||
637 | struct nv04_output_reg { | |
638 | uint32_t output; | |
639 | int head; | |
640 | }; | |
641 | ||
642 | struct nv04_mode_state { | |
cbab95db | 643 | struct nv04_crtc_reg crtc_reg[2]; |
6ee73861 BS |
644 | uint32_t pllsel; |
645 | uint32_t sel_clk; | |
6ee73861 BS |
646 | }; |
647 | ||
648 | enum nouveau_card_type { | |
2f5394c3 | 649 | NV_04 = 0x04, |
6ee73861 BS |
650 | NV_10 = 0x10, |
651 | NV_20 = 0x20, | |
652 | NV_30 = 0x30, | |
653 | NV_40 = 0x40, | |
654 | NV_50 = 0x50, | |
4b223eef | 655 | NV_C0 = 0xc0, |
2f5394c3 | 656 | NV_D0 = 0xd0, |
68455a43 | 657 | NV_E0 = 0xe0, |
6ee73861 BS |
658 | }; |
659 | ||
660 | struct drm_nouveau_private { | |
661 | struct drm_device *dev; | |
aba99a84 | 662 | bool noaccel; |
6ee73861 BS |
663 | |
664 | /* the card type, takes NV_* as values */ | |
665 | enum nouveau_card_type card_type; | |
666 | /* exact chipset, derived from NV_PMC_BOOT_0 */ | |
667 | int chipset; | |
668 | int flags; | |
f2cbe46f | 669 | u32 crystal; |
6ee73861 BS |
670 | |
671 | void __iomem *mmio; | |
5125bfd8 | 672 | |
e05d7eae | 673 | spinlock_t ramin_lock; |
6ee73861 | 674 | void __iomem *ramin; |
5125bfd8 BS |
675 | u32 ramin_size; |
676 | u32 ramin_base; | |
677 | bool ramin_available; | |
e05d7eae | 678 | struct drm_mm ramin_heap; |
6dfdd7a6 | 679 | struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR]; |
e05d7eae | 680 | struct list_head gpuobj_list; |
b8c157d3 | 681 | struct list_head classes; |
6ee73861 | 682 | |
ac8fb975 BS |
683 | struct nouveau_bo *vga_ram; |
684 | ||
35fa2f2a | 685 | /* interrupt handling */ |
8f8a5448 | 686 | void (*irq_handler[32])(struct drm_device *); |
35fa2f2a | 687 | bool msi_enabled; |
ab838338 | 688 | |
6ee73861 BS |
689 | struct list_head vbl_waiting; |
690 | ||
691 | struct { | |
ba4420c2 | 692 | struct drm_global_reference mem_global_ref; |
6ee73861 BS |
693 | struct ttm_bo_global_ref bo_global_ref; |
694 | struct ttm_bo_device bdev; | |
6ee73861 BS |
695 | atomic_t validate_sequence; |
696 | } ttm; | |
697 | ||
0c6c1c2f FJ |
698 | struct { |
699 | spinlock_t lock; | |
700 | struct drm_mm heap; | |
701 | struct nouveau_bo *bo; | |
702 | } fence; | |
703 | ||
cff5c133 BS |
704 | struct { |
705 | spinlock_t lock; | |
706 | struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR]; | |
707 | } channels; | |
6ee73861 BS |
708 | |
709 | struct nouveau_engine engine; | |
710 | struct nouveau_channel *channel; | |
711 | ||
ff9e5279 MM |
712 | /* For PFIFO and PGRAPH. */ |
713 | spinlock_t context_switch_lock; | |
714 | ||
04eb34a4 BS |
715 | /* VM/PRAMIN flush, legacy PRAMIN aperture */ |
716 | spinlock_t vm_lock; | |
717 | ||
6ee73861 | 718 | /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ |
e05c5a31 BS |
719 | struct nouveau_ramht *ramht; |
720 | struct nouveau_gpuobj *ramfc; | |
721 | struct nouveau_gpuobj *ramro; | |
722 | ||
6ee73861 | 723 | uint32_t ramin_rsvd_vram; |
6ee73861 | 724 | |
6ee73861 BS |
725 | struct { |
726 | enum { | |
727 | NOUVEAU_GART_NONE = 0, | |
58e6c7a9 BS |
728 | NOUVEAU_GART_AGP, /* AGP */ |
729 | NOUVEAU_GART_PDMA, /* paged dma object */ | |
730 | NOUVEAU_GART_HW /* on-chip gart/vm */ | |
6ee73861 BS |
731 | } type; |
732 | uint64_t aper_base; | |
733 | uint64_t aper_size; | |
734 | uint64_t aper_free; | |
735 | ||
7948758d BS |
736 | struct ttm_backend_func *func; |
737 | ||
738 | struct { | |
739 | struct page *page; | |
740 | dma_addr_t addr; | |
741 | } dummy; | |
742 | ||
6ee73861 | 743 | struct nouveau_gpuobj *sg_ctxdma; |
6ee73861 BS |
744 | } gart_info; |
745 | ||
a0af9add | 746 | /* nv10-nv40 tiling regions */ |
a5cf68b0 FJ |
747 | struct { |
748 | struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR]; | |
749 | spinlock_t lock; | |
750 | } tile; | |
a0af9add | 751 | |
a76fb4e8 | 752 | /* VRAM/fb configuration */ |
7ad2d31c BS |
753 | enum { |
754 | NV_MEM_TYPE_UNKNOWN = 0, | |
755 | NV_MEM_TYPE_STOLEN, | |
756 | NV_MEM_TYPE_SGRAM, | |
757 | NV_MEM_TYPE_SDRAM, | |
758 | NV_MEM_TYPE_DDR1, | |
759 | NV_MEM_TYPE_DDR2, | |
760 | NV_MEM_TYPE_DDR3, | |
761 | NV_MEM_TYPE_GDDR2, | |
762 | NV_MEM_TYPE_GDDR3, | |
763 | NV_MEM_TYPE_GDDR4, | |
764 | NV_MEM_TYPE_GDDR5 | |
765 | } vram_type; | |
a76fb4e8 BS |
766 | uint64_t vram_size; |
767 | uint64_t vram_sys_base; | |
c7c039fd | 768 | bool vram_rank_B; |
a76fb4e8 | 769 | |
a76fb4e8 BS |
770 | uint64_t fb_available_size; |
771 | uint64_t fb_mappable_pages; | |
772 | uint64_t fb_aper_free; | |
773 | int fb_mtrr; | |
774 | ||
f869ef88 BS |
775 | /* BAR control (NV50-) */ |
776 | struct nouveau_vm *bar1_vm; | |
777 | struct nouveau_vm *bar3_vm; | |
778 | ||
6ee73861 | 779 | /* G8x/G9x virtual address space */ |
4c136142 | 780 | struct nouveau_vm *chan_vm; |
6ee73861 | 781 | |
04a39c57 | 782 | struct nvbios vbios; |
b4c26818 | 783 | u8 *mxms; |
486a45c2 | 784 | struct list_head i2c_ports; |
6ee73861 BS |
785 | |
786 | struct nv04_mode_state mode_reg; | |
787 | struct nv04_mode_state saved_reg; | |
788 | uint32_t saved_vga_font[4][16384]; | |
789 | uint32_t crtc_owner; | |
790 | uint32_t dac_users[4]; | |
791 | ||
6ee73861 | 792 | struct backlight_device *backlight; |
6ee73861 | 793 | |
6ee73861 BS |
794 | struct { |
795 | struct dentry *channel_root; | |
796 | } debugfs; | |
38651674 | 797 | |
8be48d92 | 798 | struct nouveau_fbdev *nfbdev; |
06415c56 | 799 | struct apertures_struct *apertures; |
6ee73861 BS |
800 | }; |
801 | ||
2730723b FJ |
802 | static inline struct drm_nouveau_private * |
803 | nouveau_private(struct drm_device *dev) | |
804 | { | |
805 | return dev->dev_private; | |
806 | } | |
807 | ||
6ee73861 BS |
808 | static inline struct drm_nouveau_private * |
809 | nouveau_bdev(struct ttm_bo_device *bd) | |
810 | { | |
811 | return container_of(bd, struct drm_nouveau_private, ttm.bdev); | |
812 | } | |
813 | ||
814 | static inline int | |
815 | nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo) | |
816 | { | |
817 | struct nouveau_bo *prev; | |
818 | ||
819 | if (!pnvbo) | |
820 | return -EINVAL; | |
821 | prev = *pnvbo; | |
822 | ||
823 | *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL; | |
824 | if (prev) { | |
825 | struct ttm_buffer_object *bo = &prev->bo; | |
826 | ||
827 | ttm_bo_unref(&bo); | |
828 | } | |
829 | ||
830 | return 0; | |
831 | } | |
832 | ||
6ee73861 | 833 | /* nouveau_drv.c */ |
03bc9675 | 834 | extern int nouveau_modeset; |
de5899bd | 835 | extern int nouveau_agpmode; |
6ee73861 BS |
836 | extern int nouveau_duallink; |
837 | extern int nouveau_uscript_lvds; | |
838 | extern int nouveau_uscript_tmds; | |
839 | extern int nouveau_vram_pushbuf; | |
840 | extern int nouveau_vram_notify; | |
7ad2d31c | 841 | extern char *nouveau_vram_type; |
6ee73861 | 842 | extern int nouveau_fbpercrtc; |
f4053509 | 843 | extern int nouveau_tv_disable; |
6ee73861 BS |
844 | extern char *nouveau_tv_norm; |
845 | extern int nouveau_reg_debug; | |
846 | extern char *nouveau_vbios; | |
a1470890 | 847 | extern int nouveau_ignorelid; |
a32ed69d MK |
848 | extern int nouveau_nofbaccel; |
849 | extern int nouveau_noaccel; | |
0cba1b76 | 850 | extern int nouveau_force_post; |
da647d5b | 851 | extern int nouveau_override_conntype; |
6f876986 BS |
852 | extern char *nouveau_perflvl; |
853 | extern int nouveau_perflvl_wr; | |
35fa2f2a | 854 | extern int nouveau_msi; |
0411de85 | 855 | extern int nouveau_ctxfw; |
b4c26818 | 856 | extern int nouveau_mxmdcb; |
6ee73861 | 857 | |
6a9ee8af DA |
858 | extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state); |
859 | extern int nouveau_pci_resume(struct pci_dev *pdev); | |
860 | ||
6ee73861 | 861 | /* nouveau_state.c */ |
3f0a68d8 | 862 | extern int nouveau_open(struct drm_device *, struct drm_file *); |
6ee73861 | 863 | extern void nouveau_preclose(struct drm_device *dev, struct drm_file *); |
3f0a68d8 | 864 | extern void nouveau_postclose(struct drm_device *, struct drm_file *); |
6ee73861 BS |
865 | extern int nouveau_load(struct drm_device *, unsigned long flags); |
866 | extern int nouveau_firstopen(struct drm_device *); | |
867 | extern void nouveau_lastclose(struct drm_device *); | |
868 | extern int nouveau_unload(struct drm_device *); | |
869 | extern int nouveau_ioctl_getparam(struct drm_device *, void *data, | |
870 | struct drm_file *); | |
871 | extern int nouveau_ioctl_setparam(struct drm_device *, void *data, | |
872 | struct drm_file *); | |
12fb9525 BS |
873 | extern bool nouveau_wait_eq(struct drm_device *, uint64_t timeout, |
874 | uint32_t reg, uint32_t mask, uint32_t val); | |
875 | extern bool nouveau_wait_ne(struct drm_device *, uint64_t timeout, | |
876 | uint32_t reg, uint32_t mask, uint32_t val); | |
78e2933d BS |
877 | extern bool nouveau_wait_cb(struct drm_device *, u64 timeout, |
878 | bool (*cond)(void *), void *); | |
6ee73861 BS |
879 | extern bool nouveau_wait_for_idle(struct drm_device *); |
880 | extern int nouveau_card_init(struct drm_device *); | |
6ee73861 BS |
881 | |
882 | /* nouveau_mem.c */ | |
fbd2895e BS |
883 | extern int nouveau_mem_vram_init(struct drm_device *); |
884 | extern void nouveau_mem_vram_fini(struct drm_device *); | |
885 | extern int nouveau_mem_gart_init(struct drm_device *); | |
886 | extern void nouveau_mem_gart_fini(struct drm_device *); | |
6ee73861 | 887 | extern int nouveau_mem_init_agp(struct drm_device *); |
e04d8e82 | 888 | extern int nouveau_mem_reset_agp(struct drm_device *); |
6ee73861 | 889 | extern void nouveau_mem_close(struct drm_device *); |
60d2a88a | 890 | extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags); |
085028ce BS |
891 | extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq, |
892 | struct nouveau_pm_memtiming *); | |
fd99fd61 BS |
893 | extern void nouveau_mem_timing_read(struct drm_device *, |
894 | struct nouveau_pm_memtiming *); | |
c70c41e8 | 895 | extern int nouveau_mem_vbios_type(struct drm_device *); |
a5cf68b0 FJ |
896 | extern struct nouveau_tile_reg *nv10_mem_set_tiling( |
897 | struct drm_device *dev, uint32_t addr, uint32_t size, | |
898 | uint32_t pitch, uint32_t flags); | |
899 | extern void nv10_mem_put_tile_region(struct drm_device *dev, | |
900 | struct nouveau_tile_reg *tile, | |
901 | struct nouveau_fence *fence); | |
573a2a37 | 902 | extern const struct ttm_mem_type_manager_func nouveau_vram_manager; |
26c0c9e3 | 903 | extern const struct ttm_mem_type_manager_func nouveau_gart_manager; |
6ee73861 BS |
904 | |
905 | /* nouveau_notifier.c */ | |
906 | extern int nouveau_notifier_init_channel(struct nouveau_channel *); | |
907 | extern void nouveau_notifier_takedown_channel(struct nouveau_channel *); | |
908 | extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle, | |
73412c38 BS |
909 | int cout, uint32_t start, uint32_t end, |
910 | uint32_t *offset); | |
6ee73861 BS |
911 | extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *); |
912 | extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data, | |
913 | struct drm_file *); | |
914 | extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data, | |
915 | struct drm_file *); | |
916 | ||
917 | /* nouveau_channel.c */ | |
918 | extern struct drm_ioctl_desc nouveau_ioctls[]; | |
919 | extern int nouveau_max_ioctl; | |
920 | extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *); | |
6ee73861 BS |
921 | extern int nouveau_channel_alloc(struct drm_device *dev, |
922 | struct nouveau_channel **chan, | |
923 | struct drm_file *file_priv, | |
924 | uint32_t fb_ctxdma, uint32_t tt_ctxdma); | |
cff5c133 | 925 | extern struct nouveau_channel * |
feeb0aec FJ |
926 | nouveau_channel_get_unlocked(struct nouveau_channel *); |
927 | extern struct nouveau_channel * | |
e8a863c1 | 928 | nouveau_channel_get(struct drm_file *, int id); |
feeb0aec | 929 | extern void nouveau_channel_put_unlocked(struct nouveau_channel **); |
cff5c133 | 930 | extern void nouveau_channel_put(struct nouveau_channel **); |
f091a3d4 FJ |
931 | extern void nouveau_channel_ref(struct nouveau_channel *chan, |
932 | struct nouveau_channel **pchan); | |
6dccd311 | 933 | extern void nouveau_channel_idle(struct nouveau_channel *chan); |
6ee73861 BS |
934 | |
935 | /* nouveau_object.c */ | |
6dfdd7a6 BS |
936 | #define NVOBJ_ENGINE_ADD(d, e, p) do { \ |
937 | struct drm_nouveau_private *dev_priv = (d)->dev_private; \ | |
938 | dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \ | |
939 | } while (0) | |
940 | ||
941 | #define NVOBJ_ENGINE_DEL(d, e) do { \ | |
942 | struct drm_nouveau_private *dev_priv = (d)->dev_private; \ | |
943 | dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \ | |
944 | } while (0) | |
945 | ||
0b89a072 | 946 | #define NVOBJ_CLASS(d, c, e) do { \ |
b8c157d3 BS |
947 | int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \ |
948 | if (ret) \ | |
949 | return ret; \ | |
71298e2f | 950 | } while (0) |
b8c157d3 | 951 | |
0b89a072 | 952 | #define NVOBJ_MTHD(d, c, m, e) do { \ |
b8c157d3 BS |
953 | int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \ |
954 | if (ret) \ | |
955 | return ret; \ | |
71298e2f | 956 | } while (0) |
b8c157d3 | 957 | |
6ee73861 BS |
958 | extern int nouveau_gpuobj_early_init(struct drm_device *); |
959 | extern int nouveau_gpuobj_init(struct drm_device *); | |
960 | extern void nouveau_gpuobj_takedown(struct drm_device *); | |
6ee73861 | 961 | extern int nouveau_gpuobj_suspend(struct drm_device *dev); |
6ee73861 | 962 | extern void nouveau_gpuobj_resume(struct drm_device *dev); |
b8c157d3 BS |
963 | extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng); |
964 | extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd, | |
965 | int (*exec)(struct nouveau_channel *, | |
71298e2f | 966 | u32 class, u32 mthd, u32 data)); |
b8c157d3 | 967 | extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32); |
274fec93 | 968 | extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32); |
6ee73861 BS |
969 | extern int nouveau_gpuobj_channel_init(struct nouveau_channel *, |
970 | uint32_t vram_h, uint32_t tt_h); | |
971 | extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *); | |
972 | extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *, | |
973 | uint32_t size, int align, uint32_t flags, | |
974 | struct nouveau_gpuobj **); | |
a8eaebc6 BS |
975 | extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *, |
976 | struct nouveau_gpuobj **); | |
43efc9ce BS |
977 | extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst, |
978 | u32 size, u32 flags, | |
a8eaebc6 | 979 | struct nouveau_gpuobj **); |
6ee73861 BS |
980 | extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class, |
981 | uint64_t offset, uint64_t size, int access, | |
982 | int target, struct nouveau_gpuobj **); | |
ceac3099 | 983 | extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, u32 handle, int class); |
7f4a195f BS |
984 | extern int nv50_gpuobj_dma_new(struct nouveau_channel *, int class, u64 base, |
985 | u64 size, int target, int access, u32 type, | |
986 | u32 comp, struct nouveau_gpuobj **pobj); | |
987 | extern void nv50_gpuobj_dma_init(struct nouveau_gpuobj *, u32 offset, | |
988 | int class, u64 base, u64 size, int target, | |
989 | int access, u32 type, u32 comp); | |
6ee73861 BS |
990 | extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data, |
991 | struct drm_file *); | |
992 | extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data, | |
993 | struct drm_file *); | |
994 | ||
995 | /* nouveau_irq.c */ | |
35fa2f2a BS |
996 | extern int nouveau_irq_init(struct drm_device *); |
997 | extern void nouveau_irq_fini(struct drm_device *); | |
6ee73861 | 998 | extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS); |
8f8a5448 BS |
999 | extern void nouveau_irq_register(struct drm_device *, int status_bit, |
1000 | void (*)(struct drm_device *)); | |
1001 | extern void nouveau_irq_unregister(struct drm_device *, int status_bit); | |
6ee73861 BS |
1002 | extern void nouveau_irq_preinstall(struct drm_device *); |
1003 | extern int nouveau_irq_postinstall(struct drm_device *); | |
1004 | extern void nouveau_irq_uninstall(struct drm_device *); | |
1005 | ||
1006 | /* nouveau_sgdma.c */ | |
1007 | extern int nouveau_sgdma_init(struct drm_device *); | |
1008 | extern void nouveau_sgdma_takedown(struct drm_device *); | |
fd70b6cd FJ |
1009 | extern uint32_t nouveau_sgdma_get_physical(struct drm_device *, |
1010 | uint32_t offset); | |
649bf3ca JG |
1011 | extern struct ttm_tt *nouveau_sgdma_create_ttm(struct ttm_bo_device *bdev, |
1012 | unsigned long size, | |
1013 | uint32_t page_flags, | |
1014 | struct page *dummy_read_page); | |
6ee73861 BS |
1015 | |
1016 | /* nouveau_debugfs.c */ | |
1017 | #if defined(CONFIG_DRM_NOUVEAU_DEBUG) | |
1018 | extern int nouveau_debugfs_init(struct drm_minor *); | |
1019 | extern void nouveau_debugfs_takedown(struct drm_minor *); | |
1020 | extern int nouveau_debugfs_channel_init(struct nouveau_channel *); | |
1021 | extern void nouveau_debugfs_channel_fini(struct nouveau_channel *); | |
1022 | #else | |
1023 | static inline int | |
1024 | nouveau_debugfs_init(struct drm_minor *minor) | |
1025 | { | |
1026 | return 0; | |
1027 | } | |
1028 | ||
1029 | static inline void nouveau_debugfs_takedown(struct drm_minor *minor) | |
1030 | { | |
1031 | } | |
1032 | ||
1033 | static inline int | |
1034 | nouveau_debugfs_channel_init(struct nouveau_channel *chan) | |
1035 | { | |
1036 | return 0; | |
1037 | } | |
1038 | ||
1039 | static inline void | |
1040 | nouveau_debugfs_channel_fini(struct nouveau_channel *chan) | |
1041 | { | |
1042 | } | |
1043 | #endif | |
1044 | ||
1045 | /* nouveau_dma.c */ | |
48aca13f | 1046 | extern void nouveau_dma_init(struct nouveau_channel *); |
9a391ad8 | 1047 | extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size); |
6ee73861 BS |
1048 | |
1049 | /* nouveau_acpi.c */ | |
afeb3e11 | 1050 | #define ROM_BIOS_PAGE 4096 |
2f41a7f1 | 1051 | #if defined(CONFIG_ACPI) |
6a9ee8af DA |
1052 | void nouveau_register_dsm_handler(void); |
1053 | void nouveau_unregister_dsm_handler(void); | |
d099230c | 1054 | void nouveau_switcheroo_optimus_dsm(void); |
afeb3e11 DA |
1055 | int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len); |
1056 | bool nouveau_acpi_rom_supported(struct pci_dev *pdev); | |
a6ed76d7 | 1057 | int nouveau_acpi_edid(struct drm_device *, struct drm_connector *); |
8edb381d DA |
1058 | #else |
1059 | static inline void nouveau_register_dsm_handler(void) {} | |
1060 | static inline void nouveau_unregister_dsm_handler(void) {} | |
d099230c | 1061 | static inline void nouveau_switcheroo_optimus_dsm(void) {} |
afeb3e11 DA |
1062 | static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; } |
1063 | static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; } | |
5620ba46 | 1064 | static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; } |
8edb381d | 1065 | #endif |
6ee73861 BS |
1066 | |
1067 | /* nouveau_backlight.c */ | |
1068 | #ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT | |
10b461e4 BS |
1069 | extern int nouveau_backlight_init(struct drm_device *); |
1070 | extern void nouveau_backlight_exit(struct drm_device *); | |
6ee73861 | 1071 | #else |
10b461e4 | 1072 | static inline int nouveau_backlight_init(struct drm_device *dev) |
6ee73861 BS |
1073 | { |
1074 | return 0; | |
1075 | } | |
1076 | ||
10b461e4 | 1077 | static inline void nouveau_backlight_exit(struct drm_device *dev) { } |
6ee73861 BS |
1078 | #endif |
1079 | ||
1080 | /* nouveau_bios.c */ | |
1081 | extern int nouveau_bios_init(struct drm_device *); | |
1082 | extern void nouveau_bios_takedown(struct drm_device *dev); | |
1083 | extern int nouveau_run_vbios_init(struct drm_device *); | |
1084 | extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table, | |
02e4f587 | 1085 | struct dcb_entry *, int crtc); |
59ef9742 | 1086 | extern void nouveau_bios_init_exec(struct drm_device *, uint16_t table); |
6ee73861 BS |
1087 | extern struct dcb_connector_table_entry * |
1088 | nouveau_bios_connector_entry(struct drm_device *, int index); | |
855a95e4 | 1089 | extern u32 get_pll_register(struct drm_device *, enum pll_types); |
6ee73861 BS |
1090 | extern int get_pll_limits(struct drm_device *, uint32_t limit_match, |
1091 | struct pll_lims *); | |
02e4f587 BS |
1092 | extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk, |
1093 | struct dcb_entry *, int crtc); | |
6ee73861 BS |
1094 | extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *); |
1095 | extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *); | |
1096 | extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk, | |
1097 | bool *dl, bool *if_is_24bit); | |
1098 | extern int run_tmds_table(struct drm_device *, struct dcb_entry *, | |
1099 | int head, int pxclk); | |
1100 | extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head, | |
1101 | enum LVDS_script, int pxclk); | |
721b0821 | 1102 | bool bios_encoder_match(struct dcb_entry *, u32 hash); |
6ee73861 | 1103 | |
b4c26818 BS |
1104 | /* nouveau_mxm.c */ |
1105 | int nouveau_mxm_init(struct drm_device *dev); | |
1106 | void nouveau_mxm_fini(struct drm_device *dev); | |
1107 | ||
6ee73861 BS |
1108 | /* nouveau_ttm.c */ |
1109 | int nouveau_ttm_global_init(struct drm_nouveau_private *); | |
1110 | void nouveau_ttm_global_release(struct drm_nouveau_private *); | |
1111 | int nouveau_ttm_mmap(struct file *, struct vm_area_struct *); | |
1112 | ||
25575b41 BS |
1113 | /* nouveau_hdmi.c */ |
1114 | void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *); | |
1115 | ||
6ee73861 | 1116 | /* nv04_fb.c */ |
7ad2d31c | 1117 | extern int nv04_fb_vram_init(struct drm_device *); |
6ee73861 BS |
1118 | extern int nv04_fb_init(struct drm_device *); |
1119 | extern void nv04_fb_takedown(struct drm_device *); | |
1120 | ||
1121 | /* nv10_fb.c */ | |
7ad2d31c BS |
1122 | extern int nv10_fb_vram_init(struct drm_device *dev); |
1123 | extern int nv1a_fb_vram_init(struct drm_device *dev); | |
6ee73861 BS |
1124 | extern int nv10_fb_init(struct drm_device *); |
1125 | extern void nv10_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1126 | extern void nv10_fb_init_tile_region(struct drm_device *dev, int i, |
1127 | uint32_t addr, uint32_t size, | |
1128 | uint32_t pitch, uint32_t flags); | |
1129 | extern void nv10_fb_set_tile_region(struct drm_device *dev, int i); | |
1130 | extern void nv10_fb_free_tile_region(struct drm_device *dev, int i); | |
6ee73861 | 1131 | |
d81c19e3 BS |
1132 | /* nv20_fb.c */ |
1133 | extern int nv20_fb_vram_init(struct drm_device *dev); | |
1134 | extern int nv20_fb_init(struct drm_device *); | |
1135 | extern void nv20_fb_takedown(struct drm_device *); | |
1136 | extern void nv20_fb_init_tile_region(struct drm_device *dev, int i, | |
1137 | uint32_t addr, uint32_t size, | |
1138 | uint32_t pitch, uint32_t flags); | |
1139 | extern void nv20_fb_set_tile_region(struct drm_device *dev, int i); | |
1140 | extern void nv20_fb_free_tile_region(struct drm_device *dev, int i); | |
1141 | ||
8bded189 FJ |
1142 | /* nv30_fb.c */ |
1143 | extern int nv30_fb_init(struct drm_device *); | |
1144 | extern void nv30_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1145 | extern void nv30_fb_init_tile_region(struct drm_device *dev, int i, |
1146 | uint32_t addr, uint32_t size, | |
1147 | uint32_t pitch, uint32_t flags); | |
1148 | extern void nv30_fb_free_tile_region(struct drm_device *dev, int i); | |
8bded189 | 1149 | |
6ee73861 | 1150 | /* nv40_fb.c */ |
ff92a6cd | 1151 | extern int nv40_fb_vram_init(struct drm_device *dev); |
6ee73861 BS |
1152 | extern int nv40_fb_init(struct drm_device *); |
1153 | extern void nv40_fb_takedown(struct drm_device *); | |
a5cf68b0 FJ |
1154 | extern void nv40_fb_set_tile_region(struct drm_device *dev, int i); |
1155 | ||
304424e1 MK |
1156 | /* nv50_fb.c */ |
1157 | extern int nv50_fb_init(struct drm_device *); | |
1158 | extern void nv50_fb_takedown(struct drm_device *); | |
6fdb383e | 1159 | extern void nv50_fb_vm_trap(struct drm_device *, int display); |
304424e1 | 1160 | |
4b223eef BS |
1161 | /* nvc0_fb.c */ |
1162 | extern int nvc0_fb_init(struct drm_device *); | |
1163 | extern void nvc0_fb_takedown(struct drm_device *); | |
1164 | ||
6ee73861 | 1165 | /* nv04_graph.c */ |
4976986b | 1166 | extern int nv04_graph_create(struct drm_device *); |
4976986b | 1167 | extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16); |
332b242f FJ |
1168 | extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan, |
1169 | u32 class, u32 mthd, u32 data); | |
274fec93 | 1170 | extern struct nouveau_bitfield nv04_graph_nsource[]; |
6ee73861 BS |
1171 | |
1172 | /* nv10_graph.c */ | |
d11db279 | 1173 | extern int nv10_graph_create(struct drm_device *); |
6ee73861 | 1174 | extern struct nouveau_channel *nv10_graph_channel(struct drm_device *); |
274fec93 BS |
1175 | extern struct nouveau_bitfield nv10_graph_intr[]; |
1176 | extern struct nouveau_bitfield nv10_graph_nstatus[]; | |
6ee73861 BS |
1177 | |
1178 | /* nv20_graph.c */ | |
a0b1de84 | 1179 | extern int nv20_graph_create(struct drm_device *); |
6ee73861 BS |
1180 | |
1181 | /* nv40_graph.c */ | |
39c8d368 | 1182 | extern int nv40_graph_create(struct drm_device *); |
d58086de BS |
1183 | extern void nv40_grctx_init(struct drm_device *, u32 *size); |
1184 | extern void nv40_grctx_fill(struct drm_device *, struct nouveau_gpuobj *); | |
6ee73861 BS |
1185 | |
1186 | /* nv50_graph.c */ | |
2703c21a | 1187 | extern int nv50_graph_create(struct drm_device *); |
6effe393 | 1188 | extern struct nouveau_enum nv50_data_error_names[]; |
7ff5441e | 1189 | extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst); |
d58086de BS |
1190 | extern int nv50_grctx_init(struct drm_device *, u32 *, u32, u32 *, u32 *); |
1191 | extern void nv50_grctx_fill(struct drm_device *, struct nouveau_gpuobj *); | |
6ee73861 | 1192 | |
4b223eef | 1193 | /* nvc0_graph.c */ |
7a45cd19 | 1194 | extern int nvc0_graph_create(struct drm_device *); |
d5a27370 | 1195 | extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst); |
4b223eef | 1196 | |
ab394543 BS |
1197 | /* nve0_graph.c */ |
1198 | extern int nve0_graph_create(struct drm_device *); | |
1199 | ||
bd2e597d | 1200 | /* nv84_crypt.c */ |
6dfdd7a6 | 1201 | extern int nv84_crypt_create(struct drm_device *); |
bd2e597d | 1202 | |
8f27c543 BS |
1203 | /* nv98_crypt.c */ |
1204 | extern int nv98_crypt_create(struct drm_device *dev); | |
1205 | ||
7ff5441e BS |
1206 | /* nva3_copy.c */ |
1207 | extern int nva3_copy_create(struct drm_device *dev); | |
1208 | ||
1209 | /* nvc0_copy.c */ | |
1210 | extern int nvc0_copy_create(struct drm_device *dev, int engine); | |
1211 | ||
323dcac5 BS |
1212 | /* nv31_mpeg.c */ |
1213 | extern int nv31_mpeg_create(struct drm_device *dev); | |
a02ccc7f | 1214 | |
93187450 BS |
1215 | /* nv50_mpeg.c */ |
1216 | extern int nv50_mpeg_create(struct drm_device *dev); | |
c0924326 | 1217 | |
8f27c543 BS |
1218 | /* nv84_bsp.c */ |
1219 | /* nv98_bsp.c */ | |
1220 | extern int nv84_bsp_create(struct drm_device *dev); | |
1221 | ||
1222 | /* nv84_vp.c */ | |
1223 | /* nv98_vp.c */ | |
1224 | extern int nv84_vp_create(struct drm_device *dev); | |
1225 | ||
1226 | /* nv98_ppp.c */ | |
1227 | extern int nv98_ppp_create(struct drm_device *dev); | |
1228 | ||
6ee73861 BS |
1229 | /* nv04_instmem.c */ |
1230 | extern int nv04_instmem_init(struct drm_device *); | |
1231 | extern void nv04_instmem_takedown(struct drm_device *); | |
1232 | extern int nv04_instmem_suspend(struct drm_device *); | |
1233 | extern void nv04_instmem_resume(struct drm_device *); | |
6e32fedc BS |
1234 | extern int nv04_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, |
1235 | u32 size, u32 align); | |
e41115d0 BS |
1236 | extern void nv04_instmem_put(struct nouveau_gpuobj *); |
1237 | extern int nv04_instmem_map(struct nouveau_gpuobj *); | |
1238 | extern void nv04_instmem_unmap(struct nouveau_gpuobj *); | |
f56cb86f | 1239 | extern void nv04_instmem_flush(struct drm_device *); |
6ee73861 BS |
1240 | |
1241 | /* nv50_instmem.c */ | |
1242 | extern int nv50_instmem_init(struct drm_device *); | |
1243 | extern void nv50_instmem_takedown(struct drm_device *); | |
1244 | extern int nv50_instmem_suspend(struct drm_device *); | |
1245 | extern void nv50_instmem_resume(struct drm_device *); | |
6e32fedc BS |
1246 | extern int nv50_instmem_get(struct nouveau_gpuobj *, struct nouveau_channel *, |
1247 | u32 size, u32 align); | |
e41115d0 BS |
1248 | extern void nv50_instmem_put(struct nouveau_gpuobj *); |
1249 | extern int nv50_instmem_map(struct nouveau_gpuobj *); | |
1250 | extern void nv50_instmem_unmap(struct nouveau_gpuobj *); | |
f56cb86f | 1251 | extern void nv50_instmem_flush(struct drm_device *); |
734ee835 | 1252 | extern void nv84_instmem_flush(struct drm_device *); |
6ee73861 | 1253 | |
4b223eef BS |
1254 | /* nvc0_instmem.c */ |
1255 | extern int nvc0_instmem_init(struct drm_device *); | |
1256 | extern void nvc0_instmem_takedown(struct drm_device *); | |
1257 | extern int nvc0_instmem_suspend(struct drm_device *); | |
1258 | extern void nvc0_instmem_resume(struct drm_device *); | |
4b223eef | 1259 | |
6ee73861 BS |
1260 | /* nv04_mc.c */ |
1261 | extern int nv04_mc_init(struct drm_device *); | |
1262 | extern void nv04_mc_takedown(struct drm_device *); | |
1263 | ||
1264 | /* nv40_mc.c */ | |
1265 | extern int nv40_mc_init(struct drm_device *); | |
1266 | extern void nv40_mc_takedown(struct drm_device *); | |
1267 | ||
1268 | /* nv50_mc.c */ | |
1269 | extern int nv50_mc_init(struct drm_device *); | |
1270 | extern void nv50_mc_takedown(struct drm_device *); | |
1271 | ||
1272 | /* nv04_timer.c */ | |
1273 | extern int nv04_timer_init(struct drm_device *); | |
1274 | extern uint64_t nv04_timer_read(struct drm_device *); | |
1275 | extern void nv04_timer_takedown(struct drm_device *); | |
1276 | ||
1277 | extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd, | |
1278 | unsigned long arg); | |
1279 | ||
1280 | /* nv04_dac.c */ | |
8f1a6086 | 1281 | extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *); |
11d6eb2a | 1282 | extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder); |
6ee73861 BS |
1283 | extern int nv04_dac_output_offset(struct drm_encoder *encoder); |
1284 | extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable); | |
8ccfe9e0 | 1285 | extern bool nv04_dac_in_use(struct drm_encoder *encoder); |
6ee73861 BS |
1286 | |
1287 | /* nv04_dfp.c */ | |
8f1a6086 | 1288 | extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1289 | extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent); |
1290 | extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent, | |
1291 | int head, bool dl); | |
1292 | extern void nv04_dfp_disable(struct drm_device *dev, int head); | |
1293 | extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode); | |
1294 | ||
1295 | /* nv04_tv.c */ | |
1296 | extern int nv04_tv_identify(struct drm_device *dev, int i2c_index); | |
8f1a6086 | 1297 | extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1298 | |
1299 | /* nv17_tv.c */ | |
8f1a6086 | 1300 | extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *); |
6ee73861 BS |
1301 | |
1302 | /* nv04_display.c */ | |
c88c2e06 FJ |
1303 | extern int nv04_display_early_init(struct drm_device *); |
1304 | extern void nv04_display_late_takedown(struct drm_device *); | |
6ee73861 BS |
1305 | extern int nv04_display_create(struct drm_device *); |
1306 | extern void nv04_display_destroy(struct drm_device *); | |
2a44e499 BS |
1307 | extern int nv04_display_init(struct drm_device *); |
1308 | extern void nv04_display_fini(struct drm_device *); | |
6ee73861 | 1309 | |
26f6d88b BS |
1310 | /* nvd0_display.c */ |
1311 | extern int nvd0_display_create(struct drm_device *); | |
26f6d88b | 1312 | extern void nvd0_display_destroy(struct drm_device *); |
2a44e499 BS |
1313 | extern int nvd0_display_init(struct drm_device *); |
1314 | extern void nvd0_display_fini(struct drm_device *); | |
3376ee37 BS |
1315 | struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc); |
1316 | void nvd0_display_flip_stop(struct drm_crtc *); | |
1317 | int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *, | |
1318 | struct nouveau_channel *, u32 swap_interval); | |
26f6d88b | 1319 | |
6ee73861 BS |
1320 | /* nv04_crtc.c */ |
1321 | extern int nv04_crtc_create(struct drm_device *, int index); | |
1322 | ||
1323 | /* nouveau_bo.c */ | |
1324 | extern struct ttm_bo_driver nouveau_bo_driver; | |
7375c95b BS |
1325 | extern int nouveau_bo_new(struct drm_device *, int size, int align, |
1326 | uint32_t flags, uint32_t tile_mode, | |
22b33e8e DA |
1327 | uint32_t tile_flags, |
1328 | struct sg_table *sg, | |
1329 | struct nouveau_bo **); | |
6ee73861 BS |
1330 | extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags); |
1331 | extern int nouveau_bo_unpin(struct nouveau_bo *); | |
1332 | extern int nouveau_bo_map(struct nouveau_bo *); | |
1333 | extern void nouveau_bo_unmap(struct nouveau_bo *); | |
78ad0f7b FJ |
1334 | extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type, |
1335 | uint32_t busy); | |
6ee73861 BS |
1336 | extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index); |
1337 | extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val); | |
1338 | extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index); | |
1339 | extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val); | |
332b242f | 1340 | extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *); |
7a45d764 BS |
1341 | extern int nouveau_bo_validate(struct nouveau_bo *, bool interruptible, |
1342 | bool no_wait_reserve, bool no_wait_gpu); | |
6ee73861 | 1343 | |
fd2871af BS |
1344 | extern struct nouveau_vma * |
1345 | nouveau_bo_vma_find(struct nouveau_bo *, struct nouveau_vm *); | |
1346 | extern int nouveau_bo_vma_add(struct nouveau_bo *, struct nouveau_vm *, | |
1347 | struct nouveau_vma *); | |
1348 | extern void nouveau_bo_vma_del(struct nouveau_bo *, struct nouveau_vma *); | |
1349 | ||
6ee73861 | 1350 | /* nouveau_gem.c */ |
f6d4e621 BS |
1351 | extern int nouveau_gem_new(struct drm_device *, int size, int align, |
1352 | uint32_t domain, uint32_t tile_mode, | |
1353 | uint32_t tile_flags, struct nouveau_bo **); | |
6ee73861 BS |
1354 | extern int nouveau_gem_object_new(struct drm_gem_object *); |
1355 | extern void nouveau_gem_object_del(struct drm_gem_object *); | |
639212d0 BS |
1356 | extern int nouveau_gem_object_open(struct drm_gem_object *, struct drm_file *); |
1357 | extern void nouveau_gem_object_close(struct drm_gem_object *, | |
1358 | struct drm_file *); | |
6ee73861 BS |
1359 | extern int nouveau_gem_ioctl_new(struct drm_device *, void *, |
1360 | struct drm_file *); | |
1361 | extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *, | |
1362 | struct drm_file *); | |
6ee73861 BS |
1363 | extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *, |
1364 | struct drm_file *); | |
1365 | extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *, | |
1366 | struct drm_file *); | |
1367 | extern int nouveau_gem_ioctl_info(struct drm_device *, void *, | |
1368 | struct drm_file *); | |
1369 | ||
22b33e8e DA |
1370 | extern struct dma_buf *nouveau_gem_prime_export(struct drm_device *dev, |
1371 | struct drm_gem_object *obj, int flags); | |
1372 | extern struct drm_gem_object *nouveau_gem_prime_import(struct drm_device *dev, | |
1373 | struct dma_buf *dma_buf); | |
1374 | ||
042206c0 | 1375 | /* nouveau_display.c */ |
27d5030a BS |
1376 | int nouveau_display_create(struct drm_device *dev); |
1377 | void nouveau_display_destroy(struct drm_device *dev); | |
f62b27db BS |
1378 | int nouveau_display_init(struct drm_device *dev); |
1379 | void nouveau_display_fini(struct drm_device *dev); | |
042206c0 FJ |
1380 | int nouveau_vblank_enable(struct drm_device *dev, int crtc); |
1381 | void nouveau_vblank_disable(struct drm_device *dev, int crtc); | |
332b242f FJ |
1382 | int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
1383 | struct drm_pending_vblank_event *event); | |
1384 | int nouveau_finish_page_flip(struct nouveau_channel *, | |
1385 | struct nouveau_page_flip_state *); | |
33dbc27f BS |
1386 | int nouveau_display_dumb_create(struct drm_file *, struct drm_device *, |
1387 | struct drm_mode_create_dumb *args); | |
1388 | int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *, | |
1389 | uint32_t handle, uint64_t *offset); | |
1390 | int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *, | |
1391 | uint32_t handle); | |
042206c0 | 1392 | |
ee2e0131 | 1393 | /* nv10_gpio.c */ |
a0b25635 BS |
1394 | int nv10_gpio_init(struct drm_device *dev); |
1395 | void nv10_gpio_fini(struct drm_device *dev); | |
1396 | int nv10_gpio_drive(struct drm_device *dev, int line, int dir, int out); | |
1397 | int nv10_gpio_sense(struct drm_device *dev, int line); | |
1398 | void nv10_gpio_irq_enable(struct drm_device *, int line, bool on); | |
6ee73861 | 1399 | |
45284162 | 1400 | /* nv50_gpio.c */ |
ee2e0131 | 1401 | int nv50_gpio_init(struct drm_device *dev); |
2cbd4c81 | 1402 | void nv50_gpio_fini(struct drm_device *dev); |
a0b25635 BS |
1403 | int nv50_gpio_drive(struct drm_device *dev, int line, int dir, int out); |
1404 | int nv50_gpio_sense(struct drm_device *dev, int line); | |
1405 | void nv50_gpio_irq_enable(struct drm_device *, int line, bool on); | |
1406 | int nvd0_gpio_drive(struct drm_device *dev, int line, int dir, int out); | |
1407 | int nvd0_gpio_sense(struct drm_device *dev, int line); | |
1408 | ||
1409 | /* nv50_calc.c */ | |
e9ebb68b BS |
1410 | int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk, |
1411 | int *N1, int *M1, int *N2, int *M2, int *P); | |
52eba8dd BS |
1412 | int nva3_calc_pll(struct drm_device *, struct pll_lims *, |
1413 | int clk, int *N, int *fN, int *M, int *P); | |
e9ebb68b | 1414 | |
6ee73861 BS |
1415 | #ifndef ioread32_native |
1416 | #ifdef __BIG_ENDIAN | |
1417 | #define ioread16_native ioread16be | |
1418 | #define iowrite16_native iowrite16be | |
1419 | #define ioread32_native ioread32be | |
1420 | #define iowrite32_native iowrite32be | |
1421 | #else /* def __BIG_ENDIAN */ | |
1422 | #define ioread16_native ioread16 | |
1423 | #define iowrite16_native iowrite16 | |
1424 | #define ioread32_native ioread32 | |
1425 | #define iowrite32_native iowrite32 | |
1426 | #endif /* def __BIG_ENDIAN else */ | |
1427 | #endif /* !ioread32_native */ | |
1428 | ||
1429 | /* channel control reg access */ | |
1430 | static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg) | |
1431 | { | |
1432 | return ioread32_native(chan->user + reg); | |
1433 | } | |
1434 | ||
1435 | static inline void nvchan_wr32(struct nouveau_channel *chan, | |
1436 | unsigned reg, u32 val) | |
1437 | { | |
1438 | iowrite32_native(val, chan->user + reg); | |
1439 | } | |
1440 | ||
1441 | /* register access */ | |
1442 | static inline u32 nv_rd32(struct drm_device *dev, unsigned reg) | |
1443 | { | |
1444 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1445 | return ioread32_native(dev_priv->mmio + reg); | |
1446 | } | |
1447 | ||
1448 | static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val) | |
1449 | { | |
1450 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1451 | iowrite32_native(val, dev_priv->mmio + reg); | |
1452 | } | |
1453 | ||
2a7fdb2b | 1454 | static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val) |
49eed80a BS |
1455 | { |
1456 | u32 tmp = nv_rd32(dev, reg); | |
2a7fdb2b BS |
1457 | nv_wr32(dev, reg, (tmp & ~mask) | val); |
1458 | return tmp; | |
49eed80a BS |
1459 | } |
1460 | ||
6ee73861 BS |
1461 | static inline u8 nv_rd08(struct drm_device *dev, unsigned reg) |
1462 | { | |
1463 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1464 | return ioread8(dev_priv->mmio + reg); | |
1465 | } | |
1466 | ||
1467 | static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val) | |
1468 | { | |
1469 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1470 | iowrite8(val, dev_priv->mmio + reg); | |
1471 | } | |
1472 | ||
4b5c152a | 1473 | #define nv_wait(dev, reg, mask, val) \ |
12fb9525 BS |
1474 | nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val)) |
1475 | #define nv_wait_ne(dev, reg, mask, val) \ | |
1476 | nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val)) | |
78e2933d BS |
1477 | #define nv_wait_cb(dev, func, data) \ |
1478 | nouveau_wait_cb(dev, 2000000000ULL, (func), (data)) | |
6ee73861 BS |
1479 | |
1480 | /* PRAMIN access */ | |
1481 | static inline u32 nv_ri32(struct drm_device *dev, unsigned offset) | |
1482 | { | |
1483 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1484 | return ioread32_native(dev_priv->ramin + offset); | |
1485 | } | |
1486 | ||
1487 | static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val) | |
1488 | { | |
1489 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1490 | iowrite32_native(val, dev_priv->ramin + offset); | |
1491 | } | |
1492 | ||
1493 | /* object access */ | |
b3beb167 BS |
1494 | extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset); |
1495 | extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val); | |
6ee73861 BS |
1496 | |
1497 | /* | |
1498 | * Logging | |
1499 | * Argument d is (struct drm_device *). | |
1500 | */ | |
1501 | #define NV_PRINTK(level, d, fmt, arg...) \ | |
1502 | printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \ | |
1503 | pci_name(d->pdev), ##arg) | |
1504 | #ifndef NV_DEBUG_NOTRACE | |
1505 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1506 | if (drm_debug & DRM_UT_DRIVER) { \ |
1507 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ | |
1508 | __LINE__, ##arg); \ | |
1509 | } \ | |
1510 | } while (0) | |
1511 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1512 | if (drm_debug & DRM_UT_KMS) { \ | |
6ee73861 BS |
1513 | NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \ |
1514 | __LINE__, ##arg); \ | |
1515 | } \ | |
1516 | } while (0) | |
1517 | #else | |
1518 | #define NV_DEBUG(d, fmt, arg...) do { \ | |
ef2bb506 MM |
1519 | if (drm_debug & DRM_UT_DRIVER) \ |
1520 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ | |
1521 | } while (0) | |
1522 | #define NV_DEBUG_KMS(d, fmt, arg...) do { \ | |
1523 | if (drm_debug & DRM_UT_KMS) \ | |
6ee73861 BS |
1524 | NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \ |
1525 | } while (0) | |
1526 | #endif | |
1527 | #define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg) | |
1528 | #define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1529 | #define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg) | |
1530 | #define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg) | |
1531 | #define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg) | |
6b5a81a2 BS |
1532 | #define NV_WARNONCE(d, fmt, arg...) do { \ |
1533 | static int _warned = 0; \ | |
1534 | if (!_warned) { \ | |
1535 | NV_WARN(d, fmt, ##arg); \ | |
1536 | _warned = 1; \ | |
1537 | } \ | |
1538 | } while(0) | |
6ee73861 BS |
1539 | |
1540 | /* nouveau_reg_debug bitmask */ | |
1541 | enum { | |
1542 | NOUVEAU_REG_DEBUG_MC = 0x1, | |
1543 | NOUVEAU_REG_DEBUG_VIDEO = 0x2, | |
1544 | NOUVEAU_REG_DEBUG_FB = 0x4, | |
1545 | NOUVEAU_REG_DEBUG_EXTDEV = 0x8, | |
1546 | NOUVEAU_REG_DEBUG_CRTC = 0x10, | |
1547 | NOUVEAU_REG_DEBUG_RAMDAC = 0x20, | |
1548 | NOUVEAU_REG_DEBUG_VGACRTC = 0x40, | |
1549 | NOUVEAU_REG_DEBUG_RMVIO = 0x80, | |
1550 | NOUVEAU_REG_DEBUG_VGAATTR = 0x100, | |
1551 | NOUVEAU_REG_DEBUG_EVO = 0x200, | |
43720133 | 1552 | NOUVEAU_REG_DEBUG_AUXCH = 0x400 |
6ee73861 BS |
1553 | }; |
1554 | ||
1555 | #define NV_REG_DEBUG(type, dev, fmt, arg...) do { \ | |
1556 | if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \ | |
1557 | NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \ | |
1558 | } while (0) | |
1559 | ||
1560 | static inline bool | |
1561 | nv_two_heads(struct drm_device *dev) | |
1562 | { | |
1563 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1564 | const int impl = dev->pci_device & 0x0ff0; | |
1565 | ||
1566 | if (dev_priv->card_type >= NV_10 && impl != 0x0100 && | |
1567 | impl != 0x0150 && impl != 0x01a0 && impl != 0x0200) | |
1568 | return true; | |
1569 | ||
1570 | return false; | |
1571 | } | |
1572 | ||
1573 | static inline bool | |
1574 | nv_gf4_disp_arch(struct drm_device *dev) | |
1575 | { | |
1576 | return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110; | |
1577 | } | |
1578 | ||
1579 | static inline bool | |
1580 | nv_two_reg_pll(struct drm_device *dev) | |
1581 | { | |
1582 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1583 | const int impl = dev->pci_device & 0x0ff0; | |
1584 | ||
1585 | if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40) | |
1586 | return true; | |
1587 | return false; | |
1588 | } | |
1589 | ||
acae116c FJ |
1590 | static inline bool |
1591 | nv_match_device(struct drm_device *dev, unsigned device, | |
1592 | unsigned sub_vendor, unsigned sub_device) | |
1593 | { | |
1594 | return dev->pdev->device == device && | |
1595 | dev->pdev->subsystem_vendor == sub_vendor && | |
1596 | dev->pdev->subsystem_device == sub_device; | |
1597 | } | |
1598 | ||
6dfdd7a6 BS |
1599 | static inline void * |
1600 | nv_engine(struct drm_device *dev, int engine) | |
1601 | { | |
1602 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1603 | return (void *)dev_priv->eng[engine]; | |
1604 | } | |
1605 | ||
c693931d BS |
1606 | /* returns 1 if device is one of the nv4x using the 0x4497 object class, |
1607 | * helpful to determine a number of other hardware features | |
1608 | */ | |
1609 | static inline int | |
1610 | nv44_graph_class(struct drm_device *dev) | |
1611 | { | |
1612 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1613 | ||
1614 | if ((dev_priv->chipset & 0xf0) == 0x60) | |
1615 | return 1; | |
1616 | ||
1617 | return !(0x0baf & (1 << (dev_priv->chipset & 0x0f))); | |
1618 | } | |
1619 | ||
7f4a195f | 1620 | /* memory type/access flags, do not match hardware values */ |
a11c3198 BS |
1621 | #define NV_MEM_ACCESS_RO 1 |
1622 | #define NV_MEM_ACCESS_WO 2 | |
7f4a195f | 1623 | #define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO) |
a11c3198 BS |
1624 | #define NV_MEM_ACCESS_SYS 4 |
1625 | #define NV_MEM_ACCESS_VM 8 | |
990449c7 | 1626 | #define NV_MEM_ACCESS_NOSNOOP 16 |
7f4a195f BS |
1627 | |
1628 | #define NV_MEM_TARGET_VRAM 0 | |
1629 | #define NV_MEM_TARGET_PCI 1 | |
1630 | #define NV_MEM_TARGET_PCI_NOSNOOP 2 | |
1631 | #define NV_MEM_TARGET_VM 3 | |
1632 | #define NV_MEM_TARGET_GART 4 | |
1633 | ||
1634 | #define NV_MEM_TYPE_VM 0x7f | |
1635 | #define NV_MEM_COMP_VM 0x03 | |
1636 | ||
b5b2e598 BS |
1637 | /* FIFO methods */ |
1638 | #define NV01_SUBCHAN_OBJECT 0x00000000 | |
1639 | #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010 | |
1640 | #define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014 | |
1641 | #define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018 | |
1642 | #define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c | |
1643 | #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001 | |
1644 | #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002 | |
1645 | #define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004 | |
5e120f6e | 1646 | #define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000 |
b5b2e598 BS |
1647 | #define NV84_SUBCHAN_NOTIFY_INTR 0x00000020 |
1648 | #define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024 | |
1649 | #define NV10_SUBCHAN_REF_CNT 0x00000050 | |
d5316e25 | 1650 | #define NVSW_SUBCHAN_PAGE_FLIP 0x00000054 |
b5b2e598 BS |
1651 | #define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060 |
1652 | #define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064 | |
1653 | #define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068 | |
1654 | #define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c | |
1655 | #define NV40_SUBCHAN_YIELD 0x00000080 | |
1656 | ||
7f4a195f | 1657 | /* NV_SW object class */ |
f03a314b | 1658 | #define NV_SW 0x0000506e |
f03a314b FJ |
1659 | #define NV_SW_DMA_VBLSEM 0x0000018c |
1660 | #define NV_SW_VBLSEM_OFFSET 0x00000400 | |
1661 | #define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404 | |
1662 | #define NV_SW_VBLSEM_RELEASE 0x00000408 | |
332b242f | 1663 | #define NV_SW_PAGE_FLIP 0x00000500 |
6ee73861 BS |
1664 | |
1665 | #endif /* __NOUVEAU_DRV_H__ */ |