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drm/nouveau: port all engines to new engine module format
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
f887c425 29#define DRIVER_EMAIL "nouveau@lists.freedesktop.org"
6ee73861
BS		 30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
f887c425 33#define DRIVER_DATE "20120316"
6ee73861 34
f887c425 35#define DRIVER_MAJOR 1
6ee73861 36#define DRIVER_MINOR 0
f887c425 37#define DRIVER_PATCHLEVEL 0
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
861d2107 48#define XXX_THIS_IS_A_HACK
3863c9bc 49#include <subdev/vm.h>
861d2107 50#include <subdev/fb.h>
3863c9bc 51#include <core/gpuobj.h>
861d2107
BS		 52
53enum blah {
54 NV_MEM_TYPE_UNKNOWN = 0,
55 NV_MEM_TYPE_STOLEN,
56 NV_MEM_TYPE_SGRAM,
57 NV_MEM_TYPE_SDRAM,
58 NV_MEM_TYPE_DDR1,
59 NV_MEM_TYPE_DDR2,
60 NV_MEM_TYPE_DDR3,
61 NV_MEM_TYPE_GDDR2,
62 NV_MEM_TYPE_GDDR3,
63 NV_MEM_TYPE_GDDR4,
64 NV_MEM_TYPE_GDDR5
65};
66
6ee73861
BS		 67#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
68
94580299 69#include <nouveau_drm.h>
6ee73861 70#include "nouveau_reg.h"
02a841d4 71#include <nouveau_bios.h>
f869ef88 72
054b93e4 73struct nouveau_grctx;
d5f42394 74struct nouveau_mem;
6ee73861 75
70790f4f
BS		 76#include <subdev/bios/pll.h>
77#include "nouveau_compat.h"
78
3863c9bc 79#define nouveau_gpuobj_new(d,c,s,a,f,o) \
ebb945a9 80 _nouveau_gpuobj_new((d), NULL, (s), (a), (f), (o))
3863c9bc
BS		 81
82#define nouveau_vm_new(d,o,l,m,v) \
83 _nouveau_vm_new((d), (o), (l), (m), (v))
84
85#define nv50_vm_flush_engine(d,e) \
86 _nv50_vm_flush_engine((d), (e))
87
6ee73861
BS		 88#define MAX_NUM_DCB_ENTRIES 16
89
5132f377 90#define NOUVEAU_MAX_CHANNEL_NR 4096
6ee73861 91
8be21a64 92#include "nouveau_bo.h"
66f24723 93#include "nouveau_gem.h"
6ee73861 94
6ee73861
BS		 95enum nouveau_flags {
96 NV_NFORCE = 0x10000000,
97 NV_NFORCE2 = 0x20000000
98};
99
332b242f
FJ		 100struct nouveau_page_flip_state {
101 struct list_head head;
102 struct drm_pending_vblank_event *event;
103 int crtc, bpp, pitch, x, y;
104 uint64_t offset;
105};
106
e419cf09
FJ		 107enum nouveau_channel_mutex_class {
108 NOUVEAU_UCHANNEL_MUTEX,
109 NOUVEAU_KCHANNEL_MUTEX
110};
111
c88c2e06 112struct nouveau_display_engine {
ef8389a8 113 void *priv;
c88c2e06
FJ		 114 int (*early_init)(struct drm_device *);
115 void (*late_takedown)(struct drm_device *);
116 int (*create)(struct drm_device *);
c88c2e06 117 void (*destroy)(struct drm_device *);
2a44e499
BS		 118 int (*init)(struct drm_device *);
119 void (*fini)(struct drm_device *);
b29caa58 120
de691855
BS		 121 struct drm_property *dithering_mode;
122 struct drm_property *dithering_depth;
b29caa58
BS		 123 struct drm_property *underscan_property;
124 struct drm_property *underscan_hborder_property;
125 struct drm_property *underscan_vborder_property;
df26bc9c
CB		 126 /* not really hue and saturation: */
127 struct drm_property *vibrant_hue_property;
128 struct drm_property *color_vibrance_property;
c88c2e06
FJ		 129};
130
330c5988 131struct nouveau_pm_voltage_level {
c3450239
BS		 132 u32 voltage; /* microvolts */
133 u8 vid;
330c5988
BS		 134};
135
136struct nouveau_pm_voltage {
137 bool supported;
03ce8d9e 138 u8 version;
330c5988
BS		 139 u8 vid_mask;
140
141 struct nouveau_pm_voltage_level *level;
142 int nr_level;
143};
144
c7c039fd
RS		 145/* Exclusive upper limits */
146#define NV_MEM_CL_DDR2_MAX 8
147#define NV_MEM_WR_DDR2_MAX 9
148#define NV_MEM_CL_DDR3_MAX 17
149#define NV_MEM_WR_DDR3_MAX 17
150#define NV_MEM_CL_GDDR3_MAX 16
151#define NV_MEM_WR_GDDR3_MAX 18
152#define NV_MEM_CL_GDDR5_MAX 21
153#define NV_MEM_WR_GDDR5_MAX 20
154
e614b2e7
MP		 155struct nouveau_pm_memtiming {
156 int id;
c7c039fd
RS		 157
158 u32 reg[9];
159 u32 mr[4];
160
bfb31465
RS		 161 u8 tCWL;
162
c7c039fd
RS		 163 u8 odt;
164 u8 drive_strength;
9a782488
RS		 165};
166
ddb20055 167struct nouveau_pm_tbl_header {
9a782488
RS		 168 u8 version;
169 u8 header_len;
170 u8 entry_cnt;
171 u8 entry_len;
172};
173
ddb20055 174struct nouveau_pm_tbl_entry {
2228c6fe 175 u8 tWR;
bfb31465 176 u8 tWTR;
2228c6fe 177 u8 tCL;
bfb31465 178 u8 tRC;
9a782488 179 u8 empty_4;
bfb31465 180 u8 tRFC; /* Byte 5 */
9a782488 181 u8 empty_6;
bfb31465 182 u8 tRAS; /* Byte 7 */
9a782488 183 u8 empty_8;
bfb31465
RS		 184 u8 tRP; /* Byte 9 */
185 u8 tRCDRD;
186 u8 tRCDWR;
187 u8 tRRD;
188 u8 tUNK_13;
189 u8 RAM_FT1; /* 14, a bitmask of random RAM features */
190 u8 empty_15;
191 u8 tUNK_16;
192 u8 empty_17;
193 u8 tUNK_18;
194 u8 tCWL;
195 u8 tUNK_20, tUNK_21;
9a782488
RS		 196};
197
8d7bb400
BS		 198struct nouveau_pm_profile;
199struct nouveau_pm_profile_func {
25c53c10
BS		 200 void (*destroy)(struct nouveau_pm_profile *);
201 void (*init)(struct nouveau_pm_profile *);
202 void (*fini)(struct nouveau_pm_profile *);
8d7bb400
BS		 203 struct nouveau_pm_level *(*select)(struct nouveau_pm_profile *);
204};
205
206struct nouveau_pm_profile {
207 const struct nouveau_pm_profile_func *func;
208 struct list_head head;
209 char name[8];
210};
211
330c5988
BS		 212#define NOUVEAU_PM_MAX_LEVEL 8
213struct nouveau_pm_level {
8d7bb400 214 struct nouveau_pm_profile profile;
330c5988
BS		 215 struct device_attribute dev_attr;
216 char name[32];
217 int id;
218
8d7bb400 219 struct nouveau_pm_memtiming timing;
330c5988 220 u32 memory;
085028ce 221 u16 memscript;
085028ce
BS		 222
223 u32 core;
330c5988 224 u32 shader;
9698b9a6
BS		 225 u32 rop;
226 u32 copy;
227 u32 daemon;
4fd2847e 228 u32 vdec;
f3fbaf34 229 u32 dom6;
9698b9a6
BS		 230 u32 unka0; /* nva3:nvc0 */
231 u32 hub01; /* nvc0- */
232 u32 hub06; /* nvc0- */
233 u32 hub07; /* nvc0- */
330c5988 234
3b5565dd
BS		 235 u32 volt_min; /* microvolts */
236 u32 volt_max;
c3450239 237 u8 fanspeed;
330c5988
BS		 238};
239
34e9d85a
MP		 240struct nouveau_pm_temp_sensor_constants {
241 u16 offset_constant;
242 s16 offset_mult;
40ce4279
EV		 243 s16 offset_div;
244 s16 slope_mult;
245 s16 slope_div;
34e9d85a
MP		 246};
247
248struct nouveau_pm_threshold_temp {
249 s16 critical;
250 s16 down_clock;
251 s16 fan_boost;
252};
253
11b7d895 254struct nouveau_pm_fan {
bc6389e4 255 u32 percent;
11b7d895
MP		 256 u32 min_duty;
257 u32 max_duty;
3f8e11e4 258 u32 pwm_freq;
b1aa5531 259 u32 pwm_divisor;
11b7d895
MP		 260};
261
330c5988
BS		 262struct nouveau_pm_engine {
263 struct nouveau_pm_voltage voltage;
264 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
265 int nr_perflvl;
34e9d85a
MP		 266 struct nouveau_pm_temp_sensor_constants sensor_constants;
267 struct nouveau_pm_threshold_temp threshold_temp;
11b7d895 268 struct nouveau_pm_fan fan;
330c5988 269
8d7bb400
BS		 270 struct nouveau_pm_profile *profile_ac;
271 struct nouveau_pm_profile *profile_dc;
25c53c10 272 struct nouveau_pm_profile *profile;
8d7bb400
BS		 273 struct list_head profiles;
274
330c5988
BS		 275 struct nouveau_pm_level boot;
276 struct nouveau_pm_level *cur;
277
8155cac4 278 struct device *hwmon;
6032649d 279 struct notifier_block acpi_nb;
8155cac4 280
77e7da68
BS		 281 int (*clocks_get)(struct drm_device *, struct nouveau_pm_level *);
282 void *(*clocks_pre)(struct drm_device *, struct nouveau_pm_level *);
dd1da8de 283 int (*clocks_set)(struct drm_device *, void *);
77e7da68 284
330c5988
BS		 285 int (*voltage_get)(struct drm_device *);
286 int (*voltage_set)(struct drm_device *, int voltage);
675aac03
BS		 287 int (*pwm_get)(struct drm_device *, int line, u32*, u32*);
288 int (*pwm_set)(struct drm_device *, int line, u32, u32);
8155cac4 289 int (*temp_get)(struct drm_device *);
330c5988
BS		 290};
291
6ee73861 292struct nouveau_engine {
c88c2e06 293 struct nouveau_display_engine display;
330c5988 294 struct nouveau_pm_engine pm;
6ee73861
BS		 295};
296
6ee73861 297enum nouveau_card_type {
2f5394c3 298 NV_04 = 0x04,
6ee73861
BS		 299 NV_10 = 0x10,
300 NV_20 = 0x20,
301 NV_30 = 0x30,
302 NV_40 = 0x40,
303 NV_50 = 0x50,
4b223eef 304 NV_C0 = 0xc0,
2f5394c3 305 NV_D0 = 0xd0,
68455a43 306 NV_E0 = 0xe0,
6ee73861
BS		 307};
308
ebb945a9
BS		 309struct nouveau_channel;
310
6ee73861
BS		 311struct drm_nouveau_private {
312 struct drm_device *dev;
aba99a84 313 bool noaccel;
6ee73861 314
94580299
BS		 315 void *newpriv;
316
6ee73861
BS		 317 /* the card type, takes NV_* as values */
318 enum nouveau_card_type card_type;
319 /* exact chipset, derived from NV_PMC_BOOT_0 */
320 int chipset;
321 int flags;
f2cbe46f 322 u32 crystal;
6ee73861 323
ac8fb975
BS		 324 struct nouveau_bo *vga_ram;
325
35fa2f2a 326 /* interrupt handling */
8f8a5448 327 void (*irq_handler[32])(struct drm_device *);
35fa2f2a 328 bool msi_enabled;
ab838338 329
6ee73861 330 struct nouveau_engine engine;
6ee73861 331
ff9e5279
MM		 332 /* For PFIFO and PGRAPH. */
333 spinlock_t context_switch_lock;
334
6ee73861 335 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31 336 struct nouveau_ramht *ramht;
e05c5a31 337
a76fb4e8
BS		 338 uint64_t fb_available_size;
339 uint64_t fb_mappable_pages;
a76fb4e8
BS		 340 int fb_mtrr;
341
04a39c57 342 struct nvbios vbios;
b4c26818 343 u8 *mxms;
486a45c2 344 struct list_head i2c_ports;
6ee73861 345
6ee73861 346 struct backlight_device *backlight;
6ee73861
BS		 347};
348
2730723b
FJ		 349static inline struct drm_nouveau_private *
350nouveau_private(struct drm_device *dev)
351{
352 return dev->dev_private;
353}
354
6ee73861 355/* nouveau_drv.c */
03bc9675 356extern int nouveau_modeset;
6ee73861
BS		 357extern int nouveau_duallink;
358extern int nouveau_uscript_lvds;
359extern int nouveau_uscript_tmds;
360extern int nouveau_vram_pushbuf;
361extern int nouveau_vram_notify;
7ad2d31c 362extern char *nouveau_vram_type;
6ee73861 363extern int nouveau_fbpercrtc;
f4053509 364extern int nouveau_tv_disable;
6ee73861
BS		 365extern char *nouveau_tv_norm;
366extern int nouveau_reg_debug;
a1470890 367extern int nouveau_ignorelid;
a32ed69d 368extern int nouveau_noaccel;
0cba1b76 369extern int nouveau_force_post;
da647d5b 370extern int nouveau_override_conntype;
6f876986
BS		 371extern char *nouveau_perflvl;
372extern int nouveau_perflvl_wr;
35fa2f2a 373extern int nouveau_msi;
0411de85 374extern int nouveau_ctxfw;
b4c26818 375extern int nouveau_mxmdcb;
6ee73861 376
6a9ee8af
DA		 377extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
378extern int nouveau_pci_resume(struct pci_dev *pdev);
379
6ee73861 380/* nouveau_state.c */
6ee73861
BS		 381extern int nouveau_load(struct drm_device *, unsigned long flags);
382extern int nouveau_firstopen(struct drm_device *);
383extern void nouveau_lastclose(struct drm_device *);
384extern int nouveau_unload(struct drm_device *);
6ee73861
BS		 385extern bool nouveau_wait_for_idle(struct drm_device *);
386extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 387
388/* nouveau_mem.c */
fbd2895e
BS		 389extern int nouveau_mem_vram_init(struct drm_device *);
390extern void nouveau_mem_vram_fini(struct drm_device *);
391extern int nouveau_mem_gart_init(struct drm_device *);
392extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 393extern void nouveau_mem_close(struct drm_device *);
60d2a88a 394extern bool nouveau_mem_flags_valid(struct drm_device *, u32 tile_flags);
085028ce
BS		 395extern int nouveau_mem_timing_calc(struct drm_device *, u32 freq,
396 struct nouveau_pm_memtiming *);
fd99fd61
BS		 397extern void nouveau_mem_timing_read(struct drm_device *,
398 struct nouveau_pm_memtiming *);
c70c41e8 399extern int nouveau_mem_vbios_type(struct drm_device *);
ebb945a9
BS		 400extern struct nouveau_tile_reg *nv10_mem_set_tiling(
401 struct drm_device *dev, uint32_t addr, uint32_t size,
402 uint32_t pitch, uint32_t flags);
403extern void nv10_mem_put_tile_region(struct drm_device *dev,
404 struct nouveau_tile_reg *tile,
405 struct nouveau_fence *fence);
406
d1b167e1 407extern int nouveau_channel_idle(struct nouveau_channel *chan);
6ee73861 408
ce22af03 409/* nouveau_gpuobj.c */
3863c9bc
BS		 410int nouveau_gpuobj_map_vm(struct nouveau_gpuobj *gpuobj, struct nouveau_vm *vm,
411 u32 flags, struct nouveau_vma *vma);
18c9b959
BS		 412void nouveau_gpuobj_unmap(struct nouveau_vma *vma);
413
6ee73861 414/* nouveau_irq.c */
35fa2f2a
BS		 415extern int nouveau_irq_init(struct drm_device *);
416extern void nouveau_irq_fini(struct drm_device *);
6ee73861 417extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
8f8a5448
BS		 418extern void nouveau_irq_register(struct drm_device *, int status_bit,
419 void (*)(struct drm_device *));
420extern void nouveau_irq_unregister(struct drm_device *, int status_bit);
6ee73861
BS		 421extern void nouveau_irq_preinstall(struct drm_device *);
422extern int nouveau_irq_postinstall(struct drm_device *);
423extern void nouveau_irq_uninstall(struct drm_device *);
424
6ee73861 425/* nouveau_acpi.c */
afeb3e11 426#define ROM_BIOS_PAGE 4096
2f41a7f1 427#if defined(CONFIG_ACPI)
6a9ee8af
DA		 428void nouveau_register_dsm_handler(void);
429void nouveau_unregister_dsm_handler(void);
d099230c 430void nouveau_switcheroo_optimus_dsm(void);
afeb3e11
DA		 431int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
432bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 433int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 434#else
435static inline void nouveau_register_dsm_handler(void) {}
436static inline void nouveau_unregister_dsm_handler(void) {}
d099230c 437static inline void nouveau_switcheroo_optimus_dsm(void) {}
afeb3e11
DA		 438static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
439static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 440static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 441#endif
6ee73861
BS		 442
443/* nouveau_backlight.c */
444#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
10b461e4
BS		 445extern int nouveau_backlight_init(struct drm_device *);
446extern void nouveau_backlight_exit(struct drm_device *);
6ee73861 447#else
10b461e4 448static inline int nouveau_backlight_init(struct drm_device *dev)
6ee73861
BS		 449{
450 return 0;
451}
452
10b461e4 453static inline void nouveau_backlight_exit(struct drm_device *dev) { }
6ee73861
BS		 454#endif
455
456/* nouveau_bios.c */
457extern int nouveau_bios_init(struct drm_device *);
458extern void nouveau_bios_takedown(struct drm_device *dev);
459extern int nouveau_run_vbios_init(struct drm_device *);
6ee73861
BS		 460extern struct dcb_connector_table_entry *
461nouveau_bios_connector_entry(struct drm_device *, int index);
02e4f587 462extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
cb75d97e 463 struct dcb_output *, int crtc);
6ee73861
BS		 464extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
465extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
466extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
467 bool *dl, bool *if_is_24bit);
cb75d97e 468extern int run_tmds_table(struct drm_device *, struct dcb_output *,
6ee73861 469 int head, int pxclk);
cb75d97e 470extern int call_lvds_script(struct drm_device *, struct dcb_output *, int head,
6ee73861 471 enum LVDS_script, int pxclk);
cb75d97e 472bool bios_encoder_match(struct dcb_output *, u32 hash);
6ee73861 473
b4c26818
BS		 474/* nouveau_mxm.c */
475int nouveau_mxm_init(struct drm_device *dev);
476void nouveau_mxm_fini(struct drm_device *dev);
477
6ee73861
BS		 478/* nouveau_ttm.c */
479int nouveau_ttm_global_init(struct drm_nouveau_private *);
480void nouveau_ttm_global_release(struct drm_nouveau_private *);
481int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
482
25575b41
BS		 483/* nouveau_hdmi.c */
484void nouveau_hdmi_mode_set(struct drm_encoder *, struct drm_display_mode *);
485
6ee73861 486extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
ebb945a9 487 unsigned long arg);
6ee73861 488
26f6d88b
BS		 489/* nvd0_display.c */
490extern int nvd0_display_create(struct drm_device *);
26f6d88b 491extern void nvd0_display_destroy(struct drm_device *);
2a44e499
BS		 492extern int nvd0_display_init(struct drm_device *);
493extern void nvd0_display_fini(struct drm_device *);
3376ee37
BS		 494struct nouveau_bo *nvd0_display_crtc_sema(struct drm_device *, int crtc);
495void nvd0_display_flip_stop(struct drm_crtc *);
496int nvd0_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
497 struct nouveau_channel *, u32 swap_interval);
26f6d88b 498
22b33e8e 499
042206c0 500/* nouveau_display.c */
27d5030a
BS		 501int nouveau_display_create(struct drm_device *dev);
502void nouveau_display_destroy(struct drm_device *dev);
f62b27db
BS		 503int nouveau_display_init(struct drm_device *dev);
504void nouveau_display_fini(struct drm_device *dev);
042206c0
FJ		 505int nouveau_vblank_enable(struct drm_device *dev, int crtc);
506void nouveau_vblank_disable(struct drm_device *dev, int crtc);
332b242f
FJ		 507int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
508 struct drm_pending_vblank_event *event);
509int nouveau_finish_page_flip(struct nouveau_channel *,
510 struct nouveau_page_flip_state *);
33dbc27f
BS		 511int nouveau_display_dumb_create(struct drm_file *, struct drm_device *,
512 struct drm_mode_create_dumb *args);
513int nouveau_display_dumb_map_offset(struct drm_file *, struct drm_device *,
514 uint32_t handle, uint64_t *offset);
515int nouveau_display_dumb_destroy(struct drm_file *, struct drm_device *,
516 uint32_t handle);
042206c0 517
6ee73861
BS		 518#ifndef ioread32_native
519#ifdef __BIG_ENDIAN
520#define ioread16_native ioread16be
521#define iowrite16_native iowrite16be
522#define ioread32_native ioread32be
523#define iowrite32_native iowrite32be
524#else /* def __BIG_ENDIAN */
525#define ioread16_native ioread16
526#define iowrite16_native iowrite16
527#define ioread32_native ioread32
528#define iowrite32_native iowrite32
529#endif /* def __BIG_ENDIAN else */
530#endif /* !ioread32_native */
531
6ee73861 532/* register access */
586c55f6
BS		 533#define nv_rd08 _nv_rd08
534#define nv_wr08 _nv_wr08
535#define nv_rd32 _nv_rd32
536#define nv_wr32 _nv_wr32
537#define nv_mask _nv_mask
6ee73861 538
4b5c152a 539#define nv_wait(dev, reg, mask, val) \
12fb9525
BS		 540 nouveau_wait_eq(dev, 2000000000ULL, (reg), (mask), (val))
541#define nv_wait_ne(dev, reg, mask, val) \
542 nouveau_wait_ne(dev, 2000000000ULL, (reg), (mask), (val))
78e2933d
BS		 543#define nv_wait_cb(dev, func, data) \
544 nouveau_wait_cb(dev, 2000000000ULL, (func), (data))
6ee73861 545
6ee73861
BS		 546/*
547 * Logging
548 * Argument d is (struct drm_device *).
549 */
550#define NV_PRINTK(level, d, fmt, arg...) \
551 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
552 pci_name(d->pdev), ##arg)
553#ifndef NV_DEBUG_NOTRACE
554#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 555 if (drm_debug & DRM_UT_DRIVER) { \
556 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
557 __LINE__, ##arg); \
558 } \
559} while (0)
560#define NV_DEBUG_KMS(d, fmt, arg...) do { \
561 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 562 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
563 __LINE__, ##arg); \
564 } \
565} while (0)
566#else
567#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 568 if (drm_debug & DRM_UT_DRIVER) \
569 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
570} while (0)
571#define NV_DEBUG_KMS(d, fmt, arg...) do { \
572 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 573 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
574} while (0)
575#endif
576#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
577#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
578#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
579#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
580#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
6b5a81a2
BS		 581#define NV_WARNONCE(d, fmt, arg...) do { \
582 static int _warned = 0; \
583 if (!_warned) { \
584 NV_WARN(d, fmt, ##arg); \
585 _warned = 1; \
586 } \
587} while(0)
6ee73861
BS		 588
589/* nouveau_reg_debug bitmask */
590enum {
591 NOUVEAU_REG_DEBUG_MC = 0x1,
592 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
593 NOUVEAU_REG_DEBUG_FB = 0x4,
594 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
595 NOUVEAU_REG_DEBUG_CRTC = 0x10,
596 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
597 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
598 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
599 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
600 NOUVEAU_REG_DEBUG_EVO = 0x200,
43720133 601 NOUVEAU_REG_DEBUG_AUXCH = 0x400
6ee73861
BS		 602};
603
604#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
605 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
606 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
607} while (0)
608
609static inline bool
610nv_two_heads(struct drm_device *dev)
611{
612 struct drm_nouveau_private *dev_priv = dev->dev_private;
613 const int impl = dev->pci_device & 0x0ff0;
614
615 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
616 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
617 return true;
618
619 return false;
620}
621
622static inline bool
623nv_gf4_disp_arch(struct drm_device *dev)
624{
625 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
626}
627
628static inline bool
629nv_two_reg_pll(struct drm_device *dev)
630{
631 struct drm_nouveau_private *dev_priv = dev->dev_private;
632 const int impl = dev->pci_device & 0x0ff0;
633
634 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
635 return true;
636 return false;
637}
638
acae116c
FJ		 639static inline bool
640nv_match_device(struct drm_device *dev, unsigned device,
641 unsigned sub_vendor, unsigned sub_device)
642{
643 return dev->pdev->device == device &&
644 dev->pdev->subsystem_vendor == sub_vendor &&
645 dev->pdev->subsystem_device == sub_device;
646}
647
c693931d
BS		 648/* returns 1 if device is one of the nv4x using the 0x4497 object class,
649 * helpful to determine a number of other hardware features
650 */
651static inline int
652nv44_graph_class(struct drm_device *dev)
653{
654 struct drm_nouveau_private *dev_priv = dev->dev_private;
655
656 if ((dev_priv->chipset & 0xf0) == 0x60)
657 return 1;
658
659 return !(0x0baf & (1 << (dev_priv->chipset & 0x0f)));
660}
661
7f4a195f 662/* memory type/access flags, do not match hardware values */
a11c3198
BS		 663#define NV_MEM_ACCESS_RO 1
664#define NV_MEM_ACCESS_WO 2
7f4a195f 665#define NV_MEM_ACCESS_RW (NV_MEM_ACCESS_RO | NV_MEM_ACCESS_WO)
a11c3198
BS		 666#define NV_MEM_ACCESS_SYS 4
667#define NV_MEM_ACCESS_VM 8
990449c7 668#define NV_MEM_ACCESS_NOSNOOP 16
7f4a195f
BS		 669
670#define NV_MEM_TARGET_VRAM 0
671#define NV_MEM_TARGET_PCI 1
672#define NV_MEM_TARGET_PCI_NOSNOOP 2
673#define NV_MEM_TARGET_VM 3
674#define NV_MEM_TARGET_GART 4
675
676#define NV_MEM_TYPE_VM 0x7f
677#define NV_MEM_COMP_VM 0x03
678
b5b2e598
BS		 679/* FIFO methods */
680#define NV01_SUBCHAN_OBJECT 0x00000000
681#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
682#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
683#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
684#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
685#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
686#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
687#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
5e120f6e 688#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
b5b2e598
BS		 689#define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
690#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
691#define NV10_SUBCHAN_REF_CNT 0x00000050
d5316e25 692#define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
b5b2e598
BS		 693#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
694#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
695#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
696#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
697#define NV40_SUBCHAN_YIELD 0x00000080
698
7f4a195f 699/* NV_SW object class */
f03a314b 700#define NV_SW 0x0000506e
f03a314b
FJ		 701#define NV_SW_DMA_VBLSEM 0x0000018c
702#define NV_SW_VBLSEM_OFFSET 0x00000400
703#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
704#define NV_SW_VBLSEM_RELEASE 0x00000408
332b242f 705#define NV_SW_PAGE_FLIP 0x00000500
6ee73861
BS		 706
707#endif /* __NOUVEAU_DRV_H__ */
Linux kernel - Deliverables
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