[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_gpuobj.c

/*
 * Copyright (C) 2006 Ben Skeggs.
 *
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

/*
 * Authors:
 *   Ben Skeggs <darktama@iinet.net.au>
 */

#include "drmP.h"
#include "drm.h"
#include "nouveau_drv.h"
#include <nouveau_drm.h>
#include <engine/fifo.h>
#include <core/ramht.h>
#include "nouveau_software.h"

struct nouveau_gpuobj_method {
	struct list_head head;
	u32 mthd;
	int (*exec)(struct nouveau_channel *, u32 class, u32 mthd, u32 data);
};

struct nouveau_gpuobj_class {
	struct list_head head;
	struct list_head methods;
	u32 id;
	u32 engine;
};

int
nouveau_gpuobj_class_new(struct drm_device *dev, u32 class, u32 engine)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj_class *oc;

	oc = kzalloc(sizeof(*oc), GFP_KERNEL);
	if (!oc)
		return -ENOMEM;

	INIT_LIST_HEAD(&oc->methods);
	oc->id = class;
	oc->engine = engine;
	list_add(&oc->head, &dev_priv->classes);
	return 0;
}

int
nouveau_gpuobj_mthd_new(struct drm_device *dev, u32 class, u32 mthd,
			int (*exec)(struct nouveau_channel *, u32, u32, u32))
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj_method *om;
	struct nouveau_gpuobj_class *oc;

	list_for_each_entry(oc, &dev_priv->classes, head) {
		if (oc->id == class)
			goto found;
	}

	return -EINVAL;

found:
	om = kzalloc(sizeof(*om), GFP_KERNEL);
	if (!om)
		return -ENOMEM;

	om->mthd = mthd;
	om->exec = exec;
	list_add(&om->head, &oc->methods);
	return 0;
}

int
nouveau_gpuobj_mthd_call(struct nouveau_channel *chan,
			 u32 class, u32 mthd, u32 data)
{
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	struct nouveau_gpuobj_method *om;
	struct nouveau_gpuobj_class *oc;

	list_for_each_entry(oc, &dev_priv->classes, head) {
		if (oc->id != class)
			continue;

		list_for_each_entry(om, &oc->methods, head) {
			if (om->mthd == mthd)
				return om->exec(chan, class, mthd, data);
		}
	}

	return -ENOENT;
}

int
nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid,
			  u32 class, u32 mthd, u32 data)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
	struct nouveau_channel *chan = NULL;
	unsigned long flags;
	int ret = -EINVAL;

	spin_lock_irqsave(&dev_priv->channels.lock, flags);
	if (chid >= 0 && chid < pfifo->channels)
		chan = dev_priv->channels.ptr[chid];
	if (chan)
		ret = nouveau_gpuobj_mthd_call(chan, class, mthd, data);
	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	return ret;
}

void
nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class,
		     u64 base, u64 size, int target, int access,
		     u32 type, u32 comp)
{
	struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
	u32 flags0;

	flags0  = (comp << 29) | (type << 22) | class;
	flags0 |= 0x00100000;

	switch (access) {
	case NV_MEM_ACCESS_RO: flags0 |= 0x00040000; break;
	case NV_MEM_ACCESS_RW:
	case NV_MEM_ACCESS_WO: flags0 |= 0x00080000; break;
	default:
		break;
	}

	switch (target) {
	case NV_MEM_TARGET_VRAM:
		flags0 |= 0x00010000;
		break;
	case NV_MEM_TARGET_PCI:
		flags0 |= 0x00020000;
		break;
	case NV_MEM_TARGET_PCI_NOSNOOP:
		flags0 |= 0x00030000;
		break;
	case NV_MEM_TARGET_GART:
		base += dev_priv->gart_info.aper_base;
	default:
		flags0 &= ~0x00100000;
		break;
	}

	/* convert to base + limit */
	size = (base + size) - 1;

	nv_wo32(obj, offset + 0x00, flags0);
	nv_wo32(obj, offset + 0x04, lower_32_bits(size));
	nv_wo32(obj, offset + 0x08, lower_32_bits(base));
	nv_wo32(obj, offset + 0x0c, upper_32_bits(size) << 24 |
				    upper_32_bits(base));
	nv_wo32(obj, offset + 0x10, 0x00000000);
	nv_wo32(obj, offset + 0x14, 0x00000000);

	nvimem_flush(obj->dev);
}

int
nv50_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base, u64 size,
		    int target, int access, u32 type, u32 comp,
		    struct nouveau_gpuobj **pobj)
{
	struct drm_device *dev = chan->dev;
	int ret;

	ret = nouveau_gpuobj_new(dev, chan, 24, 16, NVOBJ_FLAG_ZERO_FREE, pobj);
	if (ret)
		return ret;

	nv50_gpuobj_dma_init(*pobj, 0, class, base, size, target,
			     access, type, comp);
	return 0;
}

int
nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
		       u64 size, int access, int target,
		       struct nouveau_gpuobj **pobj)
{
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	struct drm_device *dev = chan->dev;
	struct nouveau_gpuobj *obj;
	u32 flags0, flags2;
	int ret;

	if (dev_priv->card_type >= NV_50) {
		u32 comp = (target == NV_MEM_TARGET_VM) ? NV_MEM_COMP_VM : 0;
		u32 type = (target == NV_MEM_TARGET_VM) ? NV_MEM_TYPE_VM : 0;

		return nv50_gpuobj_dma_new(chan, class, base, size,
					   target, access, type, comp, pobj);
	}

	if (target == NV_MEM_TARGET_GART) {
		struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;

		if (dev_priv->gart_info.type == NOUVEAU_GART_PDMA) {
			if (base == 0) {
				nouveau_gpuobj_ref(gart, pobj);
				return 0;
			}

			base   = nouveau_sgdma_get_physical(dev, base);
			target = NV_MEM_TARGET_PCI;
		} else {
			base += dev_priv->gart_info.aper_base;
			if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
				target = NV_MEM_TARGET_PCI_NOSNOOP;
			else
				target = NV_MEM_TARGET_PCI;
		}
	}

	flags0  = class;
	flags0 |= 0x00003000; /* PT present, PT linear */
	flags2  = 0;

	switch (target) {
	case NV_MEM_TARGET_PCI:
		flags0 |= 0x00020000;
		break;
	case NV_MEM_TARGET_PCI_NOSNOOP:
		flags0 |= 0x00030000;
		break;
	default:
		break;
	}

	switch (access) {
	case NV_MEM_ACCESS_RO:
		flags0 |= 0x00004000;
		break;
	case NV_MEM_ACCESS_WO:
		flags0 |= 0x00008000;
	default:
		flags2 |= 0x00000002;
		break;
	}

	flags0 |= (base & 0x00000fff) << 20;
	flags2 |= (base & 0xfffff000);

	ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
	if (ret)
		return ret;

	nv_wo32(obj, 0x00, flags0);
	nv_wo32(obj, 0x04, size - 1);
	nv_wo32(obj, 0x08, flags2);
	nv_wo32(obj, 0x0c, flags2);

	obj->engine = NVOBJ_ENGINE_SW;
	obj->class  = class;
	*pobj = obj;
	return 0;
}

int
nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
{
	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	struct drm_device *dev = chan->dev;
	struct nouveau_gpuobj_class *oc;
	int ret;

	NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);

	list_for_each_entry(oc, &dev_priv->classes, head) {
		struct nouveau_exec_engine *eng = dev_priv->eng[oc->engine];

		if (oc->id != class)
			continue;

		if (!chan->engctx[oc->engine]) {
			ret = eng->context_new(chan, oc->engine);
			if (ret)
				return ret;
		}

		return eng->object_new(chan, oc->engine, handle, class);
	}

	return -EINVAL;
}

static int
nv04_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	int ret;

	ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000,
				 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
	if (ret)
		return ret;

	return 0;
}

static int
nv50_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	int ret;

	ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000,
				 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(dev, chan, 0x0200, 0, 0, &chan->ramfc);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(dev, chan, 0x1000, 0, 0, &chan->engptr);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(dev, chan, 0x4000, 0, 0, &chan->vm_pd);
	if (ret)
		return ret;

	return 0;
}

static int
nv84_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
{
	struct drm_device *dev = chan->dev;
	int ret;

	ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000,
				 NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(dev, chan, 0x0200, 0, 0, &chan->engptr);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(dev, chan, 0x4000, 0, 0, &chan->vm_pd);
	if (ret)
		return ret;

	return 0;
}

static int
nvc0_gpuobj_channel_init(struct nouveau_channel *chan, struct nouveau_vm *vm)
{
	struct drm_device *dev = chan->dev;
	int ret;

	ret = nouveau_gpuobj_new(dev, NULL, 4096, 0x1000, 0, &chan->ramin);
	if (ret)
		return ret;

	ret = nouveau_gpuobj_new(dev, NULL, 65536, 0x1000, 0, &chan->vm_pd);
	if (ret)
		return ret;

	nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);

	nv_wo32(chan->ramin, 0x0200, lower_32_bits(chan->vm_pd->addr));
	nv_wo32(chan->ramin, 0x0204, upper_32_bits(chan->vm_pd->addr));
	nv_wo32(chan->ramin, 0x0208, 0xffffffff);
	nv_wo32(chan->ramin, 0x020c, 0x000000ff);

	return 0;
}

int
nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
			    uint32_t vram_h, uint32_t tt_h)
{
	struct drm_device *dev = chan->dev;
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fpriv *fpriv = nouveau_fpriv(chan->file_priv);
	struct nouveau_vm *vm = fpriv ? fpriv->vm : dev_priv->chan_vm;
	struct nouveau_gpuobj *vram = NULL, *tt = NULL;
	int ret;

	NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
	if (dev_priv->card_type >= NV_C0)
		return nvc0_gpuobj_channel_init(chan, vm);

	/* Allocate a chunk of memory for per-channel object storage */
	if (dev_priv->chipset >= 0x84)
		ret = nv84_gpuobj_channel_init_pramin(chan);
	else
	if (dev_priv->chipset == 0x50)
		ret = nv50_gpuobj_channel_init_pramin(chan);
	else
		ret = nv04_gpuobj_channel_init_pramin(chan);
	if (ret) {
		NV_ERROR(dev, "init pramin\n");
		return ret;
	}

	/* NV50 VM
	 *  - Allocate per-channel page-directory
	 *  - Link with shared channel VM
	 */
	if (vm)
		nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);

	/* RAMHT */
	if (dev_priv->card_type < NV_50) {
		nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL);
	} else {
		struct nouveau_gpuobj *ramht = NULL;

		ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16,
					 NVOBJ_FLAG_ZERO_ALLOC, &ramht);
		if (ret)
			return ret;

		ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
		nouveau_gpuobj_ref(NULL, &ramht);
		if (ret)
			return ret;
	}

	/* VRAM ctxdma */
	if (dev_priv->card_type >= NV_50) {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     0, (1ULL << 40), NV_MEM_ACCESS_RW,
					     NV_MEM_TARGET_VM, &vram);
		if (ret) {
			NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
			return ret;
		}
	} else {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     0, dev_priv->fb_available_size,
					     NV_MEM_ACCESS_RW,
					     NV_MEM_TARGET_VRAM, &vram);
		if (ret) {
			NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
			return ret;
		}
	}

	ret = nouveau_ramht_insert(chan, vram_h, vram);
	nouveau_gpuobj_ref(NULL, &vram);
	if (ret) {
		NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret);
		return ret;
	}

	/* TT memory ctxdma */
	if (dev_priv->card_type >= NV_50) {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     0, (1ULL << 40), NV_MEM_ACCESS_RW,
					     NV_MEM_TARGET_VM, &tt);
	} else {
		ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
					     0, dev_priv->gart_info.aper_size,
					     NV_MEM_ACCESS_RW,
					     NV_MEM_TARGET_GART, &tt);
	}

	if (ret) {
		NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
		return ret;
	}

	ret = nouveau_ramht_insert(chan, tt_h, tt);
	nouveau_gpuobj_ref(NULL, &tt);
	if (ret) {
		NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret);
		return ret;
	}

	return 0;
}

void
nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
{
	NV_DEBUG(chan->dev, "ch%d\n", chan->id);

	nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
	nouveau_gpuobj_ref(NULL, &chan->vm_pd);
	nouveau_gpuobj_ref(NULL, &chan->ramfc);
	nouveau_gpuobj_ref(NULL, &chan->engptr);

	nouveau_gpuobj_ref(NULL, &chan->ramin);
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2006 Ben Skeggs.
	3	*
	4	* All Rights Reserved.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining
	7	* a copy of this software and associated documentation files (the
	8	* "Software"), to deal in the Software without restriction, including
	9	* without limitation the rights to use, copy, modify, merge, publish,
	10	* distribute, sublicense, and/or sell copies of the Software, and to
	11	* permit persons to whom the Software is furnished to do so, subject to
	12	* the following conditions:
	13	*
	14	* The above copyright notice and this permission notice (including the
	15	* next paragraph) shall be included in all copies or substantial
	16	* portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	19	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	20	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	21	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	22	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	23	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	24	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	25	*
	26	*/
	27
	28	/*
	29	* Authors:
	30	* Ben Skeggs <darktama@iinet.net.au>
	31	*/
	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "nouveau_drv.h"
94580299	36	#include <nouveau_drm.h>
02a841d4 BS	37	#include <engine/fifo.h>
02a841d4 BS	38	#include <core/ramht.h>
20abd163	39	#include "nouveau_software.h"
6ee73861	40
b8c157d3 BS	41	struct nouveau_gpuobj_method {
	42	struct list_head head;
	43	u32 mthd;
	44	int (exec)(struct nouveau_channel , u32 class, u32 mthd, u32 data);
	45	};
	46
	47	struct nouveau_gpuobj_class {
	48	struct list_head head;
	49	struct list_head methods;
	50	u32 id;
	51	u32 engine;
	52	};
	53
	54	int
	55	nouveau_gpuobj_class_new(struct drm_device *dev, u32 class, u32 engine)
	56	{
	57	struct drm_nouveau_private *dev_priv = dev->dev_private;
	58	struct nouveau_gpuobj_class *oc;
	59
	60	oc = kzalloc(sizeof(*oc), GFP_KERNEL);
	61	if (!oc)
	62	return -ENOMEM;
	63
	64	INIT_LIST_HEAD(&oc->methods);
	65	oc->id = class;
	66	oc->engine = engine;
	67	list_add(&oc->head, &dev_priv->classes);
	68	return 0;
	69	}
	70
	71	int
	72	nouveau_gpuobj_mthd_new(struct drm_device *dev, u32 class, u32 mthd,
	73	int (exec)(struct nouveau_channel , u32, u32, u32))
	74	{
	75	struct drm_nouveau_private *dev_priv = dev->dev_private;
	76	struct nouveau_gpuobj_method *om;
	77	struct nouveau_gpuobj_class *oc;
	78
	79	list_for_each_entry(oc, &dev_priv->classes, head) {
	80	if (oc->id == class)
	81	goto found;
	82	}
	83
	84	return -EINVAL;
	85
	86	found:
	87	om = kzalloc(sizeof(*om), GFP_KERNEL);
	88	if (!om)
	89	return -ENOMEM;
	90
	91	om->mthd = mthd;
	92	om->exec = exec;
	93	list_add(&om->head, &oc->methods);
	94	return 0;
	95	}
	96
	97	int
	98	nouveau_gpuobj_mthd_call(struct nouveau_channel *chan,
	99	u32 class, u32 mthd, u32 data)
	100	{
	101	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
	102	struct nouveau_gpuobj_method *om;
	103	struct nouveau_gpuobj_class *oc;
	104
105	list_for_each_entry(oc, &dev_priv->classes, head) {
106	if (oc->id != class)
107	continue;
108
109	list_for_each_entry(om, &oc->methods, head) {
110	if (om->mthd == mthd)
111	return om->exec(chan, class, mthd, data);
112	}
113	}
114
115	return -ENOENT;
116	}
117
274fec93 BS	118	int
	119	nouveau_gpuobj_mthd_call2(struct drm_device *dev, int chid,
	120	u32 class, u32 mthd, u32 data)
	121	{
	122	struct drm_nouveau_private *dev_priv = dev->dev_private;
c420b2dc	123	struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
274fec93 BS	124	struct nouveau_channel *chan = NULL;
	125	unsigned long flags;
	126	int ret = -EINVAL;
	127
	128	spin_lock_irqsave(&dev_priv->channels.lock, flags);
c420b2dc	129	if (chid >= 0 && chid < pfifo->channels)
274fec93 BS	130	chan = dev_priv->channels.ptr[chid];
	131	if (chan)
	132	ret = nouveau_gpuobj_mthd_call(chan, class, mthd, data);
	133	spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
	134	return ret;
	135	}
	136
7f4a195f BS	137	void
	138	nv50_gpuobj_dma_init(struct nouveau_gpuobj *obj, u32 offset, int class,
	139	u64 base, u64 size, int target, int access,
	140	u32 type, u32 comp)
6ee73861	141	{
7f4a195f	142	struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
7f4a195f	143	u32 flags0;
6ee73861	144
7f4a195f BS	145	flags0 = (comp << 29) \| (type << 22) \| class;
	146	flags0 \|= 0x00100000;
	147
	148	switch (access) {
	149	case NV_MEM_ACCESS_RO: flags0 \|= 0x00040000; break;
	150	case NV_MEM_ACCESS_RW:
	151	case NV_MEM_ACCESS_WO: flags0 \|= 0x00080000; break;
	152	default:
	153	break;
	154	}
6ee73861 BS	155
6ee73861 BS	156	switch (target) {
7f4a195f BS	157	case NV_MEM_TARGET_VRAM:
	158	flags0 \|= 0x00010000;
	159	break;
	160	case NV_MEM_TARGET_PCI:
	161	flags0 \|= 0x00020000;
	162	break;
	163	case NV_MEM_TARGET_PCI_NOSNOOP:
	164	flags0 \|= 0x00030000;
6ee73861	165	break;
7f4a195f	166	case NV_MEM_TARGET_GART:
b571fe21	167	base += dev_priv->gart_info.aper_base;
6ee73861	168	default:
7f4a195f	169	flags0 &= ~0x00100000;
6ee73861 BS	170	break;
	171	}
	172
7f4a195f BS	173	/* convert to base + limit */
7f4a195f BS	174	size = (base + size) - 1;
6ee73861	175
7f4a195f BS	176	nv_wo32(obj, offset + 0x00, flags0);
	177	nv_wo32(obj, offset + 0x04, lower_32_bits(size));
	178	nv_wo32(obj, offset + 0x08, lower_32_bits(base));
	179	nv_wo32(obj, offset + 0x0c, upper_32_bits(size) << 24 \|
	180	upper_32_bits(base));
	181	nv_wo32(obj, offset + 0x10, 0x00000000);
	182	nv_wo32(obj, offset + 0x14, 0x00000000);
6ee73861	183
3863c9bc	184	nvimem_flush(obj->dev);
7f4a195f	185	}
6ee73861	186
7f4a195f BS	187	int
	188	nv50_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base, u64 size,
	189	int target, int access, u32 type, u32 comp,
	190	struct nouveau_gpuobj **pobj)
	191	{
	192	struct drm_device *dev = chan->dev;
	193	int ret;
6ee73861	194
a0fd9b9f	195	ret = nouveau_gpuobj_new(dev, chan, 24, 16, NVOBJ_FLAG_ZERO_FREE, pobj);
7f4a195f BS	196	if (ret)
7f4a195f BS	197	return ret;
6ee73861	198
7f4a195f BS	199	nv50_gpuobj_dma_init(*pobj, 0, class, base, size, target,
7f4a195f BS	200	access, type, comp);
6ee73861 BS	201	return 0;
	202	}
	203
	204	int
7f4a195f BS	205	nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
	206	u64 size, int access, int target,
	207	struct nouveau_gpuobj **pobj)
6ee73861	208	{
7f4a195f	209	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
6ee73861	210	struct drm_device *dev = chan->dev;
7f4a195f	211	struct nouveau_gpuobj *obj;
fd70b6cd	212	u32 flags0, flags2;
6ee73861 BS	213	int ret;
6ee73861 BS	214
7f4a195f BS	215	if (dev_priv->card_type >= NV_50) {
	216	u32 comp = (target == NV_MEM_TARGET_VM) ? NV_MEM_COMP_VM : 0;
	217	u32 type = (target == NV_MEM_TARGET_VM) ? NV_MEM_TYPE_VM : 0;
	218
	219	return nv50_gpuobj_dma_new(chan, class, base, size,
	220	target, access, type, comp, pobj);
	221	}
	222
	223	if (target == NV_MEM_TARGET_GART) {
58e6c7a9 BS	224	struct nouveau_gpuobj *gart = dev_priv->gart_info.sg_ctxdma;
	225
	226	if (dev_priv->gart_info.type == NOUVEAU_GART_PDMA) {
	227	if (base == 0) {
	228	nouveau_gpuobj_ref(gart, pobj);
	229	return 0;
	230	}
	231
	232	base = nouveau_sgdma_get_physical(dev, base);
7f4a195f	233	target = NV_MEM_TARGET_PCI;
7f4a195f	234	} else {
58e6c7a9 BS	235	base += dev_priv->gart_info.aper_base;
	236	if (dev_priv->gart_info.type == NOUVEAU_GART_AGP)
	237	target = NV_MEM_TARGET_PCI_NOSNOOP;
	238	else
	239	target = NV_MEM_TARGET_PCI;
6ee73861	240	}
6ee73861 BS	241	}
6ee73861 BS	242
7f4a195f BS	243	flags0 = class;
	244	flags0 \|= 0x00003000; /* PT present, PT linear */
	245	flags2 = 0;
	246
	247	switch (target) {
	248	case NV_MEM_TARGET_PCI:
	249	flags0 \|= 0x00020000;
	250	break;
	251	case NV_MEM_TARGET_PCI_NOSNOOP:
	252	flags0 \|= 0x00030000;
	253	break;
	254	default:
	255	break;
	256	}
	257
	258	switch (access) {
	259	case NV_MEM_ACCESS_RO:
	260	flags0 \|= 0x00004000;
	261	break;
	262	case NV_MEM_ACCESS_WO:
	263	flags0 \|= 0x00008000;
	264	default:
	265	flags2 \|= 0x00000002;
	266	break;
	267	}
	268
	269	flags0 \|= (base & 0x00000fff) << 20;
	270	flags2 \|= (base & 0xfffff000);
	271
a0fd9b9f	272	ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
7f4a195f BS	273	if (ret)
	274	return ret;
	275
	276	nv_wo32(obj, 0x00, flags0);
	277	nv_wo32(obj, 0x04, size - 1);
	278	nv_wo32(obj, 0x08, flags2);
	279	nv_wo32(obj, 0x0c, flags2);
	280
	281	obj->engine = NVOBJ_ENGINE_SW;
	282	obj->class = class;
	283	*pobj = obj;
	284	return 0;
6ee73861 BS	285	}
6ee73861 BS	286
6ee73861	287	int
ceac3099	288	nouveau_gpuobj_gr_new(struct nouveau_channel *chan, u32 handle, int class)
6ee73861	289	{
a6a1a380	290	struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
6ee73861	291	struct drm_device *dev = chan->dev;
b8c157d3	292	struct nouveau_gpuobj_class *oc;
6ee73861 BS	293	int ret;
	294
	295	NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
	296
b8c157d3	297	list_for_each_entry(oc, &dev_priv->classes, head) {
a82dd49f	298	struct nouveau_exec_engine *eng = dev_priv->eng[oc->engine];
a6a1a380	299
a82dd49f BS	300	if (oc->id != class)
a82dd49f BS	301	continue;
a6a1a380	302
a82dd49f BS	303	if (!chan->engctx[oc->engine]) {
	304	ret = eng->context_new(chan, oc->engine);
	305	if (ret)
	306	return ret;
2703c21a	307	}
6ee73861	308
a82dd49f	309	return eng->object_new(chan, oc->engine, handle, class);
6ee73861	310	}
ceac3099	311
a82dd49f	312	return -EINVAL;
6ee73861 BS	313	}
6ee73861 BS	314
6ee73861	315	static int
8a9b889e	316	nv04_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
6ee73861 BS	317	{
6ee73861 BS	318	struct drm_device *dev = chan->dev;
6ee73861 BS	319	int ret;
6ee73861 BS	320
8a9b889e BS	321	ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000,
	322	NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
	323	if (ret)
	324	return ret;
6ee73861	325
8a9b889e BS	326	return 0;
	327	}
	328
	329	static int
	330	nv50_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
	331	{
	332	struct drm_device *dev = chan->dev;
	333	int ret;
	334
	335	ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000,
	336	NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
	337	if (ret)
	338	return ret;
	339
8a9b889e BS	340	ret = nouveau_gpuobj_new(dev, chan, 0x0200, 0, 0, &chan->ramfc);
	341	if (ret)
	342	return ret;
	343
	344	ret = nouveau_gpuobj_new(dev, chan, 0x1000, 0, 0, &chan->engptr);
	345	if (ret)
	346	return ret;
	347
	348	ret = nouveau_gpuobj_new(dev, chan, 0x4000, 0, 0, &chan->vm_pd);
	349	if (ret)
	350	return ret;
	351
	352	return 0;
	353	}
	354
	355	static int
	356	nv84_gpuobj_channel_init_pramin(struct nouveau_channel *chan)
	357	{
	358	struct drm_device *dev = chan->dev;
	359	int ret;
	360
	361	ret = nouveau_gpuobj_new(dev, NULL, 0x10000, 0x1000,
	362	NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin);
	363	if (ret)
	364	return ret;
	365
8a9b889e BS	366	ret = nouveau_gpuobj_new(dev, chan, 0x0200, 0, 0, &chan->engptr);
	367	if (ret)
	368	return ret;
	369
	370	ret = nouveau_gpuobj_new(dev, chan, 0x4000, 0, 0, &chan->vm_pd);
	371	if (ret)
6ee73861	372	return ret;
6ee73861 BS	373
	374	return 0;
	375	}
	376
5de8037a BS	377	static int
	378	nvc0_gpuobj_channel_init(struct nouveau_channel chan, struct nouveau_vm vm)
	379	{
	380	struct drm_device *dev = chan->dev;
35bcf5d5	381	int ret;
5de8037a BS	382
	383	ret = nouveau_gpuobj_new(dev, NULL, 4096, 0x1000, 0, &chan->ramin);
	384	if (ret)
	385	return ret;
	386
3863c9bc BS	387	ret = nouveau_gpuobj_new(dev, NULL, 65536, 0x1000, 0, &chan->vm_pd);
	388	if (ret)
	389	return ret;
5de8037a	390
3863c9bc BS	391	nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);
	392
	393	nv_wo32(chan->ramin, 0x0200, lower_32_bits(chan->vm_pd->addr));
	394	nv_wo32(chan->ramin, 0x0204, upper_32_bits(chan->vm_pd->addr));
5de8037a BS	395	nv_wo32(chan->ramin, 0x0208, 0xffffffff);
	396	nv_wo32(chan->ramin, 0x020c, 0x000000ff);
	397
5de8037a BS	398	return 0;
	399	}
	400
6ee73861 BS	401	int
	402	nouveau_gpuobj_channel_init(struct nouveau_channel *chan,
	403	uint32_t vram_h, uint32_t tt_h)
	404	{
	405	struct drm_device *dev = chan->dev;
	406	struct drm_nouveau_private *dev_priv = dev->dev_private;
0320d791 BS	407	struct nouveau_fpriv *fpriv = nouveau_fpriv(chan->file_priv);
0320d791 BS	408	struct nouveau_vm *vm = fpriv ? fpriv->vm : dev_priv->chan_vm;
6ee73861	409	struct nouveau_gpuobj vram = NULL, tt = NULL;
35bcf5d5	410	int ret;
6ee73861	411
6ee73861	412	NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h);
2e9733ff	413	if (dev_priv->card_type >= NV_C0)
5de8037a	414	return nvc0_gpuobj_channel_init(chan, vm);
effd6e06	415
816544b2	416	/* Allocate a chunk of memory for per-channel object storage */
8a9b889e BS	417	if (dev_priv->chipset >= 0x84)
	418	ret = nv84_gpuobj_channel_init_pramin(chan);
	419	else
	420	if (dev_priv->chipset == 0x50)
	421	ret = nv50_gpuobj_channel_init_pramin(chan);
	422	else
	423	ret = nv04_gpuobj_channel_init_pramin(chan);
816544b2 BS	424	if (ret) {
	425	NV_ERROR(dev, "init pramin\n");
	426	return ret;
6ee73861 BS	427	}
6ee73861 BS	428
effd6e06	429	/* NV50 VM
6ee73861	430	* - Allocate per-channel page-directory
4c136142	431	* - Link with shared channel VM
6ee73861	432	*/
8a9b889e	433	if (vm)
0320d791	434	nouveau_vm_ref(vm, &chan->vm, chan->vm_pd);
6ee73861 BS	435
	436	/* RAMHT */
	437	if (dev_priv->card_type < NV_50) {
a8eaebc6 BS	438	nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL);
	439	} else {
	440	struct nouveau_gpuobj *ramht = NULL;
	441
	442	ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16,
	443	NVOBJ_FLAG_ZERO_ALLOC, &ramht);
6ee73861 BS	444	if (ret)
6ee73861 BS	445	return ret;
a8eaebc6 BS	446
	447	ret = nouveau_ramht_new(dev, ramht, &chan->ramht);
	448	nouveau_gpuobj_ref(NULL, &ramht);
6ee73861 BS	449	if (ret)
	450	return ret;
	451	}
	452
	453	/* VRAM ctxdma */
	454	if (dev_priv->card_type >= NV_50) {
	455	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
4c136142	456	0, (1ULL << 40), NV_MEM_ACCESS_RW,
7f4a195f	457	NV_MEM_TARGET_VM, &vram);
6ee73861 BS	458	if (ret) {
	459	NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
	460	return ret;
	461	}
	462	} else {
	463	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
a8eaebc6	464	0, dev_priv->fb_available_size,
7f4a195f BS	465	NV_MEM_ACCESS_RW,
7f4a195f BS	466	NV_MEM_TARGET_VRAM, &vram);
6ee73861 BS	467	if (ret) {
	468	NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret);
	469	return ret;
	470	}
	471	}
	472
a8eaebc6 BS	473	ret = nouveau_ramht_insert(chan, vram_h, vram);
a8eaebc6 BS	474	nouveau_gpuobj_ref(NULL, &vram);
6ee73861	475	if (ret) {
a8eaebc6	476	NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret);
6ee73861 BS	477	return ret;
	478	}
	479
	480	/* TT memory ctxdma */
	481	if (dev_priv->card_type >= NV_50) {
a8eaebc6	482	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
4c136142	483	0, (1ULL << 40), NV_MEM_ACCESS_RW,
7f4a195f	484	NV_MEM_TARGET_VM, &tt);
6ee73861	485	} else {
7f4a195f BS	486	ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY,
	487	0, dev_priv->gart_info.aper_size,
	488	NV_MEM_ACCESS_RW,
	489	NV_MEM_TARGET_GART, &tt);
6ee73861 BS	490	}
	491
	492	if (ret) {
	493	NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret);
	494	return ret;
	495	}
	496
a8eaebc6 BS	497	ret = nouveau_ramht_insert(chan, tt_h, tt);
a8eaebc6 BS	498	nouveau_gpuobj_ref(NULL, &tt);
6ee73861	499	if (ret) {
a8eaebc6	500	NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret);
6ee73861 BS	501	return ret;
	502	}
	503
	504	return 0;
	505	}
	506
	507	void
	508	nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan)
	509	{
35bcf5d5	510	NV_DEBUG(chan->dev, "ch%d\n", chan->id);
6ee73861	511
e432d48f BS	512	nouveau_vm_ref(NULL, &chan->vm, chan->vm_pd);
e432d48f BS	513	nouveau_gpuobj_ref(NULL, &chan->vm_pd);
8a9b889e BS	514	nouveau_gpuobj_ref(NULL, &chan->ramfc);
8a9b889e BS	515	nouveau_gpuobj_ref(NULL, &chan->engptr);
e432d48f	516
a8eaebc6	517	nouveau_gpuobj_ref(NULL, &chan->ramin);
6ee73861	518	}