[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_mem.c

/*
 * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
 * Copyright 2005 Stephane Marchesin
 *
 * The Weather Channel (TM) funded Tungsten Graphics to develop the
 * initial release of the Radeon 8500 driver under the XFree86 license.
 * This notice must be preserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Whitwell <keith@tungstengraphics.com>
 */


#include "drmP.h"
#include "drm.h"
#include "drm_sarea.h"
#include "nouveau_drv.h"

/*
 * NV10-NV40 tiling helpers
 */

static void
nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
			   uint32_t size, uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	tile->addr = addr;
	tile->size = size;
	tile->used = !!pitch;
	nouveau_fence_unref((void **)&tile->fence);

	if (!pfifo->cache_flush(dev))
		return;

	pfifo->reassign(dev, false);
	pfifo->cache_flush(dev);
	pfifo->cache_pull(dev, false);

	nouveau_wait_for_idle(dev);

	pgraph->set_region_tiling(dev, i, addr, size, pitch);
	pfb->set_region_tiling(dev, i, addr, size, pitch);

	pfifo->cache_pull(dev, true);
	pfifo->reassign(dev, true);
}

struct nouveau_tile_reg *
nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
		    uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
	int i;

	spin_lock(&dev_priv->tile.lock);

	for (i = 0; i < pfb->num_tiles; i++) {
		if (tile[i].used)
			/* Tile region in use. */
			continue;

		if (tile[i].fence &&
		    !nouveau_fence_signalled(tile[i].fence, NULL))
			/* Pending tile region. */
			continue;

		if (max(tile[i].addr, addr) <
		    min(tile[i].addr + tile[i].size, addr + size))
			/* Kill an intersecting tile region. */
			nv10_mem_set_region_tiling(dev, i, 0, 0, 0);

		if (pitch && !found) {
			/* Free tile region. */
			nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
			found = &tile[i];
		}
	}

	spin_unlock(&dev_priv->tile.lock);

	return found;
}

void
nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
		       struct nouveau_fence *fence)
{
	if (fence) {
		/* Mark it as pending. */
		tile->fence = fence;
		nouveau_fence_ref(fence);
	}

	tile->used = false;
}

/*
 * NV50 VM helpers
 */
int
nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
			uint32_t flags, uint64_t phys)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *pgt;
	unsigned block;
	int i;

	virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
	size = (size >> 16) << 1;

	phys |= ((uint64_t)flags << 32);
	phys |= 1;
	if (dev_priv->vram_sys_base) {
		phys += dev_priv->vram_sys_base;
		phys |= 0x30;
	}

	while (size) {
		unsigned offset_h = upper_32_bits(phys);
		unsigned offset_l = lower_32_bits(phys);
		unsigned pte, end;

		for (i = 7; i >= 0; i--) {
			block = 1 << (i + 1);
			if (size >= block && !(virt & (block - 1)))
				break;
		}
		offset_l |= (i << 7);

		phys += block << 15;
		size -= block;

		while (block) {
			pgt = dev_priv->vm_vram_pt[virt >> 14];
			pte = virt & 0x3ffe;

			end = pte + block;
			if (end > 16384)
				end = 16384;
			block -= (end - pte);
			virt  += (end - pte);

			while (pte < end) {
				nv_wo32(pgt, (pte * 4) + 0, offset_l);
				nv_wo32(pgt, (pte * 4) + 4, offset_h);
				pte += 2;
			}
		}
	}
	dev_priv->engine.instmem.flush(dev);

	nv50_vm_flush(dev, 5);
	nv50_vm_flush(dev, 0);
	nv50_vm_flush(dev, 4);
	nv50_vm_flush(dev, 6);
	return 0;
}

void
nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *pgt;
	unsigned pages, pte, end;

	virt -= dev_priv->vm_vram_base;
	pages = (size >> 16) << 1;

	while (pages) {
		pgt = dev_priv->vm_vram_pt[virt >> 29];
		pte = (virt & 0x1ffe0000ULL) >> 15;

		end = pte + pages;
		if (end > 16384)
			end = 16384;
		pages -= (end - pte);
		virt  += (end - pte) << 15;

		while (pte < end) {
			nv_wo32(pgt, (pte * 4), 0);
			pte++;
		}
	}
	dev_priv->engine.instmem.flush(dev);

	nv50_vm_flush(dev, 5);
	nv50_vm_flush(dev, 0);
	nv50_vm_flush(dev, 4);
	nv50_vm_flush(dev, 6);
}

/*
 * Cleanup everything
 */
void
nouveau_mem_vram_fini(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	nouveau_bo_unpin(dev_priv->vga_ram);
	nouveau_bo_ref(NULL, &dev_priv->vga_ram);

	ttm_bo_device_release(&dev_priv->ttm.bdev);

	nouveau_ttm_global_release(dev_priv);

	if (dev_priv->fb_mtrr >= 0) {
		drm_mtrr_del(dev_priv->fb_mtrr,
			     pci_resource_start(dev->pdev, 1),
			     pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
		dev_priv->fb_mtrr = -1;
	}
}

void
nouveau_mem_gart_fini(struct drm_device *dev)
{
	nouveau_sgdma_takedown(dev);

	if (drm_core_has_AGP(dev) && dev->agp) {
		struct drm_agp_mem *entry, *tempe;

		/* Remove AGP resources, but leave dev->agp
		   intact until drv_cleanup is called. */
		list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
			if (entry->bound)
				drm_unbind_agp(entry->memory);
			drm_free_agp(entry->memory, entry->pages);
			kfree(entry);
		}
		INIT_LIST_HEAD(&dev->agp->memory);

		if (dev->agp->acquired)
			drm_agp_release(dev);

		dev->agp->acquired = 0;
		dev->agp->enabled = 0;
	}
}

static uint32_t
nouveau_mem_detect_nv04(struct drm_device *dev)
{
	uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);

	if (boot0 & 0x00000100)
		return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;

	switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
	case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
		return 32 * 1024 * 1024;
	case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
		return 16 * 1024 * 1024;
	case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
		return 8 * 1024 * 1024;
	case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
		return 4 * 1024 * 1024;
	}

	return 0;
}

static uint32_t
nouveau_mem_detect_nforce(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct pci_dev *bridge;
	uint32_t mem;

	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	if (!bridge) {
		NV_ERROR(dev, "no bridge device\n");
		return 0;
	}

	if (dev_priv->flags & NV_NFORCE) {
		pci_read_config_dword(bridge, 0x7C, &mem);
		return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
	} else
	if (dev_priv->flags & NV_NFORCE2) {
		pci_read_config_dword(bridge, 0x84, &mem);
		return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
	}

	NV_ERROR(dev, "impossible!\n");
	return 0;
}

static void
nv50_vram_preinit(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i, parts, colbits, rowbitsa, rowbitsb, banks;
	u64 rowsize, predicted;
	u32 r0, r4, rt, ru;

	r0 = nv_rd32(dev, 0x100200);
	r4 = nv_rd32(dev, 0x100204);
	rt = nv_rd32(dev, 0x100250);
	ru = nv_rd32(dev, 0x001540);
	NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);

	for (i = 0, parts = 0; i < 8; i++) {
		if (ru & (0x00010000 << i))
			parts++;
	}

	colbits  =  (r4 & 0x0000f000) >> 12;
	rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
	rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
	banks    = ((r4 & 0x01000000) ? 8 : 4);

	rowsize = parts * banks * (1 << colbits) * 8;
	predicted = rowsize << rowbitsa;
	if (r0 & 0x00000004)
		predicted += rowsize << rowbitsb;

	if (predicted != dev_priv->vram_size) {
		NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
			(u32)(dev_priv->vram_size >> 20));
		NV_WARN(dev, "we calculated %dMiB VRAM\n",
			(u32)(predicted >> 20));
	}

	dev_priv->vram_rblock_size = rowsize >> 12;
	if (rt & 1)
		dev_priv->vram_rblock_size *= 3;

	NV_DEBUG(dev, "rblock %lld bytes\n",
		 (u64)dev_priv->vram_rblock_size << 12);
}

static void
nvaa_vram_preinit(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* To our knowledge, there's no large scale reordering of pages
	 * that occurs on IGP chipsets.
	 */
	dev_priv->vram_rblock_size = 1;
}

static int
nouveau_mem_detect(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (dev_priv->card_type == NV_04) {
		dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
	} else
	if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
		dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
	} else
	if (dev_priv->card_type < NV_50) {
		dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
		dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
	} else
	if (dev_priv->card_type < NV_C0) {
		dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
		dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
		dev_priv->vram_size &= 0xffffffff00ll;

		switch (dev_priv->chipset) {
		case 0xaa:
		case 0xac:
		case 0xaf:
			dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
			dev_priv->vram_sys_base <<= 12;
			nvaa_vram_preinit(dev);
			break;
		default:
			nv50_vram_preinit(dev);
			break;
		}
	} else {
		dev_priv->vram_size  = nv_rd32(dev, 0x10f20c) << 20;
		dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
	}

	NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
	if (dev_priv->vram_sys_base) {
		NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
			dev_priv->vram_sys_base);
	}

	if (dev_priv->vram_size)
		return 0;
	return -ENOMEM;
}

int
nouveau_mem_reset_agp(struct drm_device *dev)
{
#if __OS_HAS_AGP
	uint32_t saved_pci_nv_1, pmc_enable;
	int ret;

	/* First of all, disable fast writes, otherwise if it's
	 * already enabled in the AGP bridge and we disable the card's
	 * AGP controller we might be locking ourselves out of it. */
	if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
	     dev->agp->mode) & PCI_AGP_COMMAND_FW) {
		struct drm_agp_info info;
		struct drm_agp_mode mode;

		ret = drm_agp_info(dev, &info);
		if (ret)
			return ret;

		mode.mode = info.mode & ~PCI_AGP_COMMAND_FW;
		ret = drm_agp_enable(dev, mode);
		if (ret)
			return ret;
	}

	saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);

	/* clear busmaster bit */
	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
	/* disable AGP */
	nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);

	/* power cycle pgraph, if enabled */
	pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
	if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
		nv_wr32(dev, NV03_PMC_ENABLE,
				pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
		nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
				NV_PMC_ENABLE_PGRAPH);
	}

	/* and restore (gives effect of resetting AGP) */
	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
#endif

	return 0;
}

int
nouveau_mem_init_agp(struct drm_device *dev)
{
#if __OS_HAS_AGP
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct drm_agp_info info;
	struct drm_agp_mode mode;
	int ret;

	if (!dev->agp->acquired) {
		ret = drm_agp_acquire(dev);
		if (ret) {
			NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
			return ret;
		}
	}

	nouveau_mem_reset_agp(dev);

	ret = drm_agp_info(dev, &info);
	if (ret) {
		NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
		return ret;
	}

	/* see agp.h for the AGPSTAT_* modes available */
	mode.mode = info.mode;
	ret = drm_agp_enable(dev, mode);
	if (ret) {
		NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
		return ret;
	}

	dev_priv->gart_info.type	= NOUVEAU_GART_AGP;
	dev_priv->gart_info.aper_base	= info.aperture_base;
	dev_priv->gart_info.aper_size	= info.aperture_size;
#endif
	return 0;
}

int
nouveau_mem_vram_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	int ret, dma_bits;

	if (dev_priv->card_type >= NV_50 &&
	    pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
		dma_bits = 40;
	else
		dma_bits = 32;

	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
	if (ret)
		return ret;

	ret = nouveau_mem_detect(dev);
	if (ret)
		return ret;

	dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);

	ret = nouveau_ttm_global_init(dev_priv);
	if (ret)
		return ret;

	ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
				 dev_priv->ttm.bo_global_ref.ref.object,
				 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
				 dma_bits <= 32 ? true : false);
	if (ret) {
		NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
		return ret;
	}

	spin_lock_init(&dev_priv->tile.lock);

	dev_priv->fb_available_size = dev_priv->vram_size;
	dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
	if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
		dev_priv->fb_mappable_pages =
			pci_resource_len(dev->pdev, 1);
	dev_priv->fb_mappable_pages >>= PAGE_SHIFT;

	/* reserve space at end of VRAM for PRAMIN */
	if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||
	    dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)
		dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
	else
	if (dev_priv->card_type >= NV_40)
		dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
	else
		dev_priv->ramin_rsvd_vram = (512 * 1024);

	dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
	dev_priv->fb_aper_free = dev_priv->fb_available_size;

	/* mappable vram */
	ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
			     dev_priv->fb_available_size >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
		return ret;
	}

	ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
			     0, 0, true, true, &dev_priv->vga_ram);
	if (ret == 0)
		ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
	if (ret) {
		NV_WARN(dev, "failed to reserve VGA memory\n");
		nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	}

	dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
					 pci_resource_len(dev->pdev, 1),
					 DRM_MTRR_WC);
	return 0;
}

int
nouveau_mem_gart_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	int ret;

	dev_priv->gart_info.type = NOUVEAU_GART_NONE;

#if !defined(__powerpc__) && !defined(__ia64__)
	if (drm_device_is_agp(dev) && dev->agp && !nouveau_noagp) {
		ret = nouveau_mem_init_agp(dev);
		if (ret)
			NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
	}
#endif

	if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
		ret = nouveau_sgdma_init(dev);
		if (ret) {
			NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
			return ret;
		}
	}

	NV_INFO(dev, "%d MiB GART (aperture)\n",
		(int)(dev_priv->gart_info.aper_size >> 20));
	dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;

	ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
			     dev_priv->gart_info.aper_size >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
		return ret;
	}

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
	3	* Copyright 2005 Stephane Marchesin
	4	*
	5	* The Weather Channel (TM) funded Tungsten Graphics to develop the
	6	* initial release of the Radeon 8500 driver under the XFree86 license.
	7	* This notice must be preserved.
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a
	10	* copy of this software and associated documentation files (the "Software"),
	11	* to deal in the Software without restriction, including without limitation
	12	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	13	* and/or sell copies of the Software, and to permit persons to whom the
	14	* Software is furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the next
	17	* paragraph) shall be included in all copies or substantial portions of the
	18	* Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	21	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	23	* THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	24	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	25	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	26	* DEALINGS IN THE SOFTWARE.
	27	*
	28	* Authors:
	29	* Keith Whitwell <keith@tungstengraphics.com>
	30	*/
	31
	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "drm_sarea.h"
	36	#include "nouveau_drv.h"
	37
a0af9add FJ	38	/*
	39	* NV10-NV40 tiling helpers
	40	*/
	41
	42	static void
	43	nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
	44	uint32_t size, uint32_t pitch)
	45	{
	46	struct drm_nouveau_private *dev_priv = dev->dev_private;
	47	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	48	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	49	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	50	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
	51
	52	tile->addr = addr;
	53	tile->size = size;
	54	tile->used = !!pitch;
	55	nouveau_fence_unref((void **)&tile->fence);
	56
	57	if (!pfifo->cache_flush(dev))
	58	return;
	59
	60	pfifo->reassign(dev, false);
	61	pfifo->cache_flush(dev);
	62	pfifo->cache_pull(dev, false);
	63
	64	nouveau_wait_for_idle(dev);
	65
	66	pgraph->set_region_tiling(dev, i, addr, size, pitch);
	67	pfb->set_region_tiling(dev, i, addr, size, pitch);
	68
	69	pfifo->cache_pull(dev, true);
	70	pfifo->reassign(dev, true);
	71	}
	72
	73	struct nouveau_tile_reg *
	74	nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
	75	uint32_t pitch)
	76	{
	77	struct drm_nouveau_private *dev_priv = dev->dev_private;
	78	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	79	struct nouveau_tile_reg tile = dev_priv->tile.reg, found = NULL;
	80	int i;
	81
	82	spin_lock(&dev_priv->tile.lock);
	83
	84	for (i = 0; i < pfb->num_tiles; i++) {
	85	if (tile[i].used)
	86	/* Tile region in use. */
	87	continue;
	88
	89	if (tile[i].fence &&
	90	!nouveau_fence_signalled(tile[i].fence, NULL))
	91	/* Pending tile region. */
	92	continue;
	93
	94	if (max(tile[i].addr, addr) <
	95	min(tile[i].addr + tile[i].size, addr + size))
	96	/* Kill an intersecting tile region. */
	97	nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
	98
	99	if (pitch && !found) {
	100	/* Free tile region. */
	101	nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
102	found = &tile[i];
103	}
104	}
105
106	spin_unlock(&dev_priv->tile.lock);
107
108	return found;
109	}
110
111	void
112	nv10_mem_expire_tiling(struct drm_device dev, struct nouveau_tile_reg tile,
113	struct nouveau_fence *fence)
114	{
115	if (fence) {
116	/* Mark it as pending. */
117	tile->fence = fence;
118	nouveau_fence_ref(fence);
119	}
120
121	tile->used = false;
122	}
123
6ee73861 BS	124	/*
	125	* NV50 VM helpers
	126	*/
	127	int
	128	nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
	129	uint32_t flags, uint64_t phys)
	130	{
	131	struct drm_nouveau_private *dev_priv = dev->dev_private;
531e7713 BS	132	struct nouveau_gpuobj *pgt;
	133	unsigned block;
	134	int i;
6ee73861	135
531e7713 BS	136	virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
531e7713 BS	137	size = (size >> 16) << 1;
6c429667 BS	138
	139	phys \|= ((uint64_t)flags << 32);
	140	phys \|= 1;
	141	if (dev_priv->vram_sys_base) {
	142	phys += dev_priv->vram_sys_base;
	143	phys \|= 0x30;
	144	}
6ee73861	145
531e7713 BS	146	while (size) {
531e7713 BS	147	unsigned offset_h = upper_32_bits(phys);
4c27bd33	148	unsigned offset_l = lower_32_bits(phys);
531e7713 BS	149	unsigned pte, end;
	150
	151	for (i = 7; i >= 0; i--) {
	152	block = 1 << (i + 1);
	153	if (size >= block && !(virt & (block - 1)))
	154	break;
	155	}
	156	offset_l \|= (i << 7);
6ee73861	157
531e7713 BS	158	phys += block << 15;
531e7713 BS	159	size -= block;
6ee73861	160
531e7713 BS	161	while (block) {
	162	pgt = dev_priv->vm_vram_pt[virt >> 14];
	163	pte = virt & 0x3ffe;
	164
	165	end = pte + block;
	166	if (end > 16384)
	167	end = 16384;
	168	block -= (end - pte);
	169	virt += (end - pte);
	170
	171	while (pte < end) {
b3beb167 BS	172	nv_wo32(pgt, (pte * 4) + 0, offset_l);
	173	nv_wo32(pgt, (pte * 4) + 4, offset_h);
	174	pte += 2;
531e7713 BS	175	}
531e7713 BS	176	}
6ee73861	177	}
f56cb86f	178	dev_priv->engine.instmem.flush(dev);
6ee73861	179
63187215 BS	180	nv50_vm_flush(dev, 5);
	181	nv50_vm_flush(dev, 0);
	182	nv50_vm_flush(dev, 4);
	183	nv50_vm_flush(dev, 6);
6ee73861 BS	184	return 0;
	185	}
	186
	187	void
	188	nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
	189	{
4c27bd33 BS	190	struct drm_nouveau_private *dev_priv = dev->dev_private;
	191	struct nouveau_gpuobj *pgt;
	192	unsigned pages, pte, end;
	193
	194	virt -= dev_priv->vm_vram_base;
	195	pages = (size >> 16) << 1;
	196
4c27bd33 BS	197	while (pages) {
	198	pgt = dev_priv->vm_vram_pt[virt >> 29];
	199	pte = (virt & 0x1ffe0000ULL) >> 15;
	200
	201	end = pte + pages;
	202	if (end > 16384)
	203	end = 16384;
	204	pages -= (end - pte);
	205	virt += (end - pte) << 15;
	206
b3beb167 BS	207	while (pte < end) {
	208	nv_wo32(pgt, (pte * 4), 0);
	209	pte++;
	210	}
4c27bd33	211	}
f56cb86f	212	dev_priv->engine.instmem.flush(dev);
4c27bd33	213
63187215 BS	214	nv50_vm_flush(dev, 5);
	215	nv50_vm_flush(dev, 0);
	216	nv50_vm_flush(dev, 4);
	217	nv50_vm_flush(dev, 6);
6ee73861 BS	218	}
	219
	220	/*
	221	* Cleanup everything
	222	*/
b833ac26	223	void
fbd2895e	224	nouveau_mem_vram_fini(struct drm_device *dev)
6ee73861 BS	225	{
	226	struct drm_nouveau_private *dev_priv = dev->dev_private;
	227
ac8fb975 BS	228	nouveau_bo_unpin(dev_priv->vga_ram);
	229	nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	230
6ee73861 BS	231	ttm_bo_device_release(&dev_priv->ttm.bdev);
	232
	233	nouveau_ttm_global_release(dev_priv);
	234
fbd2895e BS	235	if (dev_priv->fb_mtrr >= 0) {
	236	drm_mtrr_del(dev_priv->fb_mtrr,
	237	pci_resource_start(dev->pdev, 1),
	238	pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
	239	dev_priv->fb_mtrr = -1;
	240	}
	241	}
	242
	243	void
	244	nouveau_mem_gart_fini(struct drm_device *dev)
	245	{
	246	nouveau_sgdma_takedown(dev);
	247
cd0b072f	248	if (drm_core_has_AGP(dev) && dev->agp) {
6ee73861 BS	249	struct drm_agp_mem entry, tempe;
	250
	251	/* Remove AGP resources, but leave dev->agp
	252	intact until drv_cleanup is called. */
	253	list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
	254	if (entry->bound)
	255	drm_unbind_agp(entry->memory);
	256	drm_free_agp(entry->memory, entry->pages);
	257	kfree(entry);
	258	}
	259	INIT_LIST_HEAD(&dev->agp->memory);
	260
	261	if (dev->agp->acquired)
	262	drm_agp_release(dev);
	263
	264	dev->agp->acquired = 0;
	265	dev->agp->enabled = 0;
	266	}
6ee73861 BS	267	}
6ee73861 BS	268
6ee73861	269	static uint32_t
a76fb4e8 BS	270	nouveau_mem_detect_nv04(struct drm_device *dev)
a76fb4e8 BS	271	{
3c7066bc	272	uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
a76fb4e8 BS	273
	274	if (boot0 & 0x00000100)
	275	return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
	276
3c7066bc FJ	277	switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
3c7066bc FJ	278	case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
a76fb4e8	279	return 32 * 1024 * 1024;
3c7066bc	280	case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
a76fb4e8	281	return 16 * 1024 * 1024;
3c7066bc	282	case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
a76fb4e8	283	return 8 * 1024 * 1024;
3c7066bc	284	case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
a76fb4e8 BS	285	return 4 * 1024 * 1024;
	286	}
	287
	288	return 0;
	289	}
	290
	291	static uint32_t
	292	nouveau_mem_detect_nforce(struct drm_device *dev)
6ee73861 BS	293	{
	294	struct drm_nouveau_private *dev_priv = dev->dev_private;
	295	struct pci_dev *bridge;
	296	uint32_t mem;
	297
	298	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	299	if (!bridge) {
	300	NV_ERROR(dev, "no bridge device\n");
	301	return 0;
	302	}
	303
a76fb4e8	304	if (dev_priv->flags & NV_NFORCE) {
6ee73861 BS	305	pci_read_config_dword(bridge, 0x7C, &mem);
	306	return (uint64_t)(((mem >> 6) & 31) + 1)10241024;
	307	} else
a76fb4e8	308	if (dev_priv->flags & NV_NFORCE2) {
6ee73861 BS	309	pci_read_config_dword(bridge, 0x84, &mem);
	310	return (uint64_t)(((mem >> 4) & 127) + 1)10241024;
	311	}
	312
	313	NV_ERROR(dev, "impossible!\n");
	314	return 0;
	315	}
	316
6c3d7ef2 BS	317	static void
	318	nv50_vram_preinit(struct drm_device *dev)
	319	{
	320	struct drm_nouveau_private *dev_priv = dev->dev_private;
	321	int i, parts, colbits, rowbitsa, rowbitsb, banks;
	322	u64 rowsize, predicted;
	323	u32 r0, r4, rt, ru;
	324
	325	r0 = nv_rd32(dev, 0x100200);
	326	r4 = nv_rd32(dev, 0x100204);
	327	rt = nv_rd32(dev, 0x100250);
	328	ru = nv_rd32(dev, 0x001540);
	329	NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
	330
	331	for (i = 0, parts = 0; i < 8; i++) {
	332	if (ru & (0x00010000 << i))
	333	parts++;
	334	}
	335
	336	colbits = (r4 & 0x0000f000) >> 12;
	337	rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
	338	rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
	339	banks = ((r4 & 0x01000000) ? 8 : 4);
	340
	341	rowsize = parts * banks * (1 << colbits) * 8;
	342	predicted = rowsize << rowbitsa;
	343	if (r0 & 0x00000004)
	344	predicted += rowsize << rowbitsb;
	345
	346	if (predicted != dev_priv->vram_size) {
	347	NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
	348	(u32)(dev_priv->vram_size >> 20));
	349	NV_WARN(dev, "we calculated %dMiB VRAM\n",
	350	(u32)(predicted >> 20));
	351	}
	352
	353	dev_priv->vram_rblock_size = rowsize >> 12;
	354	if (rt & 1)
	355	dev_priv->vram_rblock_size *= 3;
	356
	357	NV_DEBUG(dev, "rblock %lld bytes\n",
	358	(u64)dev_priv->vram_rblock_size << 12);
	359	}
	360
	361	static void
	362	nvaa_vram_preinit(struct drm_device *dev)
	363	{
	364	struct drm_nouveau_private *dev_priv = dev->dev_private;
	365
	366	/* To our knowledge, there's no large scale reordering of pages
	367	* that occurs on IGP chipsets.
	368	*/
	369	dev_priv->vram_rblock_size = 1;
	370	}
	371
fbd2895e	372	static int
a76fb4e8	373	nouveau_mem_detect(struct drm_device *dev)
6ee73861 BS	374	{
6ee73861 BS	375	struct drm_nouveau_private *dev_priv = dev->dev_private;
a76fb4e8 BS	376
	377	if (dev_priv->card_type == NV_04) {
	378	dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
	379	} else
	380	if (dev_priv->flags & (NV_NFORCE \| NV_NFORCE2)) {
	381	dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
7a2e4e03 BS	382	} else
7a2e4e03 BS	383	if (dev_priv->card_type < NV_50) {
3c7066bc FJ	384	dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
3c7066bc FJ	385	dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
c556d989 BS	386	} else
c556d989 BS	387	if (dev_priv->card_type < NV_C0) {
3c7066bc	388	dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
7a2e4e03	389	dev_priv->vram_size \|= (dev_priv->vram_size & 0xff) << 32;
6e86e041	390	dev_priv->vram_size &= 0xffffffff00ll;
6c3d7ef2 BS	391
	392	switch (dev_priv->chipset) {
	393	case 0xaa:
	394	case 0xac:
	395	case 0xaf:
8b281db5 BS	396	dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
8b281db5 BS	397	dev_priv->vram_sys_base <<= 12;
6c3d7ef2 BS	398	nvaa_vram_preinit(dev);
	399	break;
	400	default:
	401	nv50_vram_preinit(dev);
	402	break;
fb4f5621	403	}
c556d989 BS	404	} else {
	405	dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
	406	dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
6ee73861 BS	407	}
6ee73861 BS	408
a76fb4e8 BS	409	NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
	410	if (dev_priv->vram_sys_base) {
	411	NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
	412	dev_priv->vram_sys_base);
	413	}
	414
	415	if (dev_priv->vram_size)
	416	return 0;
	417	return -ENOMEM;
6ee73861 BS	418	}
6ee73861 BS	419
e04d8e82 FJ	420	int
e04d8e82 FJ	421	nouveau_mem_reset_agp(struct drm_device *dev)
6ee73861	422	{
e04d8e82 FJ	423	#if __OS_HAS_AGP
	424	uint32_t saved_pci_nv_1, pmc_enable;
	425	int ret;
	426
	427	/* First of all, disable fast writes, otherwise if it's
	428	* already enabled in the AGP bridge and we disable the card's
	429	* AGP controller we might be locking ourselves out of it. */
316f60a1 FJ	430	if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) \|
316f60a1 FJ	431	dev->agp->mode) & PCI_AGP_COMMAND_FW) {
e04d8e82 FJ	432	struct drm_agp_info info;
	433	struct drm_agp_mode mode;
	434
	435	ret = drm_agp_info(dev, &info);
	436	if (ret)
	437	return ret;
	438
2b495268	439	mode.mode = info.mode & ~PCI_AGP_COMMAND_FW;
e04d8e82 FJ	440	ret = drm_agp_enable(dev, mode);
	441	if (ret)
	442	return ret;
	443	}
6ee73861 BS	444
6ee73861 BS	445	saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
6ee73861 BS	446
	447	/* clear busmaster bit */
	448	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
e04d8e82 FJ	449	/* disable AGP */
e04d8e82 FJ	450	nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
6ee73861 BS	451
	452	/* power cycle pgraph, if enabled */
	453	pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
	454	if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
	455	nv_wr32(dev, NV03_PMC_ENABLE,
	456	pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
	457	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \|
	458	NV_PMC_ENABLE_PGRAPH);
	459	}
	460
	461	/* and restore (gives effect of resetting AGP) */
6ee73861	462	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
b694dfb2	463	#endif
6ee73861	464
e04d8e82 FJ	465	return 0;
	466	}
	467
6ee73861 BS	468	int
	469	nouveau_mem_init_agp(struct drm_device *dev)
	470	{
b694dfb2	471	#if __OS_HAS_AGP
6ee73861 BS	472	struct drm_nouveau_private *dev_priv = dev->dev_private;
	473	struct drm_agp_info info;
	474	struct drm_agp_mode mode;
	475	int ret;
	476
6ee73861 BS	477	if (!dev->agp->acquired) {
	478	ret = drm_agp_acquire(dev);
	479	if (ret) {
	480	NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
	481	return ret;
	482	}
	483	}
	484
2b495268 FJ	485	nouveau_mem_reset_agp(dev);
2b495268 FJ	486
6ee73861 BS	487	ret = drm_agp_info(dev, &info);
	488	if (ret) {
	489	NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
	490	return ret;
	491	}
	492
	493	/* see agp.h for the AGPSTAT_* modes available */
	494	mode.mode = info.mode;
	495	ret = drm_agp_enable(dev, mode);
	496	if (ret) {
	497	NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
	498	return ret;
	499	}
	500
	501	dev_priv->gart_info.type = NOUVEAU_GART_AGP;
	502	dev_priv->gart_info.aper_base = info.aperture_base;
	503	dev_priv->gart_info.aper_size = info.aperture_size;
b694dfb2	504	#endif
6ee73861 BS	505	return 0;
	506	}
	507
	508	int
fbd2895e	509	nouveau_mem_vram_init(struct drm_device *dev)
6ee73861 BS	510	{
	511	struct drm_nouveau_private *dev_priv = dev->dev_private;
	512	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
fbd2895e	513	int ret, dma_bits;
6ee73861 BS	514
	515	if (dev_priv->card_type >= NV_50 &&
	516	pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
	517	dma_bits = 40;
fbd2895e BS	518	else
fbd2895e BS	519	dma_bits = 32;
6ee73861 BS	520
6ee73861 BS	521	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
fbd2895e	522	if (ret)
6ee73861	523	return ret;
fbd2895e BS	524
	525	ret = nouveau_mem_detect(dev);
	526	if (ret)
	527	return ret;
	528
	529	dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
6ee73861 BS	530
	531	ret = nouveau_ttm_global_init(dev_priv);
	532	if (ret)
	533	return ret;
	534
	535	ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
	536	dev_priv->ttm.bo_global_ref.ref.object,
	537	&nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
	538	dma_bits <= 32 ? true : false);
	539	if (ret) {
	540	NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
	541	return ret;
	542	}
	543
a0af9add	544	spin_lock_init(&dev_priv->tile.lock);
6ee73861	545
a76fb4e8	546	dev_priv->fb_available_size = dev_priv->vram_size;
6ee73861	547	dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
01d73a69 JC	548	if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
	549	dev_priv->fb_mappable_pages =
	550	pci_resource_len(dev->pdev, 1);
6ee73861 BS	551	dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
6ee73861 BS	552
fbd2895e BS	553	/* reserve space at end of VRAM for PRAMIN */
	554	if (dev_priv->chipset == 0x40 \|\| dev_priv->chipset == 0x47 \|\|
	555	dev_priv->chipset == 0x49 \|\| dev_priv->chipset == 0x4b)
	556	dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
	557	else
	558	if (dev_priv->card_type >= NV_40)
	559	dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
	560	else
	561	dev_priv->ramin_rsvd_vram = (512 * 1024);
	562
6ee73861 BS	563	dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
	564	dev_priv->fb_aper_free = dev_priv->fb_available_size;
	565
	566	/* mappable vram */
	567	ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
	568	dev_priv->fb_available_size >> PAGE_SHIFT);
	569	if (ret) {
	570	NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
	571	return ret;
	572	}
	573
ac8fb975 BS	574	ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
	575	0, 0, true, true, &dev_priv->vga_ram);
	576	if (ret == 0)
	577	ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
	578	if (ret) {
	579	NV_WARN(dev, "failed to reserve VGA memory\n");
	580	nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	581	}
	582
fbd2895e BS	583	dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
	584	pci_resource_len(dev->pdev, 1),
	585	DRM_MTRR_WC);
	586	return 0;
	587	}
	588
	589	int
	590	nouveau_mem_gart_init(struct drm_device *dev)
	591	{
	592	struct drm_nouveau_private *dev_priv = dev->dev_private;
	593	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	594	int ret;
	595
	596	dev_priv->gart_info.type = NOUVEAU_GART_NONE;
	597
6ee73861	598	#if !defined(__powerpc__) && !defined(__ia64__)
e04d8e82	599	if (drm_device_is_agp(dev) && dev->agp && !nouveau_noagp) {
6ee73861 BS	600	ret = nouveau_mem_init_agp(dev);
	601	if (ret)
	602	NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
	603	}
	604	#endif
	605
	606	if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
	607	ret = nouveau_sgdma_init(dev);
	608	if (ret) {
	609	NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
	610	return ret;
	611	}
	612	}
	613
	614	NV_INFO(dev, "%d MiB GART (aperture)\n",
	615	(int)(dev_priv->gart_info.aper_size >> 20));
	616	dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
	617
	618	ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
	619	dev_priv->gart_info.aper_size >> PAGE_SHIFT);
	620	if (ret) {
	621	NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
	622	return ret;
	623	}
	624
6ee73861 BS	625	return 0;
	626	}
	627