[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_mem.c

/*
 * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
 * Copyright 2005 Stephane Marchesin
 *
 * The Weather Channel (TM) funded Tungsten Graphics to develop the
 * initial release of the Radeon 8500 driver under the XFree86 license.
 * This notice must be preserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Whitwell <keith@tungstengraphics.com>
 */


#include "drmP.h"
#include "drm.h"
#include "drm_sarea.h"
#include "nouveau_drv.h"

/*
 * NV10-NV40 tiling helpers
 */

static void
nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
			   uint32_t size, uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_tile_reg *tile = &dev_priv->tile[i];

	tile->addr = addr;
	tile->size = size;
	tile->used = !!pitch;
	nouveau_fence_unref((void **)&tile->fence);

	pfifo->reassign(dev, false);
	pfifo->cache_pull(dev, false);

	nouveau_wait_for_idle(dev);

	pgraph->set_region_tiling(dev, i, addr, size, pitch);
	pfb->set_region_tiling(dev, i, addr, size, pitch);

	pfifo->cache_pull(dev, true);
	pfifo->reassign(dev, true);
}

struct nouveau_tile_reg *
nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
		    uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_tile_reg *found = NULL;
	unsigned long i, flags;

	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);

	for (i = 0; i < pfb->num_tiles; i++) {
		struct nouveau_tile_reg *tile = &dev_priv->tile[i];

		if (tile->used)
			/* Tile region in use. */
			continue;

		if (tile->fence &&
		    !nouveau_fence_signalled(tile->fence, NULL))
			/* Pending tile region. */
			continue;

		if (max(tile->addr, addr) <
		    min(tile->addr + tile->size, addr + size))
			/* Kill an intersecting tile region. */
			nv10_mem_set_region_tiling(dev, i, 0, 0, 0);

		if (pitch && !found) {
			/* Free tile region. */
			nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
			found = tile;
		}
	}

	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);

	return found;
}

void
nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
		       struct nouveau_fence *fence)
{
	if (fence) {
		/* Mark it as pending. */
		tile->fence = fence;
		nouveau_fence_ref(fence);
	}

	tile->used = false;
}

/*
 * NV50 VM helpers
 */
int
nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
			uint32_t flags, uint64_t phys)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *pgt;
	unsigned block;
	int i;

	virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
	size = (size >> 16) << 1;

	phys |= ((uint64_t)flags << 32);
	phys |= 1;
	if (dev_priv->vram_sys_base) {
		phys += dev_priv->vram_sys_base;
		phys |= 0x30;
	}

	while (size) {
		unsigned offset_h = upper_32_bits(phys);
		unsigned offset_l = lower_32_bits(phys);
		unsigned pte, end;

		for (i = 7; i >= 0; i--) {
			block = 1 << (i + 1);
			if (size >= block && !(virt & (block - 1)))
				break;
		}
		offset_l |= (i << 7);

		phys += block << 15;
		size -= block;

		while (block) {
			pgt = dev_priv->vm_vram_pt[virt >> 14];
			pte = virt & 0x3ffe;

			end = pte + block;
			if (end > 16384)
				end = 16384;
			block -= (end - pte);
			virt  += (end - pte);

			while (pte < end) {
				nv_wo32(pgt, (pte * 4) + 0, offset_l);
				nv_wo32(pgt, (pte * 4) + 4, offset_h);
				pte += 2;
			}
		}
	}
	dev_priv->engine.instmem.flush(dev);

	nv50_vm_flush(dev, 5);
	nv50_vm_flush(dev, 0);
	nv50_vm_flush(dev, 4);
	nv50_vm_flush(dev, 6);
	return 0;
}

void
nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *pgt;
	unsigned pages, pte, end;

	virt -= dev_priv->vm_vram_base;
	pages = (size >> 16) << 1;

	while (pages) {
		pgt = dev_priv->vm_vram_pt[virt >> 29];
		pte = (virt & 0x1ffe0000ULL) >> 15;

		end = pte + pages;
		if (end > 16384)
			end = 16384;
		pages -= (end - pte);
		virt  += (end - pte) << 15;

		while (pte < end) {
			nv_wo32(pgt, (pte * 4), 0);
			pte++;
		}
	}
	dev_priv->engine.instmem.flush(dev);

	nv50_vm_flush(dev, 5);
	nv50_vm_flush(dev, 0);
	nv50_vm_flush(dev, 4);
	nv50_vm_flush(dev, 6);
}

/*
 * Cleanup everything
 */
void
nouveau_mem_vram_fini(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	nouveau_bo_unpin(dev_priv->vga_ram);
	nouveau_bo_ref(NULL, &dev_priv->vga_ram);

	ttm_bo_device_release(&dev_priv->ttm.bdev);

	nouveau_ttm_global_release(dev_priv);

	if (dev_priv->fb_mtrr >= 0) {
		drm_mtrr_del(dev_priv->fb_mtrr,
			     pci_resource_start(dev->pdev, 1),
			     pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
		dev_priv->fb_mtrr = -1;
	}
}

void
nouveau_mem_gart_fini(struct drm_device *dev)
{
	nouveau_sgdma_takedown(dev);

	if (drm_core_has_AGP(dev) && dev->agp) {
		struct drm_agp_mem *entry, *tempe;

		/* Remove AGP resources, but leave dev->agp
		   intact until drv_cleanup is called. */
		list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
			if (entry->bound)
				drm_unbind_agp(entry->memory);
			drm_free_agp(entry->memory, entry->pages);
			kfree(entry);
		}
		INIT_LIST_HEAD(&dev->agp->memory);

		if (dev->agp->acquired)
			drm_agp_release(dev);

		dev->agp->acquired = 0;
		dev->agp->enabled = 0;
	}
}

static uint32_t
nouveau_mem_detect_nv04(struct drm_device *dev)
{
	uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);

	if (boot0 & 0x00000100)
		return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;

	switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
	case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
		return 32 * 1024 * 1024;
	case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
		return 16 * 1024 * 1024;
	case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
		return 8 * 1024 * 1024;
	case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
		return 4 * 1024 * 1024;
	}

	return 0;
}

static uint32_t
nouveau_mem_detect_nforce(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct pci_dev *bridge;
	uint32_t mem;

	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	if (!bridge) {
		NV_ERROR(dev, "no bridge device\n");
		return 0;
	}

	if (dev_priv->flags & NV_NFORCE) {
		pci_read_config_dword(bridge, 0x7C, &mem);
		return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
	} else
	if (dev_priv->flags & NV_NFORCE2) {
		pci_read_config_dword(bridge, 0x84, &mem);
		return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
	}

	NV_ERROR(dev, "impossible!\n");
	return 0;
}

static void
nv50_vram_preinit(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	int i, parts, colbits, rowbitsa, rowbitsb, banks;
	u64 rowsize, predicted;
	u32 r0, r4, rt, ru;

	r0 = nv_rd32(dev, 0x100200);
	r4 = nv_rd32(dev, 0x100204);
	rt = nv_rd32(dev, 0x100250);
	ru = nv_rd32(dev, 0x001540);
	NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);

	for (i = 0, parts = 0; i < 8; i++) {
		if (ru & (0x00010000 << i))
			parts++;
	}

	colbits  =  (r4 & 0x0000f000) >> 12;
	rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
	rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
	banks    = ((r4 & 0x01000000) ? 8 : 4);

	rowsize = parts * banks * (1 << colbits) * 8;
	predicted = rowsize << rowbitsa;
	if (r0 & 0x00000004)
		predicted += rowsize << rowbitsb;

	if (predicted != dev_priv->vram_size) {
		NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
			(u32)(dev_priv->vram_size >> 20));
		NV_WARN(dev, "we calculated %dMiB VRAM\n",
			(u32)(predicted >> 20));
	}

	dev_priv->vram_rblock_size = rowsize >> 12;
	if (rt & 1)
		dev_priv->vram_rblock_size *= 3;

	NV_DEBUG(dev, "rblock %lld bytes\n",
		 (u64)dev_priv->vram_rblock_size << 12);
}

static void
nvaa_vram_preinit(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/* To our knowledge, there's no large scale reordering of pages
	 * that occurs on IGP chipsets.
	 */
	dev_priv->vram_rblock_size = 1;
}

static int
nouveau_mem_detect(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (dev_priv->card_type == NV_04) {
		dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
	} else
	if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
		dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
	} else
	if (dev_priv->card_type < NV_50) {
		dev_priv->vram_size  = nv_rd32(dev, NV04_PFB_FIFO_DATA);
		dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
	} else
	if (dev_priv->card_type < NV_C0) {
		dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
		dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
		dev_priv->vram_size &= 0xffffffff00ll;

		switch (dev_priv->chipset) {
		case 0xaa:
		case 0xac:
		case 0xaf:
			dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
			dev_priv->vram_sys_base <<= 12;
			nvaa_vram_preinit(dev);
			break;
		default:
			nv50_vram_preinit(dev);
			break;
		}
	} else {
		dev_priv->vram_size  = nv_rd32(dev, 0x10f20c) << 20;
		dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
	}

	NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
	if (dev_priv->vram_sys_base) {
		NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
			dev_priv->vram_sys_base);
	}

	if (dev_priv->vram_size)
		return 0;
	return -ENOMEM;
}

#if __OS_HAS_AGP
static unsigned long
get_agp_mode(struct drm_device *dev, unsigned long mode)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	/*
	 * FW seems to be broken on nv18, it makes the card lock up
	 * randomly.
	 */
	if (dev_priv->chipset == 0x18)
		mode &= ~PCI_AGP_COMMAND_FW;

	/*
	 * AGP mode set in the command line.
	 */
	if (nouveau_agpmode > 0) {
		bool agpv3 = mode & 0x8;
		int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;

		mode = (mode & ~0x7) | (rate & 0x7);
	}

	return mode;
}
#endif

int
nouveau_mem_reset_agp(struct drm_device *dev)
{
#if __OS_HAS_AGP
	uint32_t saved_pci_nv_1, pmc_enable;
	int ret;

	/* First of all, disable fast writes, otherwise if it's
	 * already enabled in the AGP bridge and we disable the card's
	 * AGP controller we might be locking ourselves out of it. */
	if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
	     dev->agp->mode) & PCI_AGP_COMMAND_FW) {
		struct drm_agp_info info;
		struct drm_agp_mode mode;

		ret = drm_agp_info(dev, &info);
		if (ret)
			return ret;

		mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
		ret = drm_agp_enable(dev, mode);
		if (ret)
			return ret;
	}

	saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);

	/* clear busmaster bit */
	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
	/* disable AGP */
	nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);

	/* power cycle pgraph, if enabled */
	pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
	if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
		nv_wr32(dev, NV03_PMC_ENABLE,
				pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
		nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
				NV_PMC_ENABLE_PGRAPH);
	}

	/* and restore (gives effect of resetting AGP) */
	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
#endif

	return 0;
}

int
nouveau_mem_init_agp(struct drm_device *dev)
{
#if __OS_HAS_AGP
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct drm_agp_info info;
	struct drm_agp_mode mode;
	int ret;

	if (!dev->agp->acquired) {
		ret = drm_agp_acquire(dev);
		if (ret) {
			NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
			return ret;
		}
	}

	nouveau_mem_reset_agp(dev);

	ret = drm_agp_info(dev, &info);
	if (ret) {
		NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
		return ret;
	}

	/* see agp.h for the AGPSTAT_* modes available */
	mode.mode = get_agp_mode(dev, info.mode);
	ret = drm_agp_enable(dev, mode);
	if (ret) {
		NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
		return ret;
	}

	dev_priv->gart_info.type	= NOUVEAU_GART_AGP;
	dev_priv->gart_info.aper_base	= info.aperture_base;
	dev_priv->gart_info.aper_size	= info.aperture_size;
#endif
	return 0;
}

int
nouveau_mem_vram_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	int ret, dma_bits;

	if (dev_priv->card_type >= NV_50 &&
	    pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
		dma_bits = 40;
	else
		dma_bits = 32;

	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
	if (ret)
		return ret;

	ret = nouveau_mem_detect(dev);
	if (ret)
		return ret;

	dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);

	ret = nouveau_ttm_global_init(dev_priv);
	if (ret)
		return ret;

	ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
				 dev_priv->ttm.bo_global_ref.ref.object,
				 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
				 dma_bits <= 32 ? true : false);
	if (ret) {
		NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
		return ret;
	}

	dev_priv->fb_available_size = dev_priv->vram_size;
	dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
	if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
		dev_priv->fb_mappable_pages =
			pci_resource_len(dev->pdev, 1);
	dev_priv->fb_mappable_pages >>= PAGE_SHIFT;

	/* reserve space at end of VRAM for PRAMIN */
	if (dev_priv->chipset == 0x40 || dev_priv->chipset == 0x47 ||
	    dev_priv->chipset == 0x49 || dev_priv->chipset == 0x4b)
		dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
	else
	if (dev_priv->card_type >= NV_40)
		dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
	else
		dev_priv->ramin_rsvd_vram = (512 * 1024);

	dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
	dev_priv->fb_aper_free = dev_priv->fb_available_size;

	/* mappable vram */
	ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
			     dev_priv->fb_available_size >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
		return ret;
	}

	ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
			     0, 0, true, true, &dev_priv->vga_ram);
	if (ret == 0)
		ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
	if (ret) {
		NV_WARN(dev, "failed to reserve VGA memory\n");
		nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	}

	dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
					 pci_resource_len(dev->pdev, 1),
					 DRM_MTRR_WC);
	return 0;
}

int
nouveau_mem_gart_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	int ret;

	dev_priv->gart_info.type = NOUVEAU_GART_NONE;

#if !defined(__powerpc__) && !defined(__ia64__)
	if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
		ret = nouveau_mem_init_agp(dev);
		if (ret)
			NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
	}
#endif

	if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
		ret = nouveau_sgdma_init(dev);
		if (ret) {
			NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
			return ret;
		}
	}

	NV_INFO(dev, "%d MiB GART (aperture)\n",
		(int)(dev_priv->gart_info.aper_size >> 20));
	dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;

	ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
			     dev_priv->gart_info.aper_size >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
		return ret;
	}

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
	3	* Copyright 2005 Stephane Marchesin
	4	*
	5	* The Weather Channel (TM) funded Tungsten Graphics to develop the
	6	* initial release of the Radeon 8500 driver under the XFree86 license.
	7	* This notice must be preserved.
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a
	10	* copy of this software and associated documentation files (the "Software"),
	11	* to deal in the Software without restriction, including without limitation
	12	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	13	* and/or sell copies of the Software, and to permit persons to whom the
	14	* Software is furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the next
	17	* paragraph) shall be included in all copies or substantial portions of the
	18	* Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	21	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	23	* THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	24	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	25	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	26	* DEALINGS IN THE SOFTWARE.
	27	*
	28	* Authors:
	29	* Keith Whitwell <keith@tungstengraphics.com>
	30	*/
	31
	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "drm_sarea.h"
	36	#include "nouveau_drv.h"
	37
a0af9add FJ	38	/*
	39	* NV10-NV40 tiling helpers
	40	*/
	41
	42	static void
	43	nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
	44	uint32_t size, uint32_t pitch)
	45	{
	46	struct drm_nouveau_private *dev_priv = dev->dev_private;
	47	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	48	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	49	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
9f56b126	50	struct nouveau_tile_reg *tile = &dev_priv->tile[i];
a0af9add FJ	51
	52	tile->addr = addr;
	53	tile->size = size;
	54	tile->used = !!pitch;
	55	nouveau_fence_unref((void **)&tile->fence);
	56
a0af9add	57	pfifo->reassign(dev, false);
a0af9add FJ	58	pfifo->cache_pull(dev, false);
	59
	60	nouveau_wait_for_idle(dev);
	61
	62	pgraph->set_region_tiling(dev, i, addr, size, pitch);
	63	pfb->set_region_tiling(dev, i, addr, size, pitch);
	64
	65	pfifo->cache_pull(dev, true);
	66	pfifo->reassign(dev, true);
	67	}
	68
	69	struct nouveau_tile_reg *
	70	nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
	71	uint32_t pitch)
	72	{
	73	struct drm_nouveau_private *dev_priv = dev->dev_private;
	74	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
9f56b126 FJ	75	struct nouveau_tile_reg *found = NULL;
9f56b126 FJ	76	unsigned long i, flags;
a0af9add	77
9f56b126	78	spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
a0af9add FJ	79
a0af9add FJ	80	for (i = 0; i < pfb->num_tiles; i++) {
9f56b126 FJ	81	struct nouveau_tile_reg *tile = &dev_priv->tile[i];
	82
	83	if (tile->used)
a0af9add FJ	84	/* Tile region in use. */
	85	continue;
	86
9f56b126 FJ	87	if (tile->fence &&
9f56b126 FJ	88	!nouveau_fence_signalled(tile->fence, NULL))
a0af9add FJ	89	/* Pending tile region. */
	90	continue;
	91
9f56b126 FJ	92	if (max(tile->addr, addr) <
9f56b126 FJ	93	min(tile->addr + tile->size, addr + size))
a0af9add FJ	94	/* Kill an intersecting tile region. */
	95	nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
	96
	97	if (pitch && !found) {
	98	/* Free tile region. */
	99	nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
9f56b126	100	found = tile;
a0af9add FJ	101	}
	102	}
	103
9f56b126	104	spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
a0af9add FJ	105
	106	return found;
	107	}
	108
	109	void
	110	nv10_mem_expire_tiling(struct drm_device dev, struct nouveau_tile_reg tile,
	111	struct nouveau_fence *fence)
	112	{
	113	if (fence) {
	114	/* Mark it as pending. */
	115	tile->fence = fence;
	116	nouveau_fence_ref(fence);
	117	}
	118
	119	tile->used = false;
	120	}
	121
6ee73861 BS	122	/*
	123	* NV50 VM helpers
	124	*/
	125	int
	126	nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
	127	uint32_t flags, uint64_t phys)
	128	{
	129	struct drm_nouveau_private *dev_priv = dev->dev_private;
531e7713 BS	130	struct nouveau_gpuobj *pgt;
	131	unsigned block;
	132	int i;
6ee73861	133
531e7713 BS	134	virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
531e7713 BS	135	size = (size >> 16) << 1;
6c429667 BS	136
	137	phys \|= ((uint64_t)flags << 32);
	138	phys \|= 1;
	139	if (dev_priv->vram_sys_base) {
	140	phys += dev_priv->vram_sys_base;
	141	phys \|= 0x30;
	142	}
6ee73861	143
531e7713 BS	144	while (size) {
531e7713 BS	145	unsigned offset_h = upper_32_bits(phys);
4c27bd33	146	unsigned offset_l = lower_32_bits(phys);
531e7713 BS	147	unsigned pte, end;
	148
	149	for (i = 7; i >= 0; i--) {
	150	block = 1 << (i + 1);
	151	if (size >= block && !(virt & (block - 1)))
	152	break;
	153	}
	154	offset_l \|= (i << 7);
6ee73861	155
531e7713 BS	156	phys += block << 15;
531e7713 BS	157	size -= block;
6ee73861	158
531e7713 BS	159	while (block) {
	160	pgt = dev_priv->vm_vram_pt[virt >> 14];
	161	pte = virt & 0x3ffe;
	162
	163	end = pte + block;
	164	if (end > 16384)
	165	end = 16384;
	166	block -= (end - pte);
	167	virt += (end - pte);
	168
	169	while (pte < end) {
b3beb167 BS	170	nv_wo32(pgt, (pte * 4) + 0, offset_l);
	171	nv_wo32(pgt, (pte * 4) + 4, offset_h);
	172	pte += 2;
531e7713 BS	173	}
531e7713 BS	174	}
6ee73861	175	}
f56cb86f	176	dev_priv->engine.instmem.flush(dev);
6ee73861	177
63187215 BS	178	nv50_vm_flush(dev, 5);
	179	nv50_vm_flush(dev, 0);
	180	nv50_vm_flush(dev, 4);
	181	nv50_vm_flush(dev, 6);
6ee73861 BS	182	return 0;
	183	}
	184
	185	void
	186	nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
	187	{
4c27bd33 BS	188	struct drm_nouveau_private *dev_priv = dev->dev_private;
	189	struct nouveau_gpuobj *pgt;
	190	unsigned pages, pte, end;
	191
	192	virt -= dev_priv->vm_vram_base;
	193	pages = (size >> 16) << 1;
	194
4c27bd33 BS	195	while (pages) {
	196	pgt = dev_priv->vm_vram_pt[virt >> 29];
	197	pte = (virt & 0x1ffe0000ULL) >> 15;
	198
	199	end = pte + pages;
	200	if (end > 16384)
	201	end = 16384;
	202	pages -= (end - pte);
	203	virt += (end - pte) << 15;
	204
b3beb167 BS	205	while (pte < end) {
	206	nv_wo32(pgt, (pte * 4), 0);
	207	pte++;
	208	}
4c27bd33	209	}
f56cb86f	210	dev_priv->engine.instmem.flush(dev);
4c27bd33	211
63187215 BS	212	nv50_vm_flush(dev, 5);
	213	nv50_vm_flush(dev, 0);
	214	nv50_vm_flush(dev, 4);
	215	nv50_vm_flush(dev, 6);
6ee73861 BS	216	}
	217
	218	/*
	219	* Cleanup everything
	220	*/
b833ac26	221	void
fbd2895e	222	nouveau_mem_vram_fini(struct drm_device *dev)
6ee73861 BS	223	{
	224	struct drm_nouveau_private *dev_priv = dev->dev_private;
	225
ac8fb975 BS	226	nouveau_bo_unpin(dev_priv->vga_ram);
	227	nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	228
6ee73861 BS	229	ttm_bo_device_release(&dev_priv->ttm.bdev);
	230
	231	nouveau_ttm_global_release(dev_priv);
	232
fbd2895e BS	233	if (dev_priv->fb_mtrr >= 0) {
	234	drm_mtrr_del(dev_priv->fb_mtrr,
	235	pci_resource_start(dev->pdev, 1),
	236	pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
	237	dev_priv->fb_mtrr = -1;
	238	}
	239	}
	240
	241	void
	242	nouveau_mem_gart_fini(struct drm_device *dev)
	243	{
	244	nouveau_sgdma_takedown(dev);
	245
cd0b072f	246	if (drm_core_has_AGP(dev) && dev->agp) {
6ee73861 BS	247	struct drm_agp_mem entry, tempe;
	248
	249	/* Remove AGP resources, but leave dev->agp
	250	intact until drv_cleanup is called. */
	251	list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
	252	if (entry->bound)
	253	drm_unbind_agp(entry->memory);
	254	drm_free_agp(entry->memory, entry->pages);
	255	kfree(entry);
	256	}
	257	INIT_LIST_HEAD(&dev->agp->memory);
	258
	259	if (dev->agp->acquired)
	260	drm_agp_release(dev);
	261
	262	dev->agp->acquired = 0;
	263	dev->agp->enabled = 0;
	264	}
6ee73861 BS	265	}
6ee73861 BS	266
6ee73861	267	static uint32_t
a76fb4e8 BS	268	nouveau_mem_detect_nv04(struct drm_device *dev)
a76fb4e8 BS	269	{
3c7066bc	270	uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
a76fb4e8 BS	271
	272	if (boot0 & 0x00000100)
	273	return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
	274
3c7066bc FJ	275	switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
3c7066bc FJ	276	case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
a76fb4e8	277	return 32 * 1024 * 1024;
3c7066bc	278	case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
a76fb4e8	279	return 16 * 1024 * 1024;
3c7066bc	280	case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
a76fb4e8	281	return 8 * 1024 * 1024;
3c7066bc	282	case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
a76fb4e8 BS	283	return 4 * 1024 * 1024;
	284	}
	285
	286	return 0;
	287	}
	288
	289	static uint32_t
	290	nouveau_mem_detect_nforce(struct drm_device *dev)
6ee73861 BS	291	{
	292	struct drm_nouveau_private *dev_priv = dev->dev_private;
	293	struct pci_dev *bridge;
	294	uint32_t mem;
	295
	296	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	297	if (!bridge) {
	298	NV_ERROR(dev, "no bridge device\n");
	299	return 0;
	300	}
	301
a76fb4e8	302	if (dev_priv->flags & NV_NFORCE) {
6ee73861 BS	303	pci_read_config_dword(bridge, 0x7C, &mem);
	304	return (uint64_t)(((mem >> 6) & 31) + 1)10241024;
	305	} else
a76fb4e8	306	if (dev_priv->flags & NV_NFORCE2) {
6ee73861 BS	307	pci_read_config_dword(bridge, 0x84, &mem);
	308	return (uint64_t)(((mem >> 4) & 127) + 1)10241024;
	309	}
	310
	311	NV_ERROR(dev, "impossible!\n");
	312	return 0;
	313	}
	314
6c3d7ef2 BS	315	static void
	316	nv50_vram_preinit(struct drm_device *dev)
	317	{
	318	struct drm_nouveau_private *dev_priv = dev->dev_private;
	319	int i, parts, colbits, rowbitsa, rowbitsb, banks;
	320	u64 rowsize, predicted;
	321	u32 r0, r4, rt, ru;
	322
	323	r0 = nv_rd32(dev, 0x100200);
	324	r4 = nv_rd32(dev, 0x100204);
	325	rt = nv_rd32(dev, 0x100250);
	326	ru = nv_rd32(dev, 0x001540);
	327	NV_DEBUG(dev, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n", r0, r4, rt, ru);
	328
	329	for (i = 0, parts = 0; i < 8; i++) {
	330	if (ru & (0x00010000 << i))
	331	parts++;
	332	}
	333
	334	colbits = (r4 & 0x0000f000) >> 12;
	335	rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
	336	rowbitsb = ((r4 & 0x00f00000) >> 20) + 8;
	337	banks = ((r4 & 0x01000000) ? 8 : 4);
	338
	339	rowsize = parts * banks * (1 << colbits) * 8;
	340	predicted = rowsize << rowbitsa;
	341	if (r0 & 0x00000004)
	342	predicted += rowsize << rowbitsb;
	343
	344	if (predicted != dev_priv->vram_size) {
	345	NV_WARN(dev, "memory controller reports %dMiB VRAM\n",
	346	(u32)(dev_priv->vram_size >> 20));
	347	NV_WARN(dev, "we calculated %dMiB VRAM\n",
	348	(u32)(predicted >> 20));
	349	}
	350
	351	dev_priv->vram_rblock_size = rowsize >> 12;
	352	if (rt & 1)
	353	dev_priv->vram_rblock_size *= 3;
	354
	355	NV_DEBUG(dev, "rblock %lld bytes\n",
	356	(u64)dev_priv->vram_rblock_size << 12);
	357	}
	358
	359	static void
	360	nvaa_vram_preinit(struct drm_device *dev)
	361	{
	362	struct drm_nouveau_private *dev_priv = dev->dev_private;
	363
	364	/* To our knowledge, there's no large scale reordering of pages
	365	* that occurs on IGP chipsets.
	366	*/
	367	dev_priv->vram_rblock_size = 1;
	368	}
	369
fbd2895e	370	static int
a76fb4e8	371	nouveau_mem_detect(struct drm_device *dev)
6ee73861 BS	372	{
6ee73861 BS	373	struct drm_nouveau_private *dev_priv = dev->dev_private;
a76fb4e8 BS	374
	375	if (dev_priv->card_type == NV_04) {
	376	dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
	377	} else
	378	if (dev_priv->flags & (NV_NFORCE \| NV_NFORCE2)) {
	379	dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
7a2e4e03 BS	380	} else
7a2e4e03 BS	381	if (dev_priv->card_type < NV_50) {
3c7066bc FJ	382	dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
3c7066bc FJ	383	dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
c556d989 BS	384	} else
c556d989 BS	385	if (dev_priv->card_type < NV_C0) {
3c7066bc	386	dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
7a2e4e03	387	dev_priv->vram_size \|= (dev_priv->vram_size & 0xff) << 32;
6e86e041	388	dev_priv->vram_size &= 0xffffffff00ll;
6c3d7ef2 BS	389
	390	switch (dev_priv->chipset) {
	391	case 0xaa:
	392	case 0xac:
	393	case 0xaf:
8b281db5 BS	394	dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
8b281db5 BS	395	dev_priv->vram_sys_base <<= 12;
6c3d7ef2 BS	396	nvaa_vram_preinit(dev);
	397	break;
	398	default:
	399	nv50_vram_preinit(dev);
	400	break;
fb4f5621	401	}
c556d989 BS	402	} else {
	403	dev_priv->vram_size = nv_rd32(dev, 0x10f20c) << 20;
	404	dev_priv->vram_size *= nv_rd32(dev, 0x121c74);
6ee73861 BS	405	}
6ee73861 BS	406
a76fb4e8 BS	407	NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
	408	if (dev_priv->vram_sys_base) {
	409	NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
	410	dev_priv->vram_sys_base);
	411	}
	412
	413	if (dev_priv->vram_size)
	414	return 0;
	415	return -ENOMEM;
6ee73861 BS	416	}
6ee73861 BS	417
71d06186 FJ	418	#if __OS_HAS_AGP
	419	static unsigned long
	420	get_agp_mode(struct drm_device *dev, unsigned long mode)
	421	{
	422	struct drm_nouveau_private *dev_priv = dev->dev_private;
	423
	424	/*
	425	* FW seems to be broken on nv18, it makes the card lock up
	426	* randomly.
	427	*/
	428	if (dev_priv->chipset == 0x18)
	429	mode &= ~PCI_AGP_COMMAND_FW;
	430
de5899bd FJ	431	/*
	432	* AGP mode set in the command line.
	433	*/
	434	if (nouveau_agpmode > 0) {
	435	bool agpv3 = mode & 0x8;
	436	int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
	437
	438	mode = (mode & ~0x7) \| (rate & 0x7);
	439	}
	440
71d06186 FJ	441	return mode;
	442	}
	443	#endif
	444
e04d8e82 FJ	445	int
e04d8e82 FJ	446	nouveau_mem_reset_agp(struct drm_device *dev)
6ee73861	447	{
e04d8e82 FJ	448	#if __OS_HAS_AGP
	449	uint32_t saved_pci_nv_1, pmc_enable;
	450	int ret;
	451
	452	/* First of all, disable fast writes, otherwise if it's
	453	* already enabled in the AGP bridge and we disable the card's
	454	* AGP controller we might be locking ourselves out of it. */
316f60a1 FJ	455	if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) \|
316f60a1 FJ	456	dev->agp->mode) & PCI_AGP_COMMAND_FW) {
e04d8e82 FJ	457	struct drm_agp_info info;
	458	struct drm_agp_mode mode;
	459
	460	ret = drm_agp_info(dev, &info);
	461	if (ret)
	462	return ret;
	463
71d06186	464	mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
e04d8e82 FJ	465	ret = drm_agp_enable(dev, mode);
	466	if (ret)
	467	return ret;
	468	}
6ee73861 BS	469
6ee73861 BS	470	saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
6ee73861 BS	471
	472	/* clear busmaster bit */
	473	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
e04d8e82 FJ	474	/* disable AGP */
e04d8e82 FJ	475	nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
6ee73861 BS	476
	477	/* power cycle pgraph, if enabled */
	478	pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
	479	if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
	480	nv_wr32(dev, NV03_PMC_ENABLE,
	481	pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
	482	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \|
	483	NV_PMC_ENABLE_PGRAPH);
	484	}
	485
	486	/* and restore (gives effect of resetting AGP) */
6ee73861	487	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
b694dfb2	488	#endif
6ee73861	489
e04d8e82 FJ	490	return 0;
	491	}
	492
6ee73861 BS	493	int
	494	nouveau_mem_init_agp(struct drm_device *dev)
	495	{
b694dfb2	496	#if __OS_HAS_AGP
6ee73861 BS	497	struct drm_nouveau_private *dev_priv = dev->dev_private;
	498	struct drm_agp_info info;
	499	struct drm_agp_mode mode;
	500	int ret;
	501
6ee73861 BS	502	if (!dev->agp->acquired) {
	503	ret = drm_agp_acquire(dev);
	504	if (ret) {
	505	NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
	506	return ret;
	507	}
	508	}
	509
2b495268 FJ	510	nouveau_mem_reset_agp(dev);
2b495268 FJ	511
6ee73861 BS	512	ret = drm_agp_info(dev, &info);
	513	if (ret) {
	514	NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
	515	return ret;
	516	}
	517
	518	/* see agp.h for the AGPSTAT_* modes available */
71d06186	519	mode.mode = get_agp_mode(dev, info.mode);
6ee73861 BS	520	ret = drm_agp_enable(dev, mode);
	521	if (ret) {
	522	NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
	523	return ret;
	524	}
	525
	526	dev_priv->gart_info.type = NOUVEAU_GART_AGP;
	527	dev_priv->gart_info.aper_base = info.aperture_base;
	528	dev_priv->gart_info.aper_size = info.aperture_size;
b694dfb2	529	#endif
6ee73861 BS	530	return 0;
	531	}
	532
	533	int
fbd2895e	534	nouveau_mem_vram_init(struct drm_device *dev)
6ee73861 BS	535	{
	536	struct drm_nouveau_private *dev_priv = dev->dev_private;
	537	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
fbd2895e	538	int ret, dma_bits;
6ee73861 BS	539
	540	if (dev_priv->card_type >= NV_50 &&
	541	pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
	542	dma_bits = 40;
fbd2895e BS	543	else
fbd2895e BS	544	dma_bits = 32;
6ee73861 BS	545
6ee73861 BS	546	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
fbd2895e	547	if (ret)
6ee73861	548	return ret;
fbd2895e BS	549
	550	ret = nouveau_mem_detect(dev);
	551	if (ret)
	552	return ret;
	553
	554	dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
6ee73861 BS	555
	556	ret = nouveau_ttm_global_init(dev_priv);
	557	if (ret)
	558	return ret;
	559
	560	ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
	561	dev_priv->ttm.bo_global_ref.ref.object,
	562	&nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
	563	dma_bits <= 32 ? true : false);
	564	if (ret) {
	565	NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
	566	return ret;
	567	}
	568
a76fb4e8	569	dev_priv->fb_available_size = dev_priv->vram_size;
6ee73861	570	dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
01d73a69 JC	571	if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
	572	dev_priv->fb_mappable_pages =
	573	pci_resource_len(dev->pdev, 1);
6ee73861 BS	574	dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
6ee73861 BS	575
fbd2895e BS	576	/* reserve space at end of VRAM for PRAMIN */
	577	if (dev_priv->chipset == 0x40 \|\| dev_priv->chipset == 0x47 \|\|
	578	dev_priv->chipset == 0x49 \|\| dev_priv->chipset == 0x4b)
	579	dev_priv->ramin_rsvd_vram = (2 * 1024 * 1024);
	580	else
	581	if (dev_priv->card_type >= NV_40)
	582	dev_priv->ramin_rsvd_vram = (1 * 1024 * 1024);
	583	else
	584	dev_priv->ramin_rsvd_vram = (512 * 1024);
	585
6ee73861 BS	586	dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
	587	dev_priv->fb_aper_free = dev_priv->fb_available_size;
	588
	589	/* mappable vram */
	590	ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
	591	dev_priv->fb_available_size >> PAGE_SHIFT);
	592	if (ret) {
	593	NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
	594	return ret;
	595	}
	596
ac8fb975 BS	597	ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
	598	0, 0, true, true, &dev_priv->vga_ram);
	599	if (ret == 0)
	600	ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
	601	if (ret) {
	602	NV_WARN(dev, "failed to reserve VGA memory\n");
	603	nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	604	}
	605
fbd2895e BS	606	dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
	607	pci_resource_len(dev->pdev, 1),
	608	DRM_MTRR_WC);
	609	return 0;
	610	}
	611
	612	int
	613	nouveau_mem_gart_init(struct drm_device *dev)
	614	{
	615	struct drm_nouveau_private *dev_priv = dev->dev_private;
	616	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	617	int ret;
	618
	619	dev_priv->gart_info.type = NOUVEAU_GART_NONE;
	620
6ee73861	621	#if !defined(__powerpc__) && !defined(__ia64__)
de5899bd	622	if (drm_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
6ee73861 BS	623	ret = nouveau_mem_init_agp(dev);
	624	if (ret)
	625	NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
	626	}
	627	#endif
	628
	629	if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
	630	ret = nouveau_sgdma_init(dev);
	631	if (ret) {
	632	NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
	633	return ret;
	634	}
	635	}
	636
	637	NV_INFO(dev, "%d MiB GART (aperture)\n",
	638	(int)(dev_priv->gart_info.aper_size >> 20));
	639	dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
	640
	641	ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
	642	dev_priv->gart_info.aper_size >> PAGE_SHIFT);
	643	if (ret) {
	644	NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
	645	return ret;
	646	}
	647
6ee73861 BS	648	return 0;
	649	}
	650