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6ee73861 BS |
1 | /* |
2 | * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved. | |
3 | * Copyright 2005 Stephane Marchesin | |
4 | * | |
5 | * The Weather Channel (TM) funded Tungsten Graphics to develop the | |
6 | * initial release of the Radeon 8500 driver under the XFree86 license. | |
7 | * This notice must be preserved. | |
8 | * | |
9 | * Permission is hereby granted, free of charge, to any person obtaining a | |
10 | * copy of this software and associated documentation files (the "Software"), | |
11 | * to deal in the Software without restriction, including without limitation | |
12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
13 | * and/or sell copies of the Software, and to permit persons to whom the | |
14 | * Software is furnished to do so, subject to the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the next | |
17 | * paragraph) shall be included in all copies or substantial portions of the | |
18 | * Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
21 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
22 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
23 | * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
24 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
25 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
26 | * DEALINGS IN THE SOFTWARE. | |
27 | * | |
28 | * Authors: | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "drm_sarea.h" | |
36 | #include "nouveau_drv.h" | |
37 | ||
a0af9add FJ |
38 | /* |
39 | * NV10-NV40 tiling helpers | |
40 | */ | |
41 | ||
42 | static void | |
43 | nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, | |
44 | uint32_t size, uint32_t pitch) | |
45 | { | |
46 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
47 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; | |
48 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; | |
49 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | |
50 | struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i]; | |
51 | ||
52 | tile->addr = addr; | |
53 | tile->size = size; | |
54 | tile->used = !!pitch; | |
55 | nouveau_fence_unref((void **)&tile->fence); | |
56 | ||
57 | if (!pfifo->cache_flush(dev)) | |
58 | return; | |
59 | ||
60 | pfifo->reassign(dev, false); | |
61 | pfifo->cache_flush(dev); | |
62 | pfifo->cache_pull(dev, false); | |
63 | ||
64 | nouveau_wait_for_idle(dev); | |
65 | ||
66 | pgraph->set_region_tiling(dev, i, addr, size, pitch); | |
67 | pfb->set_region_tiling(dev, i, addr, size, pitch); | |
68 | ||
69 | pfifo->cache_pull(dev, true); | |
70 | pfifo->reassign(dev, true); | |
71 | } | |
72 | ||
73 | struct nouveau_tile_reg * | |
74 | nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size, | |
75 | uint32_t pitch) | |
76 | { | |
77 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
78 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; | |
79 | struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL; | |
80 | int i; | |
81 | ||
82 | spin_lock(&dev_priv->tile.lock); | |
83 | ||
84 | for (i = 0; i < pfb->num_tiles; i++) { | |
85 | if (tile[i].used) | |
86 | /* Tile region in use. */ | |
87 | continue; | |
88 | ||
89 | if (tile[i].fence && | |
90 | !nouveau_fence_signalled(tile[i].fence, NULL)) | |
91 | /* Pending tile region. */ | |
92 | continue; | |
93 | ||
94 | if (max(tile[i].addr, addr) < | |
95 | min(tile[i].addr + tile[i].size, addr + size)) | |
96 | /* Kill an intersecting tile region. */ | |
97 | nv10_mem_set_region_tiling(dev, i, 0, 0, 0); | |
98 | ||
99 | if (pitch && !found) { | |
100 | /* Free tile region. */ | |
101 | nv10_mem_set_region_tiling(dev, i, addr, size, pitch); | |
102 | found = &tile[i]; | |
103 | } | |
104 | } | |
105 | ||
106 | spin_unlock(&dev_priv->tile.lock); | |
107 | ||
108 | return found; | |
109 | } | |
110 | ||
111 | void | |
112 | nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile, | |
113 | struct nouveau_fence *fence) | |
114 | { | |
115 | if (fence) { | |
116 | /* Mark it as pending. */ | |
117 | tile->fence = fence; | |
118 | nouveau_fence_ref(fence); | |
119 | } | |
120 | ||
121 | tile->used = false; | |
122 | } | |
123 | ||
6ee73861 BS |
124 | /* |
125 | * NV50 VM helpers | |
126 | */ | |
127 | int | |
128 | nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size, | |
129 | uint32_t flags, uint64_t phys) | |
130 | { | |
131 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
531e7713 BS |
132 | struct nouveau_gpuobj *pgt; |
133 | unsigned block; | |
134 | int i; | |
6ee73861 | 135 | |
531e7713 BS |
136 | virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1; |
137 | size = (size >> 16) << 1; | |
6c429667 BS |
138 | |
139 | phys |= ((uint64_t)flags << 32); | |
140 | phys |= 1; | |
141 | if (dev_priv->vram_sys_base) { | |
142 | phys += dev_priv->vram_sys_base; | |
143 | phys |= 0x30; | |
144 | } | |
6ee73861 | 145 | |
531e7713 BS |
146 | while (size) { |
147 | unsigned offset_h = upper_32_bits(phys); | |
4c27bd33 | 148 | unsigned offset_l = lower_32_bits(phys); |
531e7713 BS |
149 | unsigned pte, end; |
150 | ||
151 | for (i = 7; i >= 0; i--) { | |
152 | block = 1 << (i + 1); | |
153 | if (size >= block && !(virt & (block - 1))) | |
154 | break; | |
155 | } | |
156 | offset_l |= (i << 7); | |
6ee73861 | 157 | |
531e7713 BS |
158 | phys += block << 15; |
159 | size -= block; | |
6ee73861 | 160 | |
531e7713 BS |
161 | while (block) { |
162 | pgt = dev_priv->vm_vram_pt[virt >> 14]; | |
163 | pte = virt & 0x3ffe; | |
164 | ||
165 | end = pte + block; | |
166 | if (end > 16384) | |
167 | end = 16384; | |
168 | block -= (end - pte); | |
169 | virt += (end - pte); | |
170 | ||
171 | while (pte < end) { | |
172 | nv_wo32(dev, pgt, pte++, offset_l); | |
173 | nv_wo32(dev, pgt, pte++, offset_h); | |
174 | } | |
175 | } | |
6ee73861 | 176 | } |
f56cb86f | 177 | dev_priv->engine.instmem.flush(dev); |
6ee73861 | 178 | |
63187215 BS |
179 | nv50_vm_flush(dev, 5); |
180 | nv50_vm_flush(dev, 0); | |
181 | nv50_vm_flush(dev, 4); | |
182 | nv50_vm_flush(dev, 6); | |
6ee73861 BS |
183 | return 0; |
184 | } | |
185 | ||
186 | void | |
187 | nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size) | |
188 | { | |
4c27bd33 BS |
189 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
190 | struct nouveau_gpuobj *pgt; | |
191 | unsigned pages, pte, end; | |
192 | ||
193 | virt -= dev_priv->vm_vram_base; | |
194 | pages = (size >> 16) << 1; | |
195 | ||
4c27bd33 BS |
196 | while (pages) { |
197 | pgt = dev_priv->vm_vram_pt[virt >> 29]; | |
198 | pte = (virt & 0x1ffe0000ULL) >> 15; | |
199 | ||
200 | end = pte + pages; | |
201 | if (end > 16384) | |
202 | end = 16384; | |
203 | pages -= (end - pte); | |
204 | virt += (end - pte) << 15; | |
205 | ||
206 | while (pte < end) | |
207 | nv_wo32(dev, pgt, pte++, 0); | |
208 | } | |
f56cb86f | 209 | dev_priv->engine.instmem.flush(dev); |
4c27bd33 | 210 | |
63187215 BS |
211 | nv50_vm_flush(dev, 5); |
212 | nv50_vm_flush(dev, 0); | |
213 | nv50_vm_flush(dev, 4); | |
214 | nv50_vm_flush(dev, 6); | |
6ee73861 BS |
215 | } |
216 | ||
217 | /* | |
218 | * Cleanup everything | |
219 | */ | |
b833ac26 BS |
220 | void |
221 | nouveau_mem_close(struct drm_device *dev) | |
6ee73861 BS |
222 | { |
223 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
224 | ||
ac8fb975 BS |
225 | nouveau_bo_unpin(dev_priv->vga_ram); |
226 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
227 | ||
6ee73861 BS |
228 | ttm_bo_device_release(&dev_priv->ttm.bdev); |
229 | ||
230 | nouveau_ttm_global_release(dev_priv); | |
231 | ||
cd0b072f | 232 | if (drm_core_has_AGP(dev) && dev->agp) { |
6ee73861 BS |
233 | struct drm_agp_mem *entry, *tempe; |
234 | ||
235 | /* Remove AGP resources, but leave dev->agp | |
236 | intact until drv_cleanup is called. */ | |
237 | list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) { | |
238 | if (entry->bound) | |
239 | drm_unbind_agp(entry->memory); | |
240 | drm_free_agp(entry->memory, entry->pages); | |
241 | kfree(entry); | |
242 | } | |
243 | INIT_LIST_HEAD(&dev->agp->memory); | |
244 | ||
245 | if (dev->agp->acquired) | |
246 | drm_agp_release(dev); | |
247 | ||
248 | dev->agp->acquired = 0; | |
249 | dev->agp->enabled = 0; | |
250 | } | |
251 | ||
252 | if (dev_priv->fb_mtrr) { | |
01d73a69 JC |
253 | drm_mtrr_del(dev_priv->fb_mtrr, |
254 | pci_resource_start(dev->pdev, 1), | |
255 | pci_resource_len(dev->pdev, 1), DRM_MTRR_WC); | |
baf8035e | 256 | dev_priv->fb_mtrr = -1; |
6ee73861 BS |
257 | } |
258 | } | |
259 | ||
6ee73861 | 260 | static uint32_t |
a76fb4e8 BS |
261 | nouveau_mem_detect_nv04(struct drm_device *dev) |
262 | { | |
3c7066bc | 263 | uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0); |
a76fb4e8 BS |
264 | |
265 | if (boot0 & 0x00000100) | |
266 | return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024; | |
267 | ||
3c7066bc FJ |
268 | switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) { |
269 | case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB: | |
a76fb4e8 | 270 | return 32 * 1024 * 1024; |
3c7066bc | 271 | case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB: |
a76fb4e8 | 272 | return 16 * 1024 * 1024; |
3c7066bc | 273 | case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB: |
a76fb4e8 | 274 | return 8 * 1024 * 1024; |
3c7066bc | 275 | case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB: |
a76fb4e8 BS |
276 | return 4 * 1024 * 1024; |
277 | } | |
278 | ||
279 | return 0; | |
280 | } | |
281 | ||
282 | static uint32_t | |
283 | nouveau_mem_detect_nforce(struct drm_device *dev) | |
6ee73861 BS |
284 | { |
285 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
286 | struct pci_dev *bridge; | |
287 | uint32_t mem; | |
288 | ||
289 | bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1)); | |
290 | if (!bridge) { | |
291 | NV_ERROR(dev, "no bridge device\n"); | |
292 | return 0; | |
293 | } | |
294 | ||
a76fb4e8 | 295 | if (dev_priv->flags & NV_NFORCE) { |
6ee73861 BS |
296 | pci_read_config_dword(bridge, 0x7C, &mem); |
297 | return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024; | |
298 | } else | |
a76fb4e8 | 299 | if (dev_priv->flags & NV_NFORCE2) { |
6ee73861 BS |
300 | pci_read_config_dword(bridge, 0x84, &mem); |
301 | return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024; | |
302 | } | |
303 | ||
304 | NV_ERROR(dev, "impossible!\n"); | |
305 | return 0; | |
306 | } | |
307 | ||
308 | /* returns the amount of FB ram in bytes */ | |
a76fb4e8 BS |
309 | int |
310 | nouveau_mem_detect(struct drm_device *dev) | |
6ee73861 BS |
311 | { |
312 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a76fb4e8 BS |
313 | |
314 | if (dev_priv->card_type == NV_04) { | |
315 | dev_priv->vram_size = nouveau_mem_detect_nv04(dev); | |
316 | } else | |
317 | if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) { | |
318 | dev_priv->vram_size = nouveau_mem_detect_nforce(dev); | |
7a2e4e03 BS |
319 | } else |
320 | if (dev_priv->card_type < NV_50) { | |
3c7066bc FJ |
321 | dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); |
322 | dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK; | |
7a2e4e03 | 323 | } else { |
3c7066bc | 324 | dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA); |
7a2e4e03 | 325 | dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32; |
6e86e041 | 326 | dev_priv->vram_size &= 0xffffffff00ll; |
fb4f5621 | 327 | if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) { |
8b281db5 BS |
328 | dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10); |
329 | dev_priv->vram_sys_base <<= 12; | |
fb4f5621 | 330 | } |
6ee73861 BS |
331 | } |
332 | ||
a76fb4e8 BS |
333 | NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20)); |
334 | if (dev_priv->vram_sys_base) { | |
335 | NV_INFO(dev, "Stolen system memory at: 0x%010llx\n", | |
336 | dev_priv->vram_sys_base); | |
337 | } | |
338 | ||
339 | if (dev_priv->vram_size) | |
340 | return 0; | |
341 | return -ENOMEM; | |
6ee73861 BS |
342 | } |
343 | ||
b694dfb2 | 344 | #if __OS_HAS_AGP |
6ee73861 BS |
345 | static void nouveau_mem_reset_agp(struct drm_device *dev) |
346 | { | |
347 | uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable; | |
348 | ||
349 | saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1); | |
350 | saved_pci_nv_19 = nv_rd32(dev, NV04_PBUS_PCI_NV_19); | |
351 | ||
352 | /* clear busmaster bit */ | |
353 | nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4); | |
354 | /* clear SBA and AGP bits */ | |
355 | nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff); | |
356 | ||
357 | /* power cycle pgraph, if enabled */ | |
358 | pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE); | |
359 | if (pmc_enable & NV_PMC_ENABLE_PGRAPH) { | |
360 | nv_wr32(dev, NV03_PMC_ENABLE, | |
361 | pmc_enable & ~NV_PMC_ENABLE_PGRAPH); | |
362 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | | |
363 | NV_PMC_ENABLE_PGRAPH); | |
364 | } | |
365 | ||
366 | /* and restore (gives effect of resetting AGP) */ | |
367 | nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19); | |
368 | nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1); | |
369 | } | |
b694dfb2 | 370 | #endif |
6ee73861 BS |
371 | |
372 | int | |
373 | nouveau_mem_init_agp(struct drm_device *dev) | |
374 | { | |
b694dfb2 | 375 | #if __OS_HAS_AGP |
6ee73861 BS |
376 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
377 | struct drm_agp_info info; | |
378 | struct drm_agp_mode mode; | |
379 | int ret; | |
380 | ||
381 | if (nouveau_noagp) | |
382 | return 0; | |
383 | ||
384 | nouveau_mem_reset_agp(dev); | |
385 | ||
386 | if (!dev->agp->acquired) { | |
387 | ret = drm_agp_acquire(dev); | |
388 | if (ret) { | |
389 | NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret); | |
390 | return ret; | |
391 | } | |
392 | } | |
393 | ||
394 | ret = drm_agp_info(dev, &info); | |
395 | if (ret) { | |
396 | NV_ERROR(dev, "Unable to get AGP info: %d\n", ret); | |
397 | return ret; | |
398 | } | |
399 | ||
400 | /* see agp.h for the AGPSTAT_* modes available */ | |
401 | mode.mode = info.mode; | |
402 | ret = drm_agp_enable(dev, mode); | |
403 | if (ret) { | |
404 | NV_ERROR(dev, "Unable to enable AGP: %d\n", ret); | |
405 | return ret; | |
406 | } | |
407 | ||
408 | dev_priv->gart_info.type = NOUVEAU_GART_AGP; | |
409 | dev_priv->gart_info.aper_base = info.aperture_base; | |
410 | dev_priv->gart_info.aper_size = info.aperture_size; | |
b694dfb2 | 411 | #endif |
6ee73861 BS |
412 | return 0; |
413 | } | |
414 | ||
415 | int | |
416 | nouveau_mem_init(struct drm_device *dev) | |
417 | { | |
418 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
419 | struct ttm_bo_device *bdev = &dev_priv->ttm.bdev; | |
420 | int ret, dma_bits = 32; | |
421 | ||
01d73a69 | 422 | dev_priv->fb_phys = pci_resource_start(dev->pdev, 1); |
6ee73861 BS |
423 | dev_priv->gart_info.type = NOUVEAU_GART_NONE; |
424 | ||
425 | if (dev_priv->card_type >= NV_50 && | |
426 | pci_dma_supported(dev->pdev, DMA_BIT_MASK(40))) | |
427 | dma_bits = 40; | |
428 | ||
429 | ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits)); | |
430 | if (ret) { | |
431 | NV_ERROR(dev, "Error setting DMA mask: %d\n", ret); | |
432 | return ret; | |
433 | } | |
434 | ||
435 | ret = nouveau_ttm_global_init(dev_priv); | |
436 | if (ret) | |
437 | return ret; | |
438 | ||
439 | ret = ttm_bo_device_init(&dev_priv->ttm.bdev, | |
440 | dev_priv->ttm.bo_global_ref.ref.object, | |
441 | &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET, | |
442 | dma_bits <= 32 ? true : false); | |
443 | if (ret) { | |
444 | NV_ERROR(dev, "Error initialising bo driver: %d\n", ret); | |
445 | return ret; | |
446 | } | |
447 | ||
448 | INIT_LIST_HEAD(&dev_priv->ttm.bo_list); | |
449 | spin_lock_init(&dev_priv->ttm.bo_list_lock); | |
a0af9add | 450 | spin_lock_init(&dev_priv->tile.lock); |
6ee73861 | 451 | |
a76fb4e8 | 452 | dev_priv->fb_available_size = dev_priv->vram_size; |
6ee73861 | 453 | dev_priv->fb_mappable_pages = dev_priv->fb_available_size; |
01d73a69 JC |
454 | if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1)) |
455 | dev_priv->fb_mappable_pages = | |
456 | pci_resource_len(dev->pdev, 1); | |
6ee73861 BS |
457 | dev_priv->fb_mappable_pages >>= PAGE_SHIFT; |
458 | ||
6ee73861 BS |
459 | /* remove reserved space at end of vram from available amount */ |
460 | dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram; | |
461 | dev_priv->fb_aper_free = dev_priv->fb_available_size; | |
462 | ||
463 | /* mappable vram */ | |
464 | ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM, | |
465 | dev_priv->fb_available_size >> PAGE_SHIFT); | |
466 | if (ret) { | |
467 | NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret); | |
468 | return ret; | |
469 | } | |
470 | ||
ac8fb975 BS |
471 | ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM, |
472 | 0, 0, true, true, &dev_priv->vga_ram); | |
473 | if (ret == 0) | |
474 | ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM); | |
475 | if (ret) { | |
476 | NV_WARN(dev, "failed to reserve VGA memory\n"); | |
477 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
478 | } | |
479 | ||
6ee73861 BS |
480 | /* GART */ |
481 | #if !defined(__powerpc__) && !defined(__ia64__) | |
482 | if (drm_device_is_agp(dev) && dev->agp) { | |
483 | ret = nouveau_mem_init_agp(dev); | |
484 | if (ret) | |
485 | NV_ERROR(dev, "Error initialising AGP: %d\n", ret); | |
486 | } | |
487 | #endif | |
488 | ||
489 | if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) { | |
490 | ret = nouveau_sgdma_init(dev); | |
491 | if (ret) { | |
492 | NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret); | |
493 | return ret; | |
494 | } | |
495 | } | |
496 | ||
497 | NV_INFO(dev, "%d MiB GART (aperture)\n", | |
498 | (int)(dev_priv->gart_info.aper_size >> 20)); | |
499 | dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size; | |
500 | ||
501 | ret = ttm_bo_init_mm(bdev, TTM_PL_TT, | |
502 | dev_priv->gart_info.aper_size >> PAGE_SHIFT); | |
503 | if (ret) { | |
504 | NV_ERROR(dev, "Failed TT mm init: %d\n", ret); | |
505 | return ret; | |
506 | } | |
507 | ||
01d73a69 JC |
508 | dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1), |
509 | pci_resource_len(dev->pdev, 1), | |
6ee73861 | 510 | DRM_MTRR_WC); |
ac8fb975 | 511 | |
6ee73861 BS |
512 | return 0; |
513 | } | |
514 | ||
515 |