[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_mem.c

/*
 * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
 * Copyright 2005 Stephane Marchesin
 *
 * The Weather Channel (TM) funded Tungsten Graphics to develop the
 * initial release of the Radeon 8500 driver under the XFree86 license.
 * This notice must be preserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Whitwell <keith@tungstengraphics.com>
 */


#include "drmP.h"
#include "drm.h"
#include "drm_sarea.h"
#include "nouveau_drv.h"

static struct mem_block *
split_block(struct mem_block *p, uint64_t start, uint64_t size,
	    struct drm_file *file_priv)
{
	/* Maybe cut off the start of an existing block */
	if (start > p->start) {
		struct mem_block *newblock =
			kmalloc(sizeof(*newblock), GFP_KERNEL);
		if (!newblock)
			goto out;
		newblock->start = start;
		newblock->size = p->size - (start - p->start);
		newblock->file_priv = NULL;
		newblock->next = p->next;
		newblock->prev = p;
		p->next->prev = newblock;
		p->next = newblock;
		p->size -= newblock->size;
		p = newblock;
	}

	/* Maybe cut off the end of an existing block */
	if (size < p->size) {
		struct mem_block *newblock =
			kmalloc(sizeof(*newblock), GFP_KERNEL);
		if (!newblock)
			goto out;
		newblock->start = start + size;
		newblock->size = p->size - size;
		newblock->file_priv = NULL;
		newblock->next = p->next;
		newblock->prev = p;
		p->next->prev = newblock;
		p->next = newblock;
		p->size = size;
	}

out:
	/* Our block is in the middle */
	p->file_priv = file_priv;
	return p;
}

struct mem_block *
nouveau_mem_alloc_block(struct mem_block *heap, uint64_t size,
			int align2, struct drm_file *file_priv, int tail)
{
	struct mem_block *p;
	uint64_t mask = (1 << align2) - 1;

	if (!heap)
		return NULL;

	if (tail) {
		list_for_each_prev(p, heap) {
			uint64_t start = ((p->start + p->size) - size) & ~mask;

			if (p->file_priv == NULL && start >= p->start &&
			    start + size <= p->start + p->size)
				return split_block(p, start, size, file_priv);
		}
	} else {
		list_for_each(p, heap) {
			uint64_t start = (p->start + mask) & ~mask;

			if (p->file_priv == NULL &&
			    start + size <= p->start + p->size)
				return split_block(p, start, size, file_priv);
		}
	}

	return NULL;
}

void nouveau_mem_free_block(struct mem_block *p)
{
	p->file_priv = NULL;

	/* Assumes a single contiguous range.  Needs a special file_priv in
	 * 'heap' to stop it being subsumed.
	 */
	if (p->next->file_priv == NULL) {
		struct mem_block *q = p->next;
		p->size += q->size;
		p->next = q->next;
		p->next->prev = p;
		kfree(q);
	}

	if (p->prev->file_priv == NULL) {
		struct mem_block *q = p->prev;
		q->size += p->size;
		q->next = p->next;
		q->next->prev = q;
		kfree(p);
	}
}

/* Initialize.  How to check for an uninitialized heap?
 */
int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start,
			  uint64_t size)
{
	struct mem_block *blocks = kmalloc(sizeof(*blocks), GFP_KERNEL);

	if (!blocks)
		return -ENOMEM;

	*heap = kmalloc(sizeof(**heap), GFP_KERNEL);
	if (!*heap) {
		kfree(blocks);
		return -ENOMEM;
	}

	blocks->start = start;
	blocks->size = size;
	blocks->file_priv = NULL;
	blocks->next = blocks->prev = *heap;

	memset(*heap, 0, sizeof(**heap));
	(*heap)->file_priv = (struct drm_file *) -1;
	(*heap)->next = (*heap)->prev = blocks;
	return 0;
}

/*
 * Free all blocks associated with the releasing file_priv
 */
void nouveau_mem_release(struct drm_file *file_priv, struct mem_block *heap)
{
	struct mem_block *p;

	if (!heap || !heap->next)
		return;

	list_for_each(p, heap) {
		if (p->file_priv == file_priv)
			p->file_priv = NULL;
	}

	/* Assumes a single contiguous range.  Needs a special file_priv in
	 * 'heap' to stop it being subsumed.
	 */
	list_for_each(p, heap) {
		while ((p->file_priv == NULL) &&
					(p->next->file_priv == NULL) &&
					(p->next != heap)) {
			struct mem_block *q = p->next;
			p->size += q->size;
			p->next = q->next;
			p->next->prev = p;
			kfree(q);
		}
	}
}

/*
 * NV10-NV40 tiling helpers
 */

static void
nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
			   uint32_t size, uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];

	tile->addr = addr;
	tile->size = size;
	tile->used = !!pitch;
	nouveau_fence_unref((void **)&tile->fence);

	if (!pfifo->cache_flush(dev))
		return;

	pfifo->reassign(dev, false);
	pfifo->cache_flush(dev);
	pfifo->cache_pull(dev, false);

	nouveau_wait_for_idle(dev);

	pgraph->set_region_tiling(dev, i, addr, size, pitch);
	pfb->set_region_tiling(dev, i, addr, size, pitch);

	pfifo->cache_pull(dev, true);
	pfifo->reassign(dev, true);
}

struct nouveau_tile_reg *
nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
		    uint32_t pitch)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	struct nouveau_tile_reg *tile = dev_priv->tile.reg, *found = NULL;
	int i;

	spin_lock(&dev_priv->tile.lock);

	for (i = 0; i < pfb->num_tiles; i++) {
		if (tile[i].used)
			/* Tile region in use. */
			continue;

		if (tile[i].fence &&
		    !nouveau_fence_signalled(tile[i].fence, NULL))
			/* Pending tile region. */
			continue;

		if (max(tile[i].addr, addr) <
		    min(tile[i].addr + tile[i].size, addr + size))
			/* Kill an intersecting tile region. */
			nv10_mem_set_region_tiling(dev, i, 0, 0, 0);

		if (pitch && !found) {
			/* Free tile region. */
			nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
			found = &tile[i];
		}
	}

	spin_unlock(&dev_priv->tile.lock);

	return found;
}

void
nv10_mem_expire_tiling(struct drm_device *dev, struct nouveau_tile_reg *tile,
		       struct nouveau_fence *fence)
{
	if (fence) {
		/* Mark it as pending. */
		tile->fence = fence;
		nouveau_fence_ref(fence);
	}

	tile->used = false;
}

/*
 * NV50 VM helpers
 */
int
nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
			uint32_t flags, uint64_t phys)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *pgt;
	unsigned block;
	int i;

	virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
	size = (size >> 16) << 1;

	phys |= ((uint64_t)flags << 32);
	phys |= 1;
	if (dev_priv->vram_sys_base) {
		phys += dev_priv->vram_sys_base;
		phys |= 0x30;
	}

	dev_priv->engine.instmem.prepare_access(dev, true);
	while (size) {
		unsigned offset_h = upper_32_bits(phys);
		unsigned offset_l = lower_32_bits(phys);
		unsigned pte, end;

		for (i = 7; i >= 0; i--) {
			block = 1 << (i + 1);
			if (size >= block && !(virt & (block - 1)))
				break;
		}
		offset_l |= (i << 7);

		phys += block << 15;
		size -= block;

		while (block) {
			pgt = dev_priv->vm_vram_pt[virt >> 14];
			pte = virt & 0x3ffe;

			end = pte + block;
			if (end > 16384)
				end = 16384;
			block -= (end - pte);
			virt  += (end - pte);

			while (pte < end) {
				nv_wo32(dev, pgt, pte++, offset_l);
				nv_wo32(dev, pgt, pte++, offset_h);
			}
		}
	}
	dev_priv->engine.instmem.finish_access(dev);

	nv_wr32(dev, 0x100c80, 0x00050001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return -EBUSY;
	}

	nv_wr32(dev, 0x100c80, 0x00000001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return -EBUSY;
	}

	nv_wr32(dev, 0x100c80, 0x00040001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return -EBUSY;
	}

	nv_wr32(dev, 0x100c80, 0x00060001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return -EBUSY;
	}

	return 0;
}

void
nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nouveau_gpuobj *pgt;
	unsigned pages, pte, end;

	virt -= dev_priv->vm_vram_base;
	pages = (size >> 16) << 1;

	dev_priv->engine.instmem.prepare_access(dev, true);
	while (pages) {
		pgt = dev_priv->vm_vram_pt[virt >> 29];
		pte = (virt & 0x1ffe0000ULL) >> 15;

		end = pte + pages;
		if (end > 16384)
			end = 16384;
		pages -= (end - pte);
		virt  += (end - pte) << 15;

		while (pte < end)
			nv_wo32(dev, pgt, pte++, 0);
	}
	dev_priv->engine.instmem.finish_access(dev);

	nv_wr32(dev, 0x100c80, 0x00050001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return;
	}

	nv_wr32(dev, 0x100c80, 0x00000001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return;
	}

	nv_wr32(dev, 0x100c80, 0x00040001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
		return;
	}

	nv_wr32(dev, 0x100c80, 0x00060001);
	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
		NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
		NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	}
}

/*
 * Cleanup everything
 */
void nouveau_mem_takedown(struct mem_block **heap)
{
	struct mem_block *p;

	if (!*heap)
		return;

	for (p = (*heap)->next; p != *heap;) {
		struct mem_block *q = p;
		p = p->next;
		kfree(q);
	}

	kfree(*heap);
	*heap = NULL;
}

void nouveau_mem_close(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	nouveau_bo_unpin(dev_priv->vga_ram);
	nouveau_bo_ref(NULL, &dev_priv->vga_ram);

	ttm_bo_device_release(&dev_priv->ttm.bdev);

	nouveau_ttm_global_release(dev_priv);

	if (drm_core_has_AGP(dev) && dev->agp &&
	    drm_core_check_feature(dev, DRIVER_MODESET)) {
		struct drm_agp_mem *entry, *tempe;

		/* Remove AGP resources, but leave dev->agp
		   intact until drv_cleanup is called. */
		list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
			if (entry->bound)
				drm_unbind_agp(entry->memory);
			drm_free_agp(entry->memory, entry->pages);
			kfree(entry);
		}
		INIT_LIST_HEAD(&dev->agp->memory);

		if (dev->agp->acquired)
			drm_agp_release(dev);

		dev->agp->acquired = 0;
		dev->agp->enabled = 0;
	}

	if (dev_priv->fb_mtrr) {
		drm_mtrr_del(dev_priv->fb_mtrr,
			     pci_resource_start(dev->pdev, 1),
			     pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
		dev_priv->fb_mtrr = 0;
	}
}

static uint32_t
nouveau_mem_detect_nv04(struct drm_device *dev)
{
	uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0);

	if (boot0 & 0x00000100)
		return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;

	switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) {
	case NV04_BOOT_0_RAM_AMOUNT_32MB:
		return 32 * 1024 * 1024;
	case NV04_BOOT_0_RAM_AMOUNT_16MB:
		return 16 * 1024 * 1024;
	case NV04_BOOT_0_RAM_AMOUNT_8MB:
		return 8 * 1024 * 1024;
	case NV04_BOOT_0_RAM_AMOUNT_4MB:
		return 4 * 1024 * 1024;
	}

	return 0;
}

static uint32_t
nouveau_mem_detect_nforce(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct pci_dev *bridge;
	uint32_t mem;

	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	if (!bridge) {
		NV_ERROR(dev, "no bridge device\n");
		return 0;
	}

	if (dev_priv->flags & NV_NFORCE) {
		pci_read_config_dword(bridge, 0x7C, &mem);
		return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
	} else
	if (dev_priv->flags & NV_NFORCE2) {
		pci_read_config_dword(bridge, 0x84, &mem);
		return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
	}

	NV_ERROR(dev, "impossible!\n");
	return 0;
}

/* returns the amount of FB ram in bytes */
int
nouveau_mem_detect(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	if (dev_priv->card_type == NV_04) {
		dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
	} else
	if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
		dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
	} else {
		dev_priv->vram_size  = nv_rd32(dev, NV04_FIFO_DATA);
		dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK;
		if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac)
			dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
			dev_priv->vram_sys_base <<= 12;
	}

	NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
	if (dev_priv->vram_sys_base) {
		NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
			dev_priv->vram_sys_base);
	}

	if (dev_priv->vram_size)
		return 0;
	return -ENOMEM;
}

#if __OS_HAS_AGP
static void nouveau_mem_reset_agp(struct drm_device *dev)
{
	uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable;

	saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
	saved_pci_nv_19 = nv_rd32(dev, NV04_PBUS_PCI_NV_19);

	/* clear busmaster bit */
	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
	/* clear SBA and AGP bits */
	nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff);

	/* power cycle pgraph, if enabled */
	pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
	if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
		nv_wr32(dev, NV03_PMC_ENABLE,
				pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
		nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
				NV_PMC_ENABLE_PGRAPH);
	}

	/* and restore (gives effect of resetting AGP) */
	nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
}
#endif

int
nouveau_mem_init_agp(struct drm_device *dev)
{
#if __OS_HAS_AGP
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct drm_agp_info info;
	struct drm_agp_mode mode;
	int ret;

	if (nouveau_noagp)
		return 0;

	nouveau_mem_reset_agp(dev);

	if (!dev->agp->acquired) {
		ret = drm_agp_acquire(dev);
		if (ret) {
			NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
			return ret;
		}
	}

	ret = drm_agp_info(dev, &info);
	if (ret) {
		NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
		return ret;
	}

	/* see agp.h for the AGPSTAT_* modes available */
	mode.mode = info.mode;
	ret = drm_agp_enable(dev, mode);
	if (ret) {
		NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
		return ret;
	}

	dev_priv->gart_info.type	= NOUVEAU_GART_AGP;
	dev_priv->gart_info.aper_base	= info.aperture_base;
	dev_priv->gart_info.aper_size	= info.aperture_size;
#endif
	return 0;
}

int
nouveau_mem_init(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	int ret, dma_bits = 32;

	dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
	dev_priv->gart_info.type = NOUVEAU_GART_NONE;

	if (dev_priv->card_type >= NV_50 &&
	    pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
		dma_bits = 40;

	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
	if (ret) {
		NV_ERROR(dev, "Error setting DMA mask: %d\n", ret);
		return ret;
	}

	ret = nouveau_ttm_global_init(dev_priv);
	if (ret)
		return ret;

	ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
				 dev_priv->ttm.bo_global_ref.ref.object,
				 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
				 dma_bits <= 32 ? true : false);
	if (ret) {
		NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
		return ret;
	}

	INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
	spin_lock_init(&dev_priv->ttm.bo_list_lock);
	spin_lock_init(&dev_priv->tile.lock);

	dev_priv->fb_available_size = dev_priv->vram_size;
	dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
	if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
		dev_priv->fb_mappable_pages =
			pci_resource_len(dev->pdev, 1);
	dev_priv->fb_mappable_pages >>= PAGE_SHIFT;

	/* remove reserved space at end of vram from available amount */
	dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
	dev_priv->fb_aper_free = dev_priv->fb_available_size;

	/* mappable vram */
	ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
			     dev_priv->fb_available_size >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
		return ret;
	}

	ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
			     0, 0, true, true, &dev_priv->vga_ram);
	if (ret == 0)
		ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
	if (ret) {
		NV_WARN(dev, "failed to reserve VGA memory\n");
		nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	}

	/* GART */
#if !defined(__powerpc__) && !defined(__ia64__)
	if (drm_device_is_agp(dev) && dev->agp) {
		ret = nouveau_mem_init_agp(dev);
		if (ret)
			NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
	}
#endif

	if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
		ret = nouveau_sgdma_init(dev);
		if (ret) {
			NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
			return ret;
		}
	}

	NV_INFO(dev, "%d MiB GART (aperture)\n",
		(int)(dev_priv->gart_info.aper_size >> 20));
	dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;

	ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
			     dev_priv->gart_info.aper_size >> PAGE_SHIFT);
	if (ret) {
		NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
		return ret;
	}

	dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
					 pci_resource_len(dev->pdev, 1),
					 DRM_MTRR_WC);

	return 0;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
	3	* Copyright 2005 Stephane Marchesin
	4	*
	5	* The Weather Channel (TM) funded Tungsten Graphics to develop the
	6	* initial release of the Radeon 8500 driver under the XFree86 license.
	7	* This notice must be preserved.
	8	*
	9	* Permission is hereby granted, free of charge, to any person obtaining a
	10	* copy of this software and associated documentation files (the "Software"),
	11	* to deal in the Software without restriction, including without limitation
	12	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	13	* and/or sell copies of the Software, and to permit persons to whom the
	14	* Software is furnished to do so, subject to the following conditions:
	15	*
	16	* The above copyright notice and this permission notice (including the next
	17	* paragraph) shall be included in all copies or substantial portions of the
	18	* Software.
	19	*
	20	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	21	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	22	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	23	* THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
	24	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	25	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	26	* DEALINGS IN THE SOFTWARE.
	27	*
	28	* Authors:
	29	* Keith Whitwell <keith@tungstengraphics.com>
	30	*/
	31
	32
	33	#include "drmP.h"
	34	#include "drm.h"
	35	#include "drm_sarea.h"
	36	#include "nouveau_drv.h"
	37
	38	static struct mem_block *
	39	split_block(struct mem_block *p, uint64_t start, uint64_t size,
	40	struct drm_file *file_priv)
	41	{
	42	/* Maybe cut off the start of an existing block */
	43	if (start > p->start) {
	44	struct mem_block *newblock =
	45	kmalloc(sizeof(*newblock), GFP_KERNEL);
	46	if (!newblock)
	47	goto out;
	48	newblock->start = start;
	49	newblock->size = p->size - (start - p->start);
	50	newblock->file_priv = NULL;
	51	newblock->next = p->next;
	52	newblock->prev = p;
	53	p->next->prev = newblock;
	54	p->next = newblock;
	55	p->size -= newblock->size;
	56	p = newblock;
	57	}
	58
	59	/* Maybe cut off the end of an existing block */
	60	if (size < p->size) {
	61	struct mem_block *newblock =
	62	kmalloc(sizeof(*newblock), GFP_KERNEL);
	63	if (!newblock)
	64	goto out;
65	newblock->start = start + size;
66	newblock->size = p->size - size;
67	newblock->file_priv = NULL;
68	newblock->next = p->next;
69	newblock->prev = p;
70	p->next->prev = newblock;
71	p->next = newblock;
72	p->size = size;
73	}
74
75	out:
76	/* Our block is in the middle */
77	p->file_priv = file_priv;
78	return p;
79	}
80
81	struct mem_block *
82	nouveau_mem_alloc_block(struct mem_block *heap, uint64_t size,
83	int align2, struct drm_file *file_priv, int tail)
84	{
85	struct mem_block *p;
86	uint64_t mask = (1 << align2) - 1;
87
88	if (!heap)
89	return NULL;
90
91	if (tail) {
92	list_for_each_prev(p, heap) {
93	uint64_t start = ((p->start + p->size) - size) & ~mask;
94
95	if (p->file_priv == NULL && start >= p->start &&
96	start + size <= p->start + p->size)
97	return split_block(p, start, size, file_priv);
98	}
99	} else {
100	list_for_each(p, heap) {
101	uint64_t start = (p->start + mask) & ~mask;
102
103	if (p->file_priv == NULL &&
104	start + size <= p->start + p->size)
105	return split_block(p, start, size, file_priv);
106	}
107	}
108
109	return NULL;
110	}
111
112	void nouveau_mem_free_block(struct mem_block *p)
113	{
114	p->file_priv = NULL;
115
116	/* Assumes a single contiguous range. Needs a special file_priv in
117	* 'heap' to stop it being subsumed.
118	*/
119	if (p->next->file_priv == NULL) {
120	struct mem_block *q = p->next;
121	p->size += q->size;
122	p->next = q->next;
123	p->next->prev = p;
124	kfree(q);
125	}
126
127	if (p->prev->file_priv == NULL) {
128	struct mem_block *q = p->prev;
129	q->size += p->size;
130	q->next = p->next;
131	q->next->prev = q;
132	kfree(p);
133	}
134	}
135
136	/* Initialize. How to check for an uninitialized heap?
137	*/
138	int nouveau_mem_init_heap(struct mem_block **heap, uint64_t start,
139	uint64_t size)
140	{
141	struct mem_block blocks = kmalloc(sizeof(blocks), GFP_KERNEL);
142
143	if (!blocks)
144	return -ENOMEM;
145
146	heap = kmalloc(sizeof(*heap), GFP_KERNEL);
147	if (!*heap) {
148	kfree(blocks);
149	return -ENOMEM;
150	}
151
152	blocks->start = start;
153	blocks->size = size;
154	blocks->file_priv = NULL;
155	blocks->next = blocks->prev = *heap;
156
157	memset(heap, 0, sizeof(*heap));
158	(heap)->file_priv = (struct drm_file ) -1;
159	(heap)->next = (heap)->prev = blocks;
160	return 0;
161	}
162
163	/*
164	* Free all blocks associated with the releasing file_priv
165	*/
166	void nouveau_mem_release(struct drm_file file_priv, struct mem_block heap)
167	{
168	struct mem_block *p;
169
170	if (!heap \|\| !heap->next)
171	return;
172
173	list_for_each(p, heap) {
174	if (p->file_priv == file_priv)
175	p->file_priv = NULL;
176	}
177
178	/* Assumes a single contiguous range. Needs a special file_priv in
179	* 'heap' to stop it being subsumed.
180	*/
181	list_for_each(p, heap) {
182	while ((p->file_priv == NULL) &&
183	(p->next->file_priv == NULL) &&
184	(p->next != heap)) {
185	struct mem_block *q = p->next;
186	p->size += q->size;
187	p->next = q->next;
188	p->next->prev = p;
189	kfree(q);
190	}
191	}
192	}
193
a0af9add FJ	194	/*
	195	* NV10-NV40 tiling helpers
	196	*/
	197
	198	static void
	199	nv10_mem_set_region_tiling(struct drm_device *dev, int i, uint32_t addr,
	200	uint32_t size, uint32_t pitch)
	201	{
	202	struct drm_nouveau_private *dev_priv = dev->dev_private;
	203	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	204	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	205	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	206	struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
	207
	208	tile->addr = addr;
	209	tile->size = size;
	210	tile->used = !!pitch;
	211	nouveau_fence_unref((void **)&tile->fence);
	212
	213	if (!pfifo->cache_flush(dev))
	214	return;
	215
	216	pfifo->reassign(dev, false);
	217	pfifo->cache_flush(dev);
	218	pfifo->cache_pull(dev, false);
	219
	220	nouveau_wait_for_idle(dev);
	221
	222	pgraph->set_region_tiling(dev, i, addr, size, pitch);
	223	pfb->set_region_tiling(dev, i, addr, size, pitch);
	224
	225	pfifo->cache_pull(dev, true);
	226	pfifo->reassign(dev, true);
	227	}
	228
	229	struct nouveau_tile_reg *
	230	nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
	231	uint32_t pitch)
	232	{
	233	struct drm_nouveau_private *dev_priv = dev->dev_private;
	234	struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
	235	struct nouveau_tile_reg tile = dev_priv->tile.reg, found = NULL;
	236	int i;
	237
	238	spin_lock(&dev_priv->tile.lock);
	239
	240	for (i = 0; i < pfb->num_tiles; i++) {
	241	if (tile[i].used)
	242	/* Tile region in use. */
	243	continue;
	244
	245	if (tile[i].fence &&
	246	!nouveau_fence_signalled(tile[i].fence, NULL))
	247	/* Pending tile region. */
	248	continue;
	249
	250	if (max(tile[i].addr, addr) <
	251	min(tile[i].addr + tile[i].size, addr + size))
	252	/* Kill an intersecting tile region. */
	253	nv10_mem_set_region_tiling(dev, i, 0, 0, 0);
	254
	255	if (pitch && !found) {
	256	/* Free tile region. */
	257	nv10_mem_set_region_tiling(dev, i, addr, size, pitch);
258	found = &tile[i];
259	}
260	}
261
262	spin_unlock(&dev_priv->tile.lock);
263
264	return found;
265	}
266
267	void
268	nv10_mem_expire_tiling(struct drm_device dev, struct nouveau_tile_reg tile,
269	struct nouveau_fence *fence)
270	{
271	if (fence) {
272	/* Mark it as pending. */
273	tile->fence = fence;
274	nouveau_fence_ref(fence);
275	}
276
277	tile->used = false;
278	}
279
6ee73861 BS	280	/*
	281	* NV50 VM helpers
	282	*/
	283	int
	284	nv50_mem_vm_bind_linear(struct drm_device *dev, uint64_t virt, uint32_t size,
	285	uint32_t flags, uint64_t phys)
	286	{
	287	struct drm_nouveau_private *dev_priv = dev->dev_private;
531e7713 BS	288	struct nouveau_gpuobj *pgt;
	289	unsigned block;
	290	int i;
6ee73861	291
531e7713 BS	292	virt = ((virt - dev_priv->vm_vram_base) >> 16) << 1;
531e7713 BS	293	size = (size >> 16) << 1;
6c429667 BS	294
	295	phys \|= ((uint64_t)flags << 32);
	296	phys \|= 1;
	297	if (dev_priv->vram_sys_base) {
	298	phys += dev_priv->vram_sys_base;
	299	phys \|= 0x30;
	300	}
6ee73861 BS	301
6ee73861 BS	302	dev_priv->engine.instmem.prepare_access(dev, true);
531e7713 BS	303	while (size) {
531e7713 BS	304	unsigned offset_h = upper_32_bits(phys);
4c27bd33	305	unsigned offset_l = lower_32_bits(phys);
531e7713 BS	306	unsigned pte, end;
	307
	308	for (i = 7; i >= 0; i--) {
	309	block = 1 << (i + 1);
	310	if (size >= block && !(virt & (block - 1)))
	311	break;
	312	}
	313	offset_l \|= (i << 7);
6ee73861	314
531e7713 BS	315	phys += block << 15;
531e7713 BS	316	size -= block;
6ee73861	317
531e7713 BS	318	while (block) {
	319	pgt = dev_priv->vm_vram_pt[virt >> 14];
	320	pte = virt & 0x3ffe;
	321
	322	end = pte + block;
	323	if (end > 16384)
	324	end = 16384;
	325	block -= (end - pte);
	326	virt += (end - pte);
	327
	328	while (pte < end) {
	329	nv_wo32(dev, pgt, pte++, offset_l);
	330	nv_wo32(dev, pgt, pte++, offset_h);
	331	}
	332	}
6ee73861 BS	333	}
	334	dev_priv->engine.instmem.finish_access(dev);
	335
	336	nv_wr32(dev, 0x100c80, 0x00050001);
	337	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	338	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	339	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	340	return -EBUSY;
	341	}
	342
	343	nv_wr32(dev, 0x100c80, 0x00000001);
	344	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	345	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	346	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	347	return -EBUSY;
	348	}
	349
40b2a687 BS	350	nv_wr32(dev, 0x100c80, 0x00040001);
	351	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	352	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	353	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	354	return -EBUSY;
	355	}
	356
	357	nv_wr32(dev, 0x100c80, 0x00060001);
	358	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	359	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	360	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	361	return -EBUSY;
	362	}
	363
6ee73861 BS	364	return 0;
	365	}
	366
	367	void
	368	nv50_mem_vm_unbind(struct drm_device *dev, uint64_t virt, uint32_t size)
	369	{
4c27bd33 BS	370	struct drm_nouveau_private *dev_priv = dev->dev_private;
	371	struct nouveau_gpuobj *pgt;
	372	unsigned pages, pte, end;
	373
	374	virt -= dev_priv->vm_vram_base;
	375	pages = (size >> 16) << 1;
	376
	377	dev_priv->engine.instmem.prepare_access(dev, true);
	378	while (pages) {
	379	pgt = dev_priv->vm_vram_pt[virt >> 29];
	380	pte = (virt & 0x1ffe0000ULL) >> 15;
	381
	382	end = pte + pages;
	383	if (end > 16384)
	384	end = 16384;
	385	pages -= (end - pte);
	386	virt += (end - pte) << 15;
	387
	388	while (pte < end)
	389	nv_wo32(dev, pgt, pte++, 0);
	390	}
	391	dev_priv->engine.instmem.finish_access(dev);
	392
	393	nv_wr32(dev, 0x100c80, 0x00050001);
	394	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	395	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	396	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	397	return;
	398	}
	399
	400	nv_wr32(dev, 0x100c80, 0x00000001);
40b2a687 BS	401	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	402	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	403	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	404	return;
	405	}
	406
	407	nv_wr32(dev, 0x100c80, 0x00040001);
	408	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	409	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	410	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	411	return;
	412	}
	413
	414	nv_wr32(dev, 0x100c80, 0x00060001);
4c27bd33 BS	415	if (!nv_wait(0x100c80, 0x00000001, 0x00000000)) {
	416	NV_ERROR(dev, "timeout: (0x100c80 & 1) == 0 (2)\n");
	417	NV_ERROR(dev, "0x100c80 = 0x%08x\n", nv_rd32(dev, 0x100c80));
	418	}
6ee73861 BS	419	}
	420
	421	/*
	422	* Cleanup everything
	423	*/
	424	void nouveau_mem_takedown(struct mem_block **heap)
	425	{
	426	struct mem_block *p;
	427
	428	if (!*heap)
	429	return;
	430
	431	for (p = (heap)->next; p != heap;) {
	432	struct mem_block *q = p;
	433	p = p->next;
	434	kfree(q);
	435	}
	436
	437	kfree(*heap);
	438	*heap = NULL;
	439	}
	440
	441	void nouveau_mem_close(struct drm_device *dev)
	442	{
	443	struct drm_nouveau_private *dev_priv = dev->dev_private;
	444
ac8fb975 BS	445	nouveau_bo_unpin(dev_priv->vga_ram);
	446	nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	447
6ee73861 BS	448	ttm_bo_device_release(&dev_priv->ttm.bdev);
	449
	450	nouveau_ttm_global_release(dev_priv);
	451
	452	if (drm_core_has_AGP(dev) && dev->agp &&
	453	drm_core_check_feature(dev, DRIVER_MODESET)) {
	454	struct drm_agp_mem entry, tempe;
	455
	456	/* Remove AGP resources, but leave dev->agp
	457	intact until drv_cleanup is called. */
	458	list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
	459	if (entry->bound)
	460	drm_unbind_agp(entry->memory);
	461	drm_free_agp(entry->memory, entry->pages);
	462	kfree(entry);
	463	}
	464	INIT_LIST_HEAD(&dev->agp->memory);
	465
	466	if (dev->agp->acquired)
	467	drm_agp_release(dev);
	468
	469	dev->agp->acquired = 0;
	470	dev->agp->enabled = 0;
	471	}
	472
	473	if (dev_priv->fb_mtrr) {
01d73a69 JC	474	drm_mtrr_del(dev_priv->fb_mtrr,
	475	pci_resource_start(dev->pdev, 1),
	476	pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
6ee73861 BS	477	dev_priv->fb_mtrr = 0;
	478	}
	479	}
	480
6ee73861	481	static uint32_t
a76fb4e8 BS	482	nouveau_mem_detect_nv04(struct drm_device *dev)
	483	{
	484	uint32_t boot0 = nv_rd32(dev, NV03_BOOT_0);
	485
	486	if (boot0 & 0x00000100)
	487	return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
	488
	489	switch (boot0 & NV03_BOOT_0_RAM_AMOUNT) {
	490	case NV04_BOOT_0_RAM_AMOUNT_32MB:
	491	return 32 * 1024 * 1024;
	492	case NV04_BOOT_0_RAM_AMOUNT_16MB:
	493	return 16 * 1024 * 1024;
	494	case NV04_BOOT_0_RAM_AMOUNT_8MB:
	495	return 8 * 1024 * 1024;
	496	case NV04_BOOT_0_RAM_AMOUNT_4MB:
	497	return 4 * 1024 * 1024;
	498	}
	499
	500	return 0;
	501	}
	502
	503	static uint32_t
	504	nouveau_mem_detect_nforce(struct drm_device *dev)
6ee73861 BS	505	{
	506	struct drm_nouveau_private *dev_priv = dev->dev_private;
	507	struct pci_dev *bridge;
	508	uint32_t mem;
	509
	510	bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
	511	if (!bridge) {
	512	NV_ERROR(dev, "no bridge device\n");
	513	return 0;
	514	}
	515
a76fb4e8	516	if (dev_priv->flags & NV_NFORCE) {
6ee73861 BS	517	pci_read_config_dword(bridge, 0x7C, &mem);
	518	return (uint64_t)(((mem >> 6) & 31) + 1)10241024;
	519	} else
a76fb4e8	520	if (dev_priv->flags & NV_NFORCE2) {
6ee73861 BS	521	pci_read_config_dword(bridge, 0x84, &mem);
	522	return (uint64_t)(((mem >> 4) & 127) + 1)10241024;
	523	}
	524
	525	NV_ERROR(dev, "impossible!\n");
	526	return 0;
	527	}
	528
	529	/* returns the amount of FB ram in bytes */
a76fb4e8 BS	530	int
a76fb4e8 BS	531	nouveau_mem_detect(struct drm_device *dev)
6ee73861 BS	532	{
6ee73861 BS	533	struct drm_nouveau_private *dev_priv = dev->dev_private;
a76fb4e8 BS	534
	535	if (dev_priv->card_type == NV_04) {
	536	dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
	537	} else
	538	if (dev_priv->flags & (NV_NFORCE \| NV_NFORCE2)) {
	539	dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
	540	} else {
	541	dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA);
	542	dev_priv->vram_size &= NV10_FIFO_DATA_RAM_AMOUNT_MB_MASK;
	543	if (dev_priv->chipset == 0xaa \|\| dev_priv->chipset == 0xac)
8b281db5 BS	544	dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
8b281db5 BS	545	dev_priv->vram_sys_base <<= 12;
6ee73861 BS	546	}
6ee73861 BS	547
a76fb4e8 BS	548	NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
	549	if (dev_priv->vram_sys_base) {
	550	NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
	551	dev_priv->vram_sys_base);
	552	}
	553
	554	if (dev_priv->vram_size)
	555	return 0;
	556	return -ENOMEM;
6ee73861 BS	557	}
6ee73861 BS	558
b694dfb2	559	#if __OS_HAS_AGP
6ee73861 BS	560	static void nouveau_mem_reset_agp(struct drm_device *dev)
	561	{
	562	uint32_t saved_pci_nv_1, saved_pci_nv_19, pmc_enable;
	563
	564	saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
	565	saved_pci_nv_19 = nv_rd32(dev, NV04_PBUS_PCI_NV_19);
	566
	567	/* clear busmaster bit */
	568	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
	569	/* clear SBA and AGP bits */
	570	nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19 & 0xfffff0ff);
	571
	572	/* power cycle pgraph, if enabled */
	573	pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
	574	if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
	575	nv_wr32(dev, NV03_PMC_ENABLE,
	576	pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
	577	nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) \|
	578	NV_PMC_ENABLE_PGRAPH);
	579	}
	580
	581	/* and restore (gives effect of resetting AGP) */
	582	nv_wr32(dev, NV04_PBUS_PCI_NV_19, saved_pci_nv_19);
	583	nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
	584	}
b694dfb2	585	#endif
6ee73861 BS	586
	587	int
	588	nouveau_mem_init_agp(struct drm_device *dev)
	589	{
b694dfb2	590	#if __OS_HAS_AGP
6ee73861 BS	591	struct drm_nouveau_private *dev_priv = dev->dev_private;
	592	struct drm_agp_info info;
	593	struct drm_agp_mode mode;
	594	int ret;
	595
	596	if (nouveau_noagp)
	597	return 0;
	598
	599	nouveau_mem_reset_agp(dev);
	600
	601	if (!dev->agp->acquired) {
	602	ret = drm_agp_acquire(dev);
	603	if (ret) {
	604	NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
	605	return ret;
	606	}
	607	}
	608
	609	ret = drm_agp_info(dev, &info);
	610	if (ret) {
	611	NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
	612	return ret;
	613	}
	614
	615	/* see agp.h for the AGPSTAT_* modes available */
	616	mode.mode = info.mode;
	617	ret = drm_agp_enable(dev, mode);
	618	if (ret) {
	619	NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
	620	return ret;
	621	}
	622
	623	dev_priv->gart_info.type = NOUVEAU_GART_AGP;
	624	dev_priv->gart_info.aper_base = info.aperture_base;
	625	dev_priv->gart_info.aper_size = info.aperture_size;
b694dfb2	626	#endif
6ee73861 BS	627	return 0;
	628	}
	629
	630	int
	631	nouveau_mem_init(struct drm_device *dev)
	632	{
	633	struct drm_nouveau_private *dev_priv = dev->dev_private;
	634	struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
	635	int ret, dma_bits = 32;
	636
01d73a69	637	dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
6ee73861 BS	638	dev_priv->gart_info.type = NOUVEAU_GART_NONE;
	639
	640	if (dev_priv->card_type >= NV_50 &&
	641	pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
	642	dma_bits = 40;
	643
	644	ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
	645	if (ret) {
	646	NV_ERROR(dev, "Error setting DMA mask: %d\n", ret);
	647	return ret;
	648	}
	649
	650	ret = nouveau_ttm_global_init(dev_priv);
	651	if (ret)
	652	return ret;
	653
	654	ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
	655	dev_priv->ttm.bo_global_ref.ref.object,
	656	&nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
	657	dma_bits <= 32 ? true : false);
	658	if (ret) {
	659	NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
	660	return ret;
	661	}
	662
	663	INIT_LIST_HEAD(&dev_priv->ttm.bo_list);
	664	spin_lock_init(&dev_priv->ttm.bo_list_lock);
a0af9add	665	spin_lock_init(&dev_priv->tile.lock);
6ee73861	666
a76fb4e8	667	dev_priv->fb_available_size = dev_priv->vram_size;
6ee73861	668	dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
01d73a69 JC	669	if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
	670	dev_priv->fb_mappable_pages =
	671	pci_resource_len(dev->pdev, 1);
6ee73861 BS	672	dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
6ee73861 BS	673
6ee73861 BS	674	/* remove reserved space at end of vram from available amount */
	675	dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
	676	dev_priv->fb_aper_free = dev_priv->fb_available_size;
	677
	678	/* mappable vram */
	679	ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
	680	dev_priv->fb_available_size >> PAGE_SHIFT);
	681	if (ret) {
	682	NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
	683	return ret;
	684	}
	685
ac8fb975 BS	686	ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
	687	0, 0, true, true, &dev_priv->vga_ram);
	688	if (ret == 0)
	689	ret = nouveau_bo_pin(dev_priv->vga_ram, TTM_PL_FLAG_VRAM);
	690	if (ret) {
	691	NV_WARN(dev, "failed to reserve VGA memory\n");
	692	nouveau_bo_ref(NULL, &dev_priv->vga_ram);
	693	}
	694
6ee73861 BS	695	/* GART */
	696	#if !defined(__powerpc__) && !defined(__ia64__)
	697	if (drm_device_is_agp(dev) && dev->agp) {
	698	ret = nouveau_mem_init_agp(dev);
	699	if (ret)
	700	NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
	701	}
	702	#endif
	703
	704	if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
	705	ret = nouveau_sgdma_init(dev);
	706	if (ret) {
	707	NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
	708	return ret;
	709	}
	710	}
	711
	712	NV_INFO(dev, "%d MiB GART (aperture)\n",
	713	(int)(dev_priv->gart_info.aper_size >> 20));
	714	dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
	715
	716	ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
	717	dev_priv->gart_info.aper_size >> PAGE_SHIFT);
	718	if (ret) {
	719	NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
	720	return ret;
	721	}
	722
01d73a69 JC	723	dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
01d73a69 JC	724	pci_resource_len(dev->pdev, 1),
6ee73861	725	DRM_MTRR_WC);
ac8fb975	726
6ee73861 BS	727	return 0;
	728	}
	729
	730