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fbdev: allow passing more than one aperture for handoff
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_state.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/swab.h>
5a0e3ad6 27#include <linux/slab.h>
6ee73861
BS		 28#include "drmP.h"
29#include "drm.h"
30#include "drm_sarea.h"
31#include "drm_crtc_helper.h"
32#include <linux/vgaarb.h>
6a9ee8af 33#include <linux/vga_switcheroo.h>
6ee73861
BS		 34
35#include "nouveau_drv.h"
36#include "nouveau_drm.h"
38651674 37#include "nouveau_fbcon.h"
6ee73861
BS		 38#include "nv50_display.h"
39
6ee73861
BS		 40static void nouveau_stub_takedown(struct drm_device *dev) {}
41
42static int nouveau_init_engine_ptrs(struct drm_device *dev)
43{
44 struct drm_nouveau_private *dev_priv = dev->dev_private;
45 struct nouveau_engine *engine = &dev_priv->engine;
46
47 switch (dev_priv->chipset & 0xf0) {
48 case 0x00:
49 engine->instmem.init = nv04_instmem_init;
50 engine->instmem.takedown = nv04_instmem_takedown;
51 engine->instmem.suspend = nv04_instmem_suspend;
52 engine->instmem.resume = nv04_instmem_resume;
53 engine->instmem.populate = nv04_instmem_populate;
54 engine->instmem.clear = nv04_instmem_clear;
55 engine->instmem.bind = nv04_instmem_bind;
56 engine->instmem.unbind = nv04_instmem_unbind;
57 engine->instmem.prepare_access = nv04_instmem_prepare_access;
58 engine->instmem.finish_access = nv04_instmem_finish_access;
59 engine->mc.init = nv04_mc_init;
60 engine->mc.takedown = nv04_mc_takedown;
61 engine->timer.init = nv04_timer_init;
62 engine->timer.read = nv04_timer_read;
63 engine->timer.takedown = nv04_timer_takedown;
64 engine->fb.init = nv04_fb_init;
65 engine->fb.takedown = nv04_fb_takedown;
66 engine->graph.grclass = nv04_graph_grclass;
67 engine->graph.init = nv04_graph_init;
68 engine->graph.takedown = nv04_graph_takedown;
69 engine->graph.fifo_access = nv04_graph_fifo_access;
70 engine->graph.channel = nv04_graph_channel;
71 engine->graph.create_context = nv04_graph_create_context;
72 engine->graph.destroy_context = nv04_graph_destroy_context;
73 engine->graph.load_context = nv04_graph_load_context;
74 engine->graph.unload_context = nv04_graph_unload_context;
75 engine->fifo.channels = 16;
76 engine->fifo.init = nv04_fifo_init;
77 engine->fifo.takedown = nouveau_stub_takedown;
78 engine->fifo.disable = nv04_fifo_disable;
79 engine->fifo.enable = nv04_fifo_enable;
80 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 81 engine->fifo.cache_flush = nv04_fifo_cache_flush;
82 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 83 engine->fifo.channel_id = nv04_fifo_channel_id;
84 engine->fifo.create_context = nv04_fifo_create_context;
85 engine->fifo.destroy_context = nv04_fifo_destroy_context;
86 engine->fifo.load_context = nv04_fifo_load_context;
87 engine->fifo.unload_context = nv04_fifo_unload_context;
88 break;
89 case 0x10:
90 engine->instmem.init = nv04_instmem_init;
91 engine->instmem.takedown = nv04_instmem_takedown;
92 engine->instmem.suspend = nv04_instmem_suspend;
93 engine->instmem.resume = nv04_instmem_resume;
94 engine->instmem.populate = nv04_instmem_populate;
95 engine->instmem.clear = nv04_instmem_clear;
96 engine->instmem.bind = nv04_instmem_bind;
97 engine->instmem.unbind = nv04_instmem_unbind;
98 engine->instmem.prepare_access = nv04_instmem_prepare_access;
99 engine->instmem.finish_access = nv04_instmem_finish_access;
100 engine->mc.init = nv04_mc_init;
101 engine->mc.takedown = nv04_mc_takedown;
102 engine->timer.init = nv04_timer_init;
103 engine->timer.read = nv04_timer_read;
104 engine->timer.takedown = nv04_timer_takedown;
105 engine->fb.init = nv10_fb_init;
106 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 107 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 108 engine->graph.grclass = nv10_graph_grclass;
109 engine->graph.init = nv10_graph_init;
110 engine->graph.takedown = nv10_graph_takedown;
111 engine->graph.channel = nv10_graph_channel;
112 engine->graph.create_context = nv10_graph_create_context;
113 engine->graph.destroy_context = nv10_graph_destroy_context;
114 engine->graph.fifo_access = nv04_graph_fifo_access;
115 engine->graph.load_context = nv10_graph_load_context;
116 engine->graph.unload_context = nv10_graph_unload_context;
cb00f7c1 117 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
6ee73861
BS		 118 engine->fifo.channels = 32;
119 engine->fifo.init = nv10_fifo_init;
120 engine->fifo.takedown = nouveau_stub_takedown;
121 engine->fifo.disable = nv04_fifo_disable;
122 engine->fifo.enable = nv04_fifo_enable;
123 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 124 engine->fifo.cache_flush = nv04_fifo_cache_flush;
125 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 126 engine->fifo.channel_id = nv10_fifo_channel_id;
127 engine->fifo.create_context = nv10_fifo_create_context;
128 engine->fifo.destroy_context = nv10_fifo_destroy_context;
129 engine->fifo.load_context = nv10_fifo_load_context;
130 engine->fifo.unload_context = nv10_fifo_unload_context;
131 break;
132 case 0x20:
133 engine->instmem.init = nv04_instmem_init;
134 engine->instmem.takedown = nv04_instmem_takedown;
135 engine->instmem.suspend = nv04_instmem_suspend;
136 engine->instmem.resume = nv04_instmem_resume;
137 engine->instmem.populate = nv04_instmem_populate;
138 engine->instmem.clear = nv04_instmem_clear;
139 engine->instmem.bind = nv04_instmem_bind;
140 engine->instmem.unbind = nv04_instmem_unbind;
141 engine->instmem.prepare_access = nv04_instmem_prepare_access;
142 engine->instmem.finish_access = nv04_instmem_finish_access;
143 engine->mc.init = nv04_mc_init;
144 engine->mc.takedown = nv04_mc_takedown;
145 engine->timer.init = nv04_timer_init;
146 engine->timer.read = nv04_timer_read;
147 engine->timer.takedown = nv04_timer_takedown;
148 engine->fb.init = nv10_fb_init;
149 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 150 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 151 engine->graph.grclass = nv20_graph_grclass;
152 engine->graph.init = nv20_graph_init;
153 engine->graph.takedown = nv20_graph_takedown;
154 engine->graph.channel = nv10_graph_channel;
155 engine->graph.create_context = nv20_graph_create_context;
156 engine->graph.destroy_context = nv20_graph_destroy_context;
157 engine->graph.fifo_access = nv04_graph_fifo_access;
158 engine->graph.load_context = nv20_graph_load_context;
159 engine->graph.unload_context = nv20_graph_unload_context;
cb00f7c1 160 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
6ee73861
BS		 161 engine->fifo.channels = 32;
162 engine->fifo.init = nv10_fifo_init;
163 engine->fifo.takedown = nouveau_stub_takedown;
164 engine->fifo.disable = nv04_fifo_disable;
165 engine->fifo.enable = nv04_fifo_enable;
166 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 167 engine->fifo.cache_flush = nv04_fifo_cache_flush;
168 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 169 engine->fifo.channel_id = nv10_fifo_channel_id;
170 engine->fifo.create_context = nv10_fifo_create_context;
171 engine->fifo.destroy_context = nv10_fifo_destroy_context;
172 engine->fifo.load_context = nv10_fifo_load_context;
173 engine->fifo.unload_context = nv10_fifo_unload_context;
174 break;
175 case 0x30:
176 engine->instmem.init = nv04_instmem_init;
177 engine->instmem.takedown = nv04_instmem_takedown;
178 engine->instmem.suspend = nv04_instmem_suspend;
179 engine->instmem.resume = nv04_instmem_resume;
180 engine->instmem.populate = nv04_instmem_populate;
181 engine->instmem.clear = nv04_instmem_clear;
182 engine->instmem.bind = nv04_instmem_bind;
183 engine->instmem.unbind = nv04_instmem_unbind;
184 engine->instmem.prepare_access = nv04_instmem_prepare_access;
185 engine->instmem.finish_access = nv04_instmem_finish_access;
186 engine->mc.init = nv04_mc_init;
187 engine->mc.takedown = nv04_mc_takedown;
188 engine->timer.init = nv04_timer_init;
189 engine->timer.read = nv04_timer_read;
190 engine->timer.takedown = nv04_timer_takedown;
191 engine->fb.init = nv10_fb_init;
192 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 193 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 194 engine->graph.grclass = nv30_graph_grclass;
195 engine->graph.init = nv30_graph_init;
196 engine->graph.takedown = nv20_graph_takedown;
197 engine->graph.fifo_access = nv04_graph_fifo_access;
198 engine->graph.channel = nv10_graph_channel;
199 engine->graph.create_context = nv20_graph_create_context;
200 engine->graph.destroy_context = nv20_graph_destroy_context;
201 engine->graph.load_context = nv20_graph_load_context;
202 engine->graph.unload_context = nv20_graph_unload_context;
cb00f7c1 203 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
6ee73861
BS		 204 engine->fifo.channels = 32;
205 engine->fifo.init = nv10_fifo_init;
206 engine->fifo.takedown = nouveau_stub_takedown;
207 engine->fifo.disable = nv04_fifo_disable;
208 engine->fifo.enable = nv04_fifo_enable;
209 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 210 engine->fifo.cache_flush = nv04_fifo_cache_flush;
211 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 212 engine->fifo.channel_id = nv10_fifo_channel_id;
213 engine->fifo.create_context = nv10_fifo_create_context;
214 engine->fifo.destroy_context = nv10_fifo_destroy_context;
215 engine->fifo.load_context = nv10_fifo_load_context;
216 engine->fifo.unload_context = nv10_fifo_unload_context;
217 break;
218 case 0x40:
219 case 0x60:
220 engine->instmem.init = nv04_instmem_init;
221 engine->instmem.takedown = nv04_instmem_takedown;
222 engine->instmem.suspend = nv04_instmem_suspend;
223 engine->instmem.resume = nv04_instmem_resume;
224 engine->instmem.populate = nv04_instmem_populate;
225 engine->instmem.clear = nv04_instmem_clear;
226 engine->instmem.bind = nv04_instmem_bind;
227 engine->instmem.unbind = nv04_instmem_unbind;
228 engine->instmem.prepare_access = nv04_instmem_prepare_access;
229 engine->instmem.finish_access = nv04_instmem_finish_access;
230 engine->mc.init = nv40_mc_init;
231 engine->mc.takedown = nv40_mc_takedown;
232 engine->timer.init = nv04_timer_init;
233 engine->timer.read = nv04_timer_read;
234 engine->timer.takedown = nv04_timer_takedown;
235 engine->fb.init = nv40_fb_init;
236 engine->fb.takedown = nv40_fb_takedown;
cb00f7c1 237 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
6ee73861
BS		 238 engine->graph.grclass = nv40_graph_grclass;
239 engine->graph.init = nv40_graph_init;
240 engine->graph.takedown = nv40_graph_takedown;
241 engine->graph.fifo_access = nv04_graph_fifo_access;
242 engine->graph.channel = nv40_graph_channel;
243 engine->graph.create_context = nv40_graph_create_context;
244 engine->graph.destroy_context = nv40_graph_destroy_context;
245 engine->graph.load_context = nv40_graph_load_context;
246 engine->graph.unload_context = nv40_graph_unload_context;
cb00f7c1 247 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
6ee73861
BS		 248 engine->fifo.channels = 32;
249 engine->fifo.init = nv40_fifo_init;
250 engine->fifo.takedown = nouveau_stub_takedown;
251 engine->fifo.disable = nv04_fifo_disable;
252 engine->fifo.enable = nv04_fifo_enable;
253 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 254 engine->fifo.cache_flush = nv04_fifo_cache_flush;
255 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 256 engine->fifo.channel_id = nv10_fifo_channel_id;
257 engine->fifo.create_context = nv40_fifo_create_context;
258 engine->fifo.destroy_context = nv40_fifo_destroy_context;
259 engine->fifo.load_context = nv40_fifo_load_context;
260 engine->fifo.unload_context = nv40_fifo_unload_context;
261 break;
262 case 0x50:
263 case 0x80: /* gotta love NVIDIA's consistency.. */
264 case 0x90:
265 case 0xA0:
266 engine->instmem.init = nv50_instmem_init;
267 engine->instmem.takedown = nv50_instmem_takedown;
268 engine->instmem.suspend = nv50_instmem_suspend;
269 engine->instmem.resume = nv50_instmem_resume;
270 engine->instmem.populate = nv50_instmem_populate;
271 engine->instmem.clear = nv50_instmem_clear;
272 engine->instmem.bind = nv50_instmem_bind;
273 engine->instmem.unbind = nv50_instmem_unbind;
274 engine->instmem.prepare_access = nv50_instmem_prepare_access;
275 engine->instmem.finish_access = nv50_instmem_finish_access;
276 engine->mc.init = nv50_mc_init;
277 engine->mc.takedown = nv50_mc_takedown;
278 engine->timer.init = nv04_timer_init;
279 engine->timer.read = nv04_timer_read;
280 engine->timer.takedown = nv04_timer_takedown;
304424e1
MK		 281 engine->fb.init = nv50_fb_init;
282 engine->fb.takedown = nv50_fb_takedown;
6ee73861
BS		 283 engine->graph.grclass = nv50_graph_grclass;
284 engine->graph.init = nv50_graph_init;
285 engine->graph.takedown = nv50_graph_takedown;
286 engine->graph.fifo_access = nv50_graph_fifo_access;
287 engine->graph.channel = nv50_graph_channel;
288 engine->graph.create_context = nv50_graph_create_context;
289 engine->graph.destroy_context = nv50_graph_destroy_context;
290 engine->graph.load_context = nv50_graph_load_context;
291 engine->graph.unload_context = nv50_graph_unload_context;
292 engine->fifo.channels = 128;
293 engine->fifo.init = nv50_fifo_init;
294 engine->fifo.takedown = nv50_fifo_takedown;
295 engine->fifo.disable = nv04_fifo_disable;
296 engine->fifo.enable = nv04_fifo_enable;
297 engine->fifo.reassign = nv04_fifo_reassign;
298 engine->fifo.channel_id = nv50_fifo_channel_id;
299 engine->fifo.create_context = nv50_fifo_create_context;
300 engine->fifo.destroy_context = nv50_fifo_destroy_context;
301 engine->fifo.load_context = nv50_fifo_load_context;
302 engine->fifo.unload_context = nv50_fifo_unload_context;
303 break;
304 default:
305 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
306 return 1;
307 }
308
309 return 0;
310}
311
312static unsigned int
313nouveau_vga_set_decode(void *priv, bool state)
314{
9967b948
MK		 315 struct drm_device *dev = priv;
316 struct drm_nouveau_private *dev_priv = dev->dev_private;
317
318 if (dev_priv->chipset >= 0x40)
319 nv_wr32(dev, 0x88054, state);
320 else
321 nv_wr32(dev, 0x1854, state);
322
6ee73861
BS		 323 if (state)
324 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
325 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
326 else
327 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
328}
329
0735f62e
BS		 330static int
331nouveau_card_init_channel(struct drm_device *dev)
332{
333 struct drm_nouveau_private *dev_priv = dev->dev_private;
334 struct nouveau_gpuobj *gpuobj;
335 int ret;
336
337 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
338 (struct drm_file *)-2,
339 NvDmaFB, NvDmaTT);
340 if (ret)
341 return ret;
342
343 gpuobj = NULL;
344 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
a76fb4e8 345 0, dev_priv->vram_size,
0735f62e
BS		 346 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
347 &gpuobj);
348 if (ret)
349 goto out_err;
350
351 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
352 gpuobj, NULL);
353 if (ret)
354 goto out_err;
355
356 gpuobj = NULL;
357 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
358 dev_priv->gart_info.aper_size,
359 NV_DMA_ACCESS_RW, &gpuobj, NULL);
360 if (ret)
361 goto out_err;
362
363 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
364 gpuobj, NULL);
365 if (ret)
366 goto out_err;
367
368 return 0;
369out_err:
370 nouveau_gpuobj_del(dev, &gpuobj);
371 nouveau_channel_free(dev_priv->channel);
372 dev_priv->channel = NULL;
373 return ret;
374}
375
6a9ee8af
DA		 376static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
377 enum vga_switcheroo_state state)
378{
379 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
380 if (state == VGA_SWITCHEROO_ON) {
381 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
382 nouveau_pci_resume(pdev);
383 } else {
384 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
385 nouveau_pci_suspend(pdev, pmm);
386 }
387}
388
389static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
390{
391 struct drm_device *dev = pci_get_drvdata(pdev);
392 bool can_switch;
393
394 spin_lock(&dev->count_lock);
395 can_switch = (dev->open_count == 0);
396 spin_unlock(&dev->count_lock);
397 return can_switch;
398}
399
6ee73861
BS		 400int
401nouveau_card_init(struct drm_device *dev)
402{
403 struct drm_nouveau_private *dev_priv = dev->dev_private;
404 struct nouveau_engine *engine;
6ee73861
BS		 405 int ret;
406
407 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
408
409 if (dev_priv->init_state == NOUVEAU_CARD_INIT_DONE)
410 return 0;
411
412 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
6a9ee8af
DA		 413 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
414 nouveau_switcheroo_can_switch);
6ee73861
BS		 415
416 /* Initialise internal driver API hooks */
417 ret = nouveau_init_engine_ptrs(dev);
418 if (ret)
c5804be0 419 goto out;
6ee73861
BS		 420 engine = &dev_priv->engine;
421 dev_priv->init_state = NOUVEAU_CARD_INIT_FAILED;
ff9e5279 422 spin_lock_init(&dev_priv->context_switch_lock);
6ee73861
BS		 423
424 /* Parse BIOS tables / Run init tables if card not POSTed */
425 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
426 ret = nouveau_bios_init(dev);
427 if (ret)
c5804be0 428 goto out;
6ee73861
BS		 429 }
430
a76fb4e8
BS		 431 ret = nouveau_mem_detect(dev);
432 if (ret)
433 goto out_bios;
434
6ee73861
BS		 435 ret = nouveau_gpuobj_early_init(dev);
436 if (ret)
c5804be0 437 goto out_bios;
6ee73861
BS		 438
439 /* Initialise instance memory, must happen before mem_init so we
440 * know exactly how much VRAM we're able to use for "normal"
441 * purposes.
442 */
443 ret = engine->instmem.init(dev);
444 if (ret)
c5804be0 445 goto out_gpuobj_early;
6ee73861
BS		 446
447 /* Setup the memory manager */
448 ret = nouveau_mem_init(dev);
449 if (ret)
c5804be0 450 goto out_instmem;
6ee73861
BS		 451
452 ret = nouveau_gpuobj_init(dev);
453 if (ret)
c5804be0 454 goto out_mem;
6ee73861
BS		 455
456 /* PMC */
457 ret = engine->mc.init(dev);
458 if (ret)
c5804be0 459 goto out_gpuobj;
6ee73861
BS		 460
461 /* PTIMER */
462 ret = engine->timer.init(dev);
463 if (ret)
c5804be0 464 goto out_mc;
6ee73861
BS		 465
466 /* PFB */
467 ret = engine->fb.init(dev);
468 if (ret)
c5804be0 469 goto out_timer;
6ee73861 470
a32ed69d
MK		 471 if (nouveau_noaccel)
472 engine->graph.accel_blocked = true;
473 else {
474 /* PGRAPH */
475 ret = engine->graph.init(dev);
476 if (ret)
477 goto out_fb;
6ee73861 478
a32ed69d
MK		 479 /* PFIFO */
480 ret = engine->fifo.init(dev);
481 if (ret)
482 goto out_graph;
483 }
6ee73861
BS		 484
485 /* this call irq_preinstall, register irq handler and
486 * call irq_postinstall
487 */
488 ret = drm_irq_install(dev);
489 if (ret)
c5804be0 490 goto out_fifo;
6ee73861
BS		 491
492 ret = drm_vblank_init(dev, 0);
493 if (ret)
c5804be0 494 goto out_irq;
6ee73861
BS		 495
496 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
497
0735f62e
BS		 498 if (!engine->graph.accel_blocked) {
499 ret = nouveau_card_init_channel(dev);
500 if (ret)
501 goto out_irq;
6ee73861
BS		 502 }
503
504 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
c5804be0 505 if (dev_priv->card_type >= NV_50)
6ee73861 506 ret = nv50_display_create(dev);
c5804be0 507 else
6ee73861 508 ret = nv04_display_create(dev);
c5804be0 509 if (ret)
78bb3512 510 goto out_channel;
6ee73861
BS		 511 }
512
513 ret = nouveau_backlight_init(dev);
514 if (ret)
515 NV_ERROR(dev, "Error %d registering backlight\n", ret);
516
517 dev_priv->init_state = NOUVEAU_CARD_INIT_DONE;
518
519 if (drm_core_check_feature(dev, DRIVER_MODESET))
38651674 520 nouveau_fbcon_init(dev);
6ee73861
BS		 521
522 return 0;
c5804be0 523
78bb3512
BS		 524out_channel:
525 if (dev_priv->channel) {
526 nouveau_channel_free(dev_priv->channel);
527 dev_priv->channel = NULL;
528 }
c5804be0
MK		 529out_irq:
530 drm_irq_uninstall(dev);
531out_fifo:
a32ed69d
MK		 532 if (!nouveau_noaccel)
533 engine->fifo.takedown(dev);
c5804be0 534out_graph:
a32ed69d
MK		 535 if (!nouveau_noaccel)
536 engine->graph.takedown(dev);
c5804be0
MK		 537out_fb:
538 engine->fb.takedown(dev);
539out_timer:
540 engine->timer.takedown(dev);
541out_mc:
542 engine->mc.takedown(dev);
543out_gpuobj:
544 nouveau_gpuobj_takedown(dev);
545out_mem:
78bb3512 546 nouveau_sgdma_takedown(dev);
c5804be0
MK		 547 nouveau_mem_close(dev);
548out_instmem:
549 engine->instmem.takedown(dev);
550out_gpuobj_early:
551 nouveau_gpuobj_late_takedown(dev);
552out_bios:
553 nouveau_bios_takedown(dev);
554out:
555 vga_client_register(dev->pdev, NULL, NULL, NULL);
556 return ret;
6ee73861
BS		 557}
558
559static void nouveau_card_takedown(struct drm_device *dev)
560{
561 struct drm_nouveau_private *dev_priv = dev->dev_private;
562 struct nouveau_engine *engine = &dev_priv->engine;
563
564 NV_DEBUG(dev, "prev state = %d\n", dev_priv->init_state);
565
566 if (dev_priv->init_state != NOUVEAU_CARD_INIT_DOWN) {
38651674 567
6ee73861
BS		 568 nouveau_backlight_exit(dev);
569
570 if (dev_priv->channel) {
571 nouveau_channel_free(dev_priv->channel);
572 dev_priv->channel = NULL;
573 }
574
a32ed69d
MK		 575 if (!nouveau_noaccel) {
576 engine->fifo.takedown(dev);
577 engine->graph.takedown(dev);
578 }
6ee73861
BS		 579 engine->fb.takedown(dev);
580 engine->timer.takedown(dev);
581 engine->mc.takedown(dev);
582
583 mutex_lock(&dev->struct_mutex);
71666475 584 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
6ee73861
BS		 585 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
586 mutex_unlock(&dev->struct_mutex);
587 nouveau_sgdma_takedown(dev);
588
589 nouveau_gpuobj_takedown(dev);
590 nouveau_mem_close(dev);
591 engine->instmem.takedown(dev);
592
593 if (drm_core_check_feature(dev, DRIVER_MODESET))
594 drm_irq_uninstall(dev);
595
596 nouveau_gpuobj_late_takedown(dev);
597 nouveau_bios_takedown(dev);
598
599 vga_client_register(dev->pdev, NULL, NULL, NULL);
600
601 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
602 }
603}
604
605/* here a client dies, release the stuff that was allocated for its
606 * file_priv */
607void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
608{
609 nouveau_channel_cleanup(dev, file_priv);
610}
611
612/* first module load, setup the mmio/fb mapping */
613/* KMS: we need mmio at load time, not when the first drm client opens. */
614int nouveau_firstopen(struct drm_device *dev)
615{
616 return 0;
617}
618
619/* if we have an OF card, copy vbios to RAMIN */
620static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
621{
622#if defined(__powerpc__)
623 int size, i;
624 const uint32_t *bios;
625 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
626 if (!dn) {
627 NV_INFO(dev, "Unable to get the OF node\n");
628 return;
629 }
630
631 bios = of_get_property(dn, "NVDA,BMP", &size);
632 if (bios) {
633 for (i = 0; i < size; i += 4)
634 nv_wi32(dev, i, bios[i/4]);
635 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
636 } else {
637 NV_INFO(dev, "Unable to get the OF bios\n");
638 }
639#endif
640}
641
642int nouveau_load(struct drm_device *dev, unsigned long flags)
643{
644 struct drm_nouveau_private *dev_priv;
645 uint32_t reg0;
646 resource_size_t mmio_start_offs;
647
648 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
649 if (!dev_priv)
650 return -ENOMEM;
651 dev->dev_private = dev_priv;
652 dev_priv->dev = dev;
653
654 dev_priv->flags = flags & NOUVEAU_FLAGS;
655 dev_priv->init_state = NOUVEAU_CARD_INIT_DOWN;
656
657 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
658 dev->pci_vendor, dev->pci_device, dev->pdev->class);
659
6ee73861
BS		 660 dev_priv->wq = create_workqueue("nouveau");
661 if (!dev_priv->wq)
662 return -EINVAL;
663
664 /* resource 0 is mmio regs */
665 /* resource 1 is linear FB */
666 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
667 /* resource 6 is bios */
668
669 /* map the mmio regs */
670 mmio_start_offs = pci_resource_start(dev->pdev, 0);
671 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
672 if (!dev_priv->mmio) {
673 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
674 "Please report your setup to " DRIVER_EMAIL "\n");
675 return -EINVAL;
676 }
677 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
678 (unsigned long long)mmio_start_offs);
679
680#ifdef __BIG_ENDIAN
681 /* Put the card in BE mode if it's not */
682 if (nv_rd32(dev, NV03_PMC_BOOT_1))
683 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
684
685 DRM_MEMORYBARRIER();
686#endif
687
688 /* Time to determine the card architecture */
689 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
690
691 /* We're dealing with >=NV10 */
692 if ((reg0 & 0x0f000000) > 0) {
693 /* Bit 27-20 contain the architecture in hex */
694 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
695 /* NV04 or NV05 */
696 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1dee7a93
BS		 697 if (reg0 & 0x00f00000)
698 dev_priv->chipset = 0x05;
699 else
700 dev_priv->chipset = 0x04;
6ee73861
BS		 701 } else
702 dev_priv->chipset = 0xff;
703
704 switch (dev_priv->chipset & 0xf0) {
705 case 0x00:
706 case 0x10:
707 case 0x20:
708 case 0x30:
709 dev_priv->card_type = dev_priv->chipset & 0xf0;
710 break;
711 case 0x40:
712 case 0x60:
713 dev_priv->card_type = NV_40;
714 break;
715 case 0x50:
716 case 0x80:
717 case 0x90:
718 case 0xa0:
719 dev_priv->card_type = NV_50;
720 break;
721 default:
722 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
723 return -EINVAL;
724 }
725
726 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
727 dev_priv->card_type, reg0);
728
729 /* map larger RAMIN aperture on NV40 cards */
730 dev_priv->ramin = NULL;
731 if (dev_priv->card_type >= NV_40) {
732 int ramin_bar = 2;
733 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
734 ramin_bar = 3;
735
736 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
737 dev_priv->ramin = ioremap(
738 pci_resource_start(dev->pdev, ramin_bar),
739 dev_priv->ramin_size);
740 if (!dev_priv->ramin) {
741 NV_ERROR(dev, "Failed to init RAMIN mapping, "
742 "limited instance memory available\n");
743 }
744 }
745
746 /* On older cards (or if the above failed), create a map covering
747 * the BAR0 PRAMIN aperture */
748 if (!dev_priv->ramin) {
749 dev_priv->ramin_size = 1 * 1024 * 1024;
750 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
751 dev_priv->ramin_size);
752 if (!dev_priv->ramin) {
753 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
754 return -ENOMEM;
755 }
756 }
757
758 nouveau_OF_copy_vbios_to_ramin(dev);
759
760 /* Special flags */
761 if (dev->pci_device == 0x01a0)
762 dev_priv->flags |= NV_NFORCE;
763 else if (dev->pci_device == 0x01f0)
764 dev_priv->flags |= NV_NFORCE2;
765
766 /* For kernel modesetting, init card now and bring up fbcon */
767 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
768 int ret = nouveau_card_init(dev);
769 if (ret)
770 return ret;
771 }
772
773 return 0;
774}
775
776static void nouveau_close(struct drm_device *dev)
777{
778 struct drm_nouveau_private *dev_priv = dev->dev_private;
779
111b459a
FJ		 780 /* In the case of an error dev_priv may not be allocated yet */
781 if (dev_priv)
6ee73861
BS		 782 nouveau_card_takedown(dev);
783}
784
785/* KMS: we need mmio at load time, not when the first drm client opens. */
786void nouveau_lastclose(struct drm_device *dev)
787{
788 if (drm_core_check_feature(dev, DRIVER_MODESET))
789 return;
790
791 nouveau_close(dev);
792}
793
794int nouveau_unload(struct drm_device *dev)
795{
796 struct drm_nouveau_private *dev_priv = dev->dev_private;
797
798 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
38651674 799 nouveau_fbcon_fini(dev);
6ee73861
BS		 800 if (dev_priv->card_type >= NV_50)
801 nv50_display_destroy(dev);
802 else
803 nv04_display_destroy(dev);
804 nouveau_close(dev);
805 }
806
807 iounmap(dev_priv->mmio);
808 iounmap(dev_priv->ramin);
809
810 kfree(dev_priv);
811 dev->dev_private = NULL;
812 return 0;
813}
814
6ee73861
BS		 815int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
816 struct drm_file *file_priv)
817{
818 struct drm_nouveau_private *dev_priv = dev->dev_private;
819 struct drm_nouveau_getparam *getparam = data;
820
821 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
822
823 switch (getparam->param) {
824 case NOUVEAU_GETPARAM_CHIPSET_ID:
825 getparam->value = dev_priv->chipset;
826 break;
827 case NOUVEAU_GETPARAM_PCI_VENDOR:
828 getparam->value = dev->pci_vendor;
829 break;
830 case NOUVEAU_GETPARAM_PCI_DEVICE:
831 getparam->value = dev->pci_device;
832 break;
833 case NOUVEAU_GETPARAM_BUS_TYPE:
834 if (drm_device_is_agp(dev))
835 getparam->value = NV_AGP;
836 else if (drm_device_is_pcie(dev))
837 getparam->value = NV_PCIE;
838 else
839 getparam->value = NV_PCI;
840 break;
841 case NOUVEAU_GETPARAM_FB_PHYSICAL:
842 getparam->value = dev_priv->fb_phys;
843 break;
844 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
845 getparam->value = dev_priv->gart_info.aper_base;
846 break;
847 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
848 if (dev->sg) {
849 getparam->value = (unsigned long)dev->sg->virtual;
850 } else {
851 NV_ERROR(dev, "Requested PCIGART address, "
852 "while no PCIGART was created\n");
853 return -EINVAL;
854 }
855 break;
856 case NOUVEAU_GETPARAM_FB_SIZE:
857 getparam->value = dev_priv->fb_available_size;
858 break;
859 case NOUVEAU_GETPARAM_AGP_SIZE:
860 getparam->value = dev_priv->gart_info.aper_size;
861 break;
862 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
863 getparam->value = dev_priv->vm_vram_base;
864 break;
69c9700b
MK		 865 case NOUVEAU_GETPARAM_GRAPH_UNITS:
866 /* NV40 and NV50 versions are quite different, but register
867 * address is the same. User is supposed to know the card
868 * family anyway... */
869 if (dev_priv->chipset >= 0x40) {
870 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
871 break;
872 }
873 /* FALLTHRU */
6ee73861
BS		 874 default:
875 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
876 return -EINVAL;
877 }
878
879 return 0;
880}
881
882int
883nouveau_ioctl_setparam(struct drm_device *dev, void *data,
884 struct drm_file *file_priv)
885{
886 struct drm_nouveau_setparam *setparam = data;
887
888 NOUVEAU_CHECK_INITIALISED_WITH_RETURN;
889
890 switch (setparam->param) {
891 default:
892 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
893 return -EINVAL;
894 }
895
896 return 0;
897}
898
899/* Wait until (value(reg) & mask) == val, up until timeout has hit */
900bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
901 uint32_t reg, uint32_t mask, uint32_t val)
902{
903 struct drm_nouveau_private *dev_priv = dev->dev_private;
904 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
905 uint64_t start = ptimer->read(dev);
906
907 do {
908 if ((nv_rd32(dev, reg) & mask) == val)
909 return true;
910 } while (ptimer->read(dev) - start < timeout);
911
912 return false;
913}
914
915/* Waits for PGRAPH to go completely idle */
916bool nouveau_wait_for_idle(struct drm_device *dev)
917{
918 if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
919 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
920 nv_rd32(dev, NV04_PGRAPH_STATUS));
921 return false;
922 }
923
924 return true;
925}
926
Linux kernel - Deliverables
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