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drm/nv30: Workaround dual TMDS brain damage.
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nouveau_state.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/swab.h>
5a0e3ad6 27#include <linux/slab.h>
6ee73861
BS		 28#include "drmP.h"
29#include "drm.h"
30#include "drm_sarea.h"
31#include "drm_crtc_helper.h"
32#include <linux/vgaarb.h>
6a9ee8af 33#include <linux/vga_switcheroo.h>
6ee73861
BS		 34
35#include "nouveau_drv.h"
36#include "nouveau_drm.h"
38651674 37#include "nouveau_fbcon.h"
6ee73861
BS		 38#include "nv50_display.h"
39
6ee73861 40static void nouveau_stub_takedown(struct drm_device *dev) {}
ee2e0131 41static int nouveau_stub_init(struct drm_device *dev) { return 0; }
6ee73861
BS		 42
43static int nouveau_init_engine_ptrs(struct drm_device *dev)
44{
45 struct drm_nouveau_private *dev_priv = dev->dev_private;
46 struct nouveau_engine *engine = &dev_priv->engine;
47
48 switch (dev_priv->chipset & 0xf0) {
49 case 0x00:
50 engine->instmem.init = nv04_instmem_init;
51 engine->instmem.takedown = nv04_instmem_takedown;
52 engine->instmem.suspend = nv04_instmem_suspend;
53 engine->instmem.resume = nv04_instmem_resume;
54 engine->instmem.populate = nv04_instmem_populate;
55 engine->instmem.clear = nv04_instmem_clear;
56 engine->instmem.bind = nv04_instmem_bind;
57 engine->instmem.unbind = nv04_instmem_unbind;
f56cb86f 58 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 59 engine->mc.init = nv04_mc_init;
60 engine->mc.takedown = nv04_mc_takedown;
61 engine->timer.init = nv04_timer_init;
62 engine->timer.read = nv04_timer_read;
63 engine->timer.takedown = nv04_timer_takedown;
64 engine->fb.init = nv04_fb_init;
65 engine->fb.takedown = nv04_fb_takedown;
66 engine->graph.grclass = nv04_graph_grclass;
67 engine->graph.init = nv04_graph_init;
68 engine->graph.takedown = nv04_graph_takedown;
69 engine->graph.fifo_access = nv04_graph_fifo_access;
70 engine->graph.channel = nv04_graph_channel;
71 engine->graph.create_context = nv04_graph_create_context;
72 engine->graph.destroy_context = nv04_graph_destroy_context;
73 engine->graph.load_context = nv04_graph_load_context;
74 engine->graph.unload_context = nv04_graph_unload_context;
75 engine->fifo.channels = 16;
76 engine->fifo.init = nv04_fifo_init;
77 engine->fifo.takedown = nouveau_stub_takedown;
78 engine->fifo.disable = nv04_fifo_disable;
79 engine->fifo.enable = nv04_fifo_enable;
80 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 81 engine->fifo.cache_flush = nv04_fifo_cache_flush;
82 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 83 engine->fifo.channel_id = nv04_fifo_channel_id;
84 engine->fifo.create_context = nv04_fifo_create_context;
85 engine->fifo.destroy_context = nv04_fifo_destroy_context;
86 engine->fifo.load_context = nv04_fifo_load_context;
87 engine->fifo.unload_context = nv04_fifo_unload_context;
c88c2e06
FJ		 88 engine->display.early_init = nv04_display_early_init;
89 engine->display.late_takedown = nv04_display_late_takedown;
90 engine->display.create = nv04_display_create;
91 engine->display.init = nv04_display_init;
92 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 93 engine->gpio.init = nouveau_stub_init;
94 engine->gpio.takedown = nouveau_stub_takedown;
95 engine->gpio.get = NULL;
96 engine->gpio.set = NULL;
97 engine->gpio.irq_enable = NULL;
6ee73861
BS		 98 break;
99 case 0x10:
100 engine->instmem.init = nv04_instmem_init;
101 engine->instmem.takedown = nv04_instmem_takedown;
102 engine->instmem.suspend = nv04_instmem_suspend;
103 engine->instmem.resume = nv04_instmem_resume;
104 engine->instmem.populate = nv04_instmem_populate;
105 engine->instmem.clear = nv04_instmem_clear;
106 engine->instmem.bind = nv04_instmem_bind;
107 engine->instmem.unbind = nv04_instmem_unbind;
f56cb86f 108 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 109 engine->mc.init = nv04_mc_init;
110 engine->mc.takedown = nv04_mc_takedown;
111 engine->timer.init = nv04_timer_init;
112 engine->timer.read = nv04_timer_read;
113 engine->timer.takedown = nv04_timer_takedown;
114 engine->fb.init = nv10_fb_init;
115 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 116 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 117 engine->graph.grclass = nv10_graph_grclass;
118 engine->graph.init = nv10_graph_init;
119 engine->graph.takedown = nv10_graph_takedown;
120 engine->graph.channel = nv10_graph_channel;
121 engine->graph.create_context = nv10_graph_create_context;
122 engine->graph.destroy_context = nv10_graph_destroy_context;
123 engine->graph.fifo_access = nv04_graph_fifo_access;
124 engine->graph.load_context = nv10_graph_load_context;
125 engine->graph.unload_context = nv10_graph_unload_context;
cb00f7c1 126 engine->graph.set_region_tiling = nv10_graph_set_region_tiling;
6ee73861
BS		 127 engine->fifo.channels = 32;
128 engine->fifo.init = nv10_fifo_init;
129 engine->fifo.takedown = nouveau_stub_takedown;
130 engine->fifo.disable = nv04_fifo_disable;
131 engine->fifo.enable = nv04_fifo_enable;
132 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 133 engine->fifo.cache_flush = nv04_fifo_cache_flush;
134 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 135 engine->fifo.channel_id = nv10_fifo_channel_id;
136 engine->fifo.create_context = nv10_fifo_create_context;
137 engine->fifo.destroy_context = nv10_fifo_destroy_context;
138 engine->fifo.load_context = nv10_fifo_load_context;
139 engine->fifo.unload_context = nv10_fifo_unload_context;
c88c2e06
FJ		 140 engine->display.early_init = nv04_display_early_init;
141 engine->display.late_takedown = nv04_display_late_takedown;
142 engine->display.create = nv04_display_create;
143 engine->display.init = nv04_display_init;
144 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 145 engine->gpio.init = nouveau_stub_init;
146 engine->gpio.takedown = nouveau_stub_takedown;
147 engine->gpio.get = nv10_gpio_get;
148 engine->gpio.set = nv10_gpio_set;
149 engine->gpio.irq_enable = NULL;
6ee73861
BS		 150 break;
151 case 0x20:
152 engine->instmem.init = nv04_instmem_init;
153 engine->instmem.takedown = nv04_instmem_takedown;
154 engine->instmem.suspend = nv04_instmem_suspend;
155 engine->instmem.resume = nv04_instmem_resume;
156 engine->instmem.populate = nv04_instmem_populate;
157 engine->instmem.clear = nv04_instmem_clear;
158 engine->instmem.bind = nv04_instmem_bind;
159 engine->instmem.unbind = nv04_instmem_unbind;
f56cb86f 160 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 161 engine->mc.init = nv04_mc_init;
162 engine->mc.takedown = nv04_mc_takedown;
163 engine->timer.init = nv04_timer_init;
164 engine->timer.read = nv04_timer_read;
165 engine->timer.takedown = nv04_timer_takedown;
166 engine->fb.init = nv10_fb_init;
167 engine->fb.takedown = nv10_fb_takedown;
cb00f7c1 168 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 169 engine->graph.grclass = nv20_graph_grclass;
170 engine->graph.init = nv20_graph_init;
171 engine->graph.takedown = nv20_graph_takedown;
172 engine->graph.channel = nv10_graph_channel;
173 engine->graph.create_context = nv20_graph_create_context;
174 engine->graph.destroy_context = nv20_graph_destroy_context;
175 engine->graph.fifo_access = nv04_graph_fifo_access;
176 engine->graph.load_context = nv20_graph_load_context;
177 engine->graph.unload_context = nv20_graph_unload_context;
cb00f7c1 178 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
6ee73861
BS		 179 engine->fifo.channels = 32;
180 engine->fifo.init = nv10_fifo_init;
181 engine->fifo.takedown = nouveau_stub_takedown;
182 engine->fifo.disable = nv04_fifo_disable;
183 engine->fifo.enable = nv04_fifo_enable;
184 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 185 engine->fifo.cache_flush = nv04_fifo_cache_flush;
186 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 187 engine->fifo.channel_id = nv10_fifo_channel_id;
188 engine->fifo.create_context = nv10_fifo_create_context;
189 engine->fifo.destroy_context = nv10_fifo_destroy_context;
190 engine->fifo.load_context = nv10_fifo_load_context;
191 engine->fifo.unload_context = nv10_fifo_unload_context;
c88c2e06
FJ		 192 engine->display.early_init = nv04_display_early_init;
193 engine->display.late_takedown = nv04_display_late_takedown;
194 engine->display.create = nv04_display_create;
195 engine->display.init = nv04_display_init;
196 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 197 engine->gpio.init = nouveau_stub_init;
198 engine->gpio.takedown = nouveau_stub_takedown;
199 engine->gpio.get = nv10_gpio_get;
200 engine->gpio.set = nv10_gpio_set;
201 engine->gpio.irq_enable = NULL;
6ee73861
BS		 202 break;
203 case 0x30:
204 engine->instmem.init = nv04_instmem_init;
205 engine->instmem.takedown = nv04_instmem_takedown;
206 engine->instmem.suspend = nv04_instmem_suspend;
207 engine->instmem.resume = nv04_instmem_resume;
208 engine->instmem.populate = nv04_instmem_populate;
209 engine->instmem.clear = nv04_instmem_clear;
210 engine->instmem.bind = nv04_instmem_bind;
211 engine->instmem.unbind = nv04_instmem_unbind;
f56cb86f 212 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 213 engine->mc.init = nv04_mc_init;
214 engine->mc.takedown = nv04_mc_takedown;
215 engine->timer.init = nv04_timer_init;
216 engine->timer.read = nv04_timer_read;
217 engine->timer.takedown = nv04_timer_takedown;
8bded189
FJ		 218 engine->fb.init = nv30_fb_init;
219 engine->fb.takedown = nv30_fb_takedown;
cb00f7c1 220 engine->fb.set_region_tiling = nv10_fb_set_region_tiling;
6ee73861
BS		 221 engine->graph.grclass = nv30_graph_grclass;
222 engine->graph.init = nv30_graph_init;
223 engine->graph.takedown = nv20_graph_takedown;
224 engine->graph.fifo_access = nv04_graph_fifo_access;
225 engine->graph.channel = nv10_graph_channel;
226 engine->graph.create_context = nv20_graph_create_context;
227 engine->graph.destroy_context = nv20_graph_destroy_context;
228 engine->graph.load_context = nv20_graph_load_context;
229 engine->graph.unload_context = nv20_graph_unload_context;
cb00f7c1 230 engine->graph.set_region_tiling = nv20_graph_set_region_tiling;
6ee73861
BS		 231 engine->fifo.channels = 32;
232 engine->fifo.init = nv10_fifo_init;
233 engine->fifo.takedown = nouveau_stub_takedown;
234 engine->fifo.disable = nv04_fifo_disable;
235 engine->fifo.enable = nv04_fifo_enable;
236 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 237 engine->fifo.cache_flush = nv04_fifo_cache_flush;
238 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 239 engine->fifo.channel_id = nv10_fifo_channel_id;
240 engine->fifo.create_context = nv10_fifo_create_context;
241 engine->fifo.destroy_context = nv10_fifo_destroy_context;
242 engine->fifo.load_context = nv10_fifo_load_context;
243 engine->fifo.unload_context = nv10_fifo_unload_context;
c88c2e06
FJ		 244 engine->display.early_init = nv04_display_early_init;
245 engine->display.late_takedown = nv04_display_late_takedown;
246 engine->display.create = nv04_display_create;
247 engine->display.init = nv04_display_init;
248 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 249 engine->gpio.init = nouveau_stub_init;
250 engine->gpio.takedown = nouveau_stub_takedown;
251 engine->gpio.get = nv10_gpio_get;
252 engine->gpio.set = nv10_gpio_set;
253 engine->gpio.irq_enable = NULL;
6ee73861
BS		 254 break;
255 case 0x40:
256 case 0x60:
257 engine->instmem.init = nv04_instmem_init;
258 engine->instmem.takedown = nv04_instmem_takedown;
259 engine->instmem.suspend = nv04_instmem_suspend;
260 engine->instmem.resume = nv04_instmem_resume;
261 engine->instmem.populate = nv04_instmem_populate;
262 engine->instmem.clear = nv04_instmem_clear;
263 engine->instmem.bind = nv04_instmem_bind;
264 engine->instmem.unbind = nv04_instmem_unbind;
f56cb86f 265 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 266 engine->mc.init = nv40_mc_init;
267 engine->mc.takedown = nv40_mc_takedown;
268 engine->timer.init = nv04_timer_init;
269 engine->timer.read = nv04_timer_read;
270 engine->timer.takedown = nv04_timer_takedown;
271 engine->fb.init = nv40_fb_init;
272 engine->fb.takedown = nv40_fb_takedown;
cb00f7c1 273 engine->fb.set_region_tiling = nv40_fb_set_region_tiling;
6ee73861
BS		 274 engine->graph.grclass = nv40_graph_grclass;
275 engine->graph.init = nv40_graph_init;
276 engine->graph.takedown = nv40_graph_takedown;
277 engine->graph.fifo_access = nv04_graph_fifo_access;
278 engine->graph.channel = nv40_graph_channel;
279 engine->graph.create_context = nv40_graph_create_context;
280 engine->graph.destroy_context = nv40_graph_destroy_context;
281 engine->graph.load_context = nv40_graph_load_context;
282 engine->graph.unload_context = nv40_graph_unload_context;
cb00f7c1 283 engine->graph.set_region_tiling = nv40_graph_set_region_tiling;
6ee73861
BS		 284 engine->fifo.channels = 32;
285 engine->fifo.init = nv40_fifo_init;
286 engine->fifo.takedown = nouveau_stub_takedown;
287 engine->fifo.disable = nv04_fifo_disable;
288 engine->fifo.enable = nv04_fifo_enable;
289 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12
FJ		 290 engine->fifo.cache_flush = nv04_fifo_cache_flush;
291 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 292 engine->fifo.channel_id = nv10_fifo_channel_id;
293 engine->fifo.create_context = nv40_fifo_create_context;
294 engine->fifo.destroy_context = nv40_fifo_destroy_context;
295 engine->fifo.load_context = nv40_fifo_load_context;
296 engine->fifo.unload_context = nv40_fifo_unload_context;
c88c2e06
FJ		 297 engine->display.early_init = nv04_display_early_init;
298 engine->display.late_takedown = nv04_display_late_takedown;
299 engine->display.create = nv04_display_create;
300 engine->display.init = nv04_display_init;
301 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 302 engine->gpio.init = nouveau_stub_init;
303 engine->gpio.takedown = nouveau_stub_takedown;
304 engine->gpio.get = nv10_gpio_get;
305 engine->gpio.set = nv10_gpio_set;
306 engine->gpio.irq_enable = NULL;
6ee73861
BS		 307 break;
308 case 0x50:
309 case 0x80: /* gotta love NVIDIA's consistency.. */
310 case 0x90:
311 case 0xA0:
312 engine->instmem.init = nv50_instmem_init;
313 engine->instmem.takedown = nv50_instmem_takedown;
314 engine->instmem.suspend = nv50_instmem_suspend;
315 engine->instmem.resume = nv50_instmem_resume;
316 engine->instmem.populate = nv50_instmem_populate;
317 engine->instmem.clear = nv50_instmem_clear;
318 engine->instmem.bind = nv50_instmem_bind;
319 engine->instmem.unbind = nv50_instmem_unbind;
734ee835
BS		 320 if (dev_priv->chipset == 0x50)
321 engine->instmem.flush = nv50_instmem_flush;
322 else
323 engine->instmem.flush = nv84_instmem_flush;
6ee73861
BS		 324 engine->mc.init = nv50_mc_init;
325 engine->mc.takedown = nv50_mc_takedown;
326 engine->timer.init = nv04_timer_init;
327 engine->timer.read = nv04_timer_read;
328 engine->timer.takedown = nv04_timer_takedown;
304424e1
MK		 329 engine->fb.init = nv50_fb_init;
330 engine->fb.takedown = nv50_fb_takedown;
6ee73861
BS		 331 engine->graph.grclass = nv50_graph_grclass;
332 engine->graph.init = nv50_graph_init;
333 engine->graph.takedown = nv50_graph_takedown;
334 engine->graph.fifo_access = nv50_graph_fifo_access;
335 engine->graph.channel = nv50_graph_channel;
336 engine->graph.create_context = nv50_graph_create_context;
337 engine->graph.destroy_context = nv50_graph_destroy_context;
338 engine->graph.load_context = nv50_graph_load_context;
339 engine->graph.unload_context = nv50_graph_unload_context;
340 engine->fifo.channels = 128;
341 engine->fifo.init = nv50_fifo_init;
342 engine->fifo.takedown = nv50_fifo_takedown;
343 engine->fifo.disable = nv04_fifo_disable;
344 engine->fifo.enable = nv04_fifo_enable;
345 engine->fifo.reassign = nv04_fifo_reassign;
346 engine->fifo.channel_id = nv50_fifo_channel_id;
347 engine->fifo.create_context = nv50_fifo_create_context;
348 engine->fifo.destroy_context = nv50_fifo_destroy_context;
349 engine->fifo.load_context = nv50_fifo_load_context;
350 engine->fifo.unload_context = nv50_fifo_unload_context;
c88c2e06
FJ		 351 engine->display.early_init = nv50_display_early_init;
352 engine->display.late_takedown = nv50_display_late_takedown;
353 engine->display.create = nv50_display_create;
354 engine->display.init = nv50_display_init;
355 engine->display.destroy = nv50_display_destroy;
ee2e0131
BS		 356 engine->gpio.init = nv50_gpio_init;
357 engine->gpio.takedown = nouveau_stub_takedown;
358 engine->gpio.get = nv50_gpio_get;
359 engine->gpio.set = nv50_gpio_set;
360 engine->gpio.irq_enable = nv50_gpio_irq_enable;
6ee73861
BS		 361 break;
362 default:
363 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
364 return 1;
365 }
366
367 return 0;
368}
369
370static unsigned int
371nouveau_vga_set_decode(void *priv, bool state)
372{
9967b948
MK		 373 struct drm_device *dev = priv;
374 struct drm_nouveau_private *dev_priv = dev->dev_private;
375
376 if (dev_priv->chipset >= 0x40)
377 nv_wr32(dev, 0x88054, state);
378 else
379 nv_wr32(dev, 0x1854, state);
380
6ee73861
BS		 381 if (state)
382 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
383 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
384 else
385 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
386}
387
0735f62e
BS		 388static int
389nouveau_card_init_channel(struct drm_device *dev)
390{
391 struct drm_nouveau_private *dev_priv = dev->dev_private;
392 struct nouveau_gpuobj *gpuobj;
393 int ret;
394
395 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
396 (struct drm_file *)-2,
397 NvDmaFB, NvDmaTT);
398 if (ret)
399 return ret;
400
401 gpuobj = NULL;
402 ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY,
a76fb4e8 403 0, dev_priv->vram_size,
0735f62e
BS		 404 NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM,
405 &gpuobj);
406 if (ret)
407 goto out_err;
408
409 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaVRAM,
410 gpuobj, NULL);
411 if (ret)
412 goto out_err;
413
414 gpuobj = NULL;
415 ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0,
416 dev_priv->gart_info.aper_size,
417 NV_DMA_ACCESS_RW, &gpuobj, NULL);
418 if (ret)
419 goto out_err;
420
421 ret = nouveau_gpuobj_ref_add(dev, dev_priv->channel, NvDmaGART,
422 gpuobj, NULL);
423 if (ret)
424 goto out_err;
425
426 return 0;
427out_err:
428 nouveau_gpuobj_del(dev, &gpuobj);
429 nouveau_channel_free(dev_priv->channel);
430 dev_priv->channel = NULL;
431 return ret;
432}
433
6a9ee8af
DA		 434static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
435 enum vga_switcheroo_state state)
436{
fbf81762 437 struct drm_device *dev = pci_get_drvdata(pdev);
6a9ee8af
DA		 438 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
439 if (state == VGA_SWITCHEROO_ON) {
440 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
441 nouveau_pci_resume(pdev);
fbf81762 442 drm_kms_helper_poll_enable(dev);
6a9ee8af
DA		 443 } else {
444 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
fbf81762 445 drm_kms_helper_poll_disable(dev);
6a9ee8af
DA		 446 nouveau_pci_suspend(pdev, pmm);
447 }
448}
449
450static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
451{
452 struct drm_device *dev = pci_get_drvdata(pdev);
453 bool can_switch;
454
455 spin_lock(&dev->count_lock);
456 can_switch = (dev->open_count == 0);
457 spin_unlock(&dev->count_lock);
458 return can_switch;
459}
460
6ee73861
BS		 461int
462nouveau_card_init(struct drm_device *dev)
463{
464 struct drm_nouveau_private *dev_priv = dev->dev_private;
465 struct nouveau_engine *engine;
6ee73861
BS		 466 int ret;
467
6ee73861 468 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
6a9ee8af
DA		 469 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
470 nouveau_switcheroo_can_switch);
6ee73861
BS		 471
472 /* Initialise internal driver API hooks */
473 ret = nouveau_init_engine_ptrs(dev);
474 if (ret)
c5804be0 475 goto out;
6ee73861 476 engine = &dev_priv->engine;
ff9e5279 477 spin_lock_init(&dev_priv->context_switch_lock);
6ee73861 478
c88c2e06
FJ		 479 /* Make the CRTCs and I2C buses accessible */
480 ret = engine->display.early_init(dev);
481 if (ret)
482 goto out;
483
6ee73861 484 /* Parse BIOS tables / Run init tables if card not POSTed */
cd0b072f
BS		 485 ret = nouveau_bios_init(dev);
486 if (ret)
c88c2e06 487 goto out_display_early;
6ee73861 488
a76fb4e8
BS		 489 ret = nouveau_mem_detect(dev);
490 if (ret)
491 goto out_bios;
492
6ee73861
BS		 493 ret = nouveau_gpuobj_early_init(dev);
494 if (ret)
c5804be0 495 goto out_bios;
6ee73861
BS		 496
497 /* Initialise instance memory, must happen before mem_init so we
498 * know exactly how much VRAM we're able to use for "normal"
499 * purposes.
500 */
501 ret = engine->instmem.init(dev);
502 if (ret)
c5804be0 503 goto out_gpuobj_early;
6ee73861
BS		 504
505 /* Setup the memory manager */
506 ret = nouveau_mem_init(dev);
507 if (ret)
c5804be0 508 goto out_instmem;
6ee73861
BS		 509
510 ret = nouveau_gpuobj_init(dev);
511 if (ret)
c5804be0 512 goto out_mem;
6ee73861
BS		 513
514 /* PMC */
515 ret = engine->mc.init(dev);
516 if (ret)
c5804be0 517 goto out_gpuobj;
6ee73861 518
ee2e0131
BS		 519 /* PGPIO */
520 ret = engine->gpio.init(dev);
521 if (ret)
522 goto out_mc;
523
6ee73861
BS		 524 /* PTIMER */
525 ret = engine->timer.init(dev);
526 if (ret)
ee2e0131 527 goto out_gpio;
6ee73861
BS		 528
529 /* PFB */
530 ret = engine->fb.init(dev);
531 if (ret)
c5804be0 532 goto out_timer;
6ee73861 533
a32ed69d
MK		 534 if (nouveau_noaccel)
535 engine->graph.accel_blocked = true;
536 else {
537 /* PGRAPH */
538 ret = engine->graph.init(dev);
539 if (ret)
540 goto out_fb;
6ee73861 541
a32ed69d
MK		 542 /* PFIFO */
543 ret = engine->fifo.init(dev);
544 if (ret)
545 goto out_graph;
546 }
6ee73861 547
c88c2e06 548 ret = engine->display.create(dev);
e88efe05
BS		 549 if (ret)
550 goto out_fifo;
551
6ee73861
BS		 552 /* this call irq_preinstall, register irq handler and
553 * call irq_postinstall
554 */
555 ret = drm_irq_install(dev);
556 if (ret)
e88efe05 557 goto out_display;
6ee73861
BS		 558
559 ret = drm_vblank_init(dev, 0);
560 if (ret)
c5804be0 561 goto out_irq;
6ee73861
BS		 562
563 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
564
0735f62e
BS		 565 if (!engine->graph.accel_blocked) {
566 ret = nouveau_card_init_channel(dev);
567 if (ret)
568 goto out_irq;
6ee73861
BS		 569 }
570
6ee73861
BS		 571 ret = nouveau_backlight_init(dev);
572 if (ret)
573 NV_ERROR(dev, "Error %d registering backlight\n", ret);
574
cd0b072f
BS		 575 nouveau_fbcon_init(dev);
576 drm_kms_helper_poll_init(dev);
6ee73861 577 return 0;
c5804be0
MK		 578
579out_irq:
580 drm_irq_uninstall(dev);
e88efe05 581out_display:
c88c2e06 582 engine->display.destroy(dev);
c5804be0 583out_fifo:
a32ed69d
MK		 584 if (!nouveau_noaccel)
585 engine->fifo.takedown(dev);
c5804be0 586out_graph:
a32ed69d
MK		 587 if (!nouveau_noaccel)
588 engine->graph.takedown(dev);
c5804be0
MK		 589out_fb:
590 engine->fb.takedown(dev);
591out_timer:
592 engine->timer.takedown(dev);
ee2e0131
BS		 593out_gpio:
594 engine->gpio.takedown(dev);
c5804be0
MK		 595out_mc:
596 engine->mc.takedown(dev);
597out_gpuobj:
598 nouveau_gpuobj_takedown(dev);
599out_mem:
78bb3512 600 nouveau_sgdma_takedown(dev);
c5804be0
MK		 601 nouveau_mem_close(dev);
602out_instmem:
603 engine->instmem.takedown(dev);
604out_gpuobj_early:
605 nouveau_gpuobj_late_takedown(dev);
606out_bios:
607 nouveau_bios_takedown(dev);
c88c2e06
FJ		 608out_display_early:
609 engine->display.late_takedown(dev);
c5804be0
MK		 610out:
611 vga_client_register(dev->pdev, NULL, NULL, NULL);
612 return ret;
6ee73861
BS		 613}
614
615static void nouveau_card_takedown(struct drm_device *dev)
616{
617 struct drm_nouveau_private *dev_priv = dev->dev_private;
618 struct nouveau_engine *engine = &dev_priv->engine;
619
b6d3d871 620 nouveau_backlight_exit(dev);
38651674 621
b6d3d871
BS		 622 if (dev_priv->channel) {
623 nouveau_channel_free(dev_priv->channel);
624 dev_priv->channel = NULL;
625 }
6ee73861 626
b6d3d871
BS		 627 if (!nouveau_noaccel) {
628 engine->fifo.takedown(dev);
629 engine->graph.takedown(dev);
630 }
631 engine->fb.takedown(dev);
632 engine->timer.takedown(dev);
ee2e0131 633 engine->gpio.takedown(dev);
b6d3d871 634 engine->mc.takedown(dev);
c88c2e06 635 engine->display.late_takedown(dev);
6ee73861 636
b6d3d871
BS		 637 mutex_lock(&dev->struct_mutex);
638 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
639 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
640 mutex_unlock(&dev->struct_mutex);
641 nouveau_sgdma_takedown(dev);
6ee73861 642
b6d3d871
BS		 643 nouveau_gpuobj_takedown(dev);
644 nouveau_mem_close(dev);
645 engine->instmem.takedown(dev);
6ee73861 646
b6d3d871 647 drm_irq_uninstall(dev);
6ee73861 648
b6d3d871
BS		 649 nouveau_gpuobj_late_takedown(dev);
650 nouveau_bios_takedown(dev);
6ee73861 651
b6d3d871 652 vga_client_register(dev->pdev, NULL, NULL, NULL);
6ee73861
BS		 653}
654
655/* here a client dies, release the stuff that was allocated for its
656 * file_priv */
657void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
658{
659 nouveau_channel_cleanup(dev, file_priv);
660}
661
662/* first module load, setup the mmio/fb mapping */
663/* KMS: we need mmio at load time, not when the first drm client opens. */
664int nouveau_firstopen(struct drm_device *dev)
665{
666 return 0;
667}
668
669/* if we have an OF card, copy vbios to RAMIN */
670static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
671{
672#if defined(__powerpc__)
673 int size, i;
674 const uint32_t *bios;
675 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
676 if (!dn) {
677 NV_INFO(dev, "Unable to get the OF node\n");
678 return;
679 }
680
681 bios = of_get_property(dn, "NVDA,BMP", &size);
682 if (bios) {
683 for (i = 0; i < size; i += 4)
684 nv_wi32(dev, i, bios[i/4]);
685 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
686 } else {
687 NV_INFO(dev, "Unable to get the OF bios\n");
688 }
689#endif
690}
691
06415c56
MS		 692static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
693{
694 struct pci_dev *pdev = dev->pdev;
695 struct apertures_struct *aper = alloc_apertures(3);
696 if (!aper)
697 return NULL;
698
699 aper->ranges[0].base = pci_resource_start(pdev, 1);
700 aper->ranges[0].size = pci_resource_len(pdev, 1);
701 aper->count = 1;
702
703 if (pci_resource_len(pdev, 2)) {
704 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
705 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
706 aper->count++;
707 }
708
709 if (pci_resource_len(pdev, 3)) {
710 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
711 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
712 aper->count++;
713 }
714
715 return aper;
716}
717
718static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
719{
720 struct drm_nouveau_private *dev_priv = dev->dev_private;
3b9676e7 721 bool primary = false;
06415c56
MS		 722 dev_priv->apertures = nouveau_get_apertures(dev);
723 if (!dev_priv->apertures)
724 return -ENOMEM;
725
3b9676e7
MS		 726#ifdef CONFIG_X86
727 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
728#endif
729
730 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
06415c56
MS		 731 return 0;
732}
733
6ee73861
BS		 734int nouveau_load(struct drm_device *dev, unsigned long flags)
735{
736 struct drm_nouveau_private *dev_priv;
737 uint32_t reg0;
738 resource_size_t mmio_start_offs;
cd0b072f 739 int ret;
6ee73861
BS		 740
741 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
a0d069ea
DC		 742 if (!dev_priv) {
743 ret = -ENOMEM;
744 goto err_out;
745 }
6ee73861
BS		 746 dev->dev_private = dev_priv;
747 dev_priv->dev = dev;
748
749 dev_priv->flags = flags & NOUVEAU_FLAGS;
6ee73861
BS		 750
751 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
752 dev->pci_vendor, dev->pci_device, dev->pdev->class);
753
6ee73861 754 dev_priv->wq = create_workqueue("nouveau");
a0d069ea
DC		 755 if (!dev_priv->wq) {
756 ret = -EINVAL;
757 goto err_priv;
758 }
6ee73861
BS		 759
760 /* resource 0 is mmio regs */
761 /* resource 1 is linear FB */
762 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
763 /* resource 6 is bios */
764
765 /* map the mmio regs */
766 mmio_start_offs = pci_resource_start(dev->pdev, 0);
767 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
768 if (!dev_priv->mmio) {
769 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
770 "Please report your setup to " DRIVER_EMAIL "\n");
a0d069ea
DC		 771 ret = -EINVAL;
772 goto err_wq;
6ee73861
BS		 773 }
774 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
775 (unsigned long long)mmio_start_offs);
776
777#ifdef __BIG_ENDIAN
778 /* Put the card in BE mode if it's not */
779 if (nv_rd32(dev, NV03_PMC_BOOT_1))
780 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
781
782 DRM_MEMORYBARRIER();
783#endif
784
785 /* Time to determine the card architecture */
786 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
787
788 /* We're dealing with >=NV10 */
789 if ((reg0 & 0x0f000000) > 0) {
790 /* Bit 27-20 contain the architecture in hex */
791 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
792 /* NV04 or NV05 */
793 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1dee7a93
BS		 794 if (reg0 & 0x00f00000)
795 dev_priv->chipset = 0x05;
796 else
797 dev_priv->chipset = 0x04;
6ee73861
BS		 798 } else
799 dev_priv->chipset = 0xff;
800
801 switch (dev_priv->chipset & 0xf0) {
802 case 0x00:
803 case 0x10:
804 case 0x20:
805 case 0x30:
806 dev_priv->card_type = dev_priv->chipset & 0xf0;
807 break;
808 case 0x40:
809 case 0x60:
810 dev_priv->card_type = NV_40;
811 break;
812 case 0x50:
813 case 0x80:
814 case 0x90:
815 case 0xa0:
816 dev_priv->card_type = NV_50;
817 break;
818 default:
819 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
a0d069ea
DC		 820 ret = -EINVAL;
821 goto err_mmio;
6ee73861
BS		 822 }
823
824 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
825 dev_priv->card_type, reg0);
826
cd0b072f
BS		 827 ret = nouveau_remove_conflicting_drivers(dev);
828 if (ret)
a0d069ea 829 goto err_mmio;
06415c56 830
6d696305 831 /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */
6ee73861
BS		 832 if (dev_priv->card_type >= NV_40) {
833 int ramin_bar = 2;
834 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
835 ramin_bar = 3;
836
837 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
6d696305
BS		 838 dev_priv->ramin =
839 ioremap(pci_resource_start(dev->pdev, ramin_bar),
6ee73861
BS		 840 dev_priv->ramin_size);
841 if (!dev_priv->ramin) {
6d696305 842 NV_ERROR(dev, "Failed to PRAMIN BAR");
a0d069ea
DC		 843 ret = -ENOMEM;
844 goto err_mmio;
6ee73861 845 }
6d696305 846 } else {
6ee73861
BS		 847 dev_priv->ramin_size = 1 * 1024 * 1024;
848 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
6d696305 849 dev_priv->ramin_size);
6ee73861
BS		 850 if (!dev_priv->ramin) {
851 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
a0d069ea
DC		 852 ret = -ENOMEM;
853 goto err_mmio;
6ee73861
BS		 854 }
855 }
856
857 nouveau_OF_copy_vbios_to_ramin(dev);
858
859 /* Special flags */
860 if (dev->pci_device == 0x01a0)
861 dev_priv->flags |= NV_NFORCE;
862 else if (dev->pci_device == 0x01f0)
863 dev_priv->flags |= NV_NFORCE2;
864
865 /* For kernel modesetting, init card now and bring up fbcon */
cd0b072f
BS		 866 ret = nouveau_card_init(dev);
867 if (ret)
a0d069ea 868 goto err_ramin;
6ee73861
BS		 869
870 return 0;
a0d069ea
DC		 871
872err_ramin:
873 iounmap(dev_priv->ramin);
874err_mmio:
875 iounmap(dev_priv->mmio);
876err_wq:
877 destroy_workqueue(dev_priv->wq);
878err_priv:
879 kfree(dev_priv);
880 dev->dev_private = NULL;
881err_out:
882 return ret;
6ee73861
BS		 883}
884
6ee73861
BS		 885void nouveau_lastclose(struct drm_device *dev)
886{
6ee73861
BS		 887}
888
889int nouveau_unload(struct drm_device *dev)
890{
891 struct drm_nouveau_private *dev_priv = dev->dev_private;
c88c2e06 892 struct nouveau_engine *engine = &dev_priv->engine;
6ee73861 893
cd0b072f
BS		 894 drm_kms_helper_poll_fini(dev);
895 nouveau_fbcon_fini(dev);
c88c2e06 896 engine->display.destroy(dev);
cd0b072f 897 nouveau_card_takedown(dev);
6ee73861
BS		 898
899 iounmap(dev_priv->mmio);
900 iounmap(dev_priv->ramin);
901
902 kfree(dev_priv);
903 dev->dev_private = NULL;
904 return 0;
905}
906
6ee73861
BS		 907int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
908 struct drm_file *file_priv)
909{
910 struct drm_nouveau_private *dev_priv = dev->dev_private;
911 struct drm_nouveau_getparam *getparam = data;
912
6ee73861
BS		 913 switch (getparam->param) {
914 case NOUVEAU_GETPARAM_CHIPSET_ID:
915 getparam->value = dev_priv->chipset;
916 break;
917 case NOUVEAU_GETPARAM_PCI_VENDOR:
918 getparam->value = dev->pci_vendor;
919 break;
920 case NOUVEAU_GETPARAM_PCI_DEVICE:
921 getparam->value = dev->pci_device;
922 break;
923 case NOUVEAU_GETPARAM_BUS_TYPE:
924 if (drm_device_is_agp(dev))
925 getparam->value = NV_AGP;
926 else if (drm_device_is_pcie(dev))
927 getparam->value = NV_PCIE;
928 else
929 getparam->value = NV_PCI;
930 break;
931 case NOUVEAU_GETPARAM_FB_PHYSICAL:
932 getparam->value = dev_priv->fb_phys;
933 break;
934 case NOUVEAU_GETPARAM_AGP_PHYSICAL:
935 getparam->value = dev_priv->gart_info.aper_base;
936 break;
937 case NOUVEAU_GETPARAM_PCI_PHYSICAL:
938 if (dev->sg) {
939 getparam->value = (unsigned long)dev->sg->virtual;
940 } else {
941 NV_ERROR(dev, "Requested PCIGART address, "
942 "while no PCIGART was created\n");
943 return -EINVAL;
944 }
945 break;
946 case NOUVEAU_GETPARAM_FB_SIZE:
947 getparam->value = dev_priv->fb_available_size;
948 break;
949 case NOUVEAU_GETPARAM_AGP_SIZE:
950 getparam->value = dev_priv->gart_info.aper_size;
951 break;
952 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
953 getparam->value = dev_priv->vm_vram_base;
954 break;
7fc74f17
MK		 955 case NOUVEAU_GETPARAM_PTIMER_TIME:
956 getparam->value = dev_priv->engine.timer.read(dev);
957 break;
69c9700b
MK		 958 case NOUVEAU_GETPARAM_GRAPH_UNITS:
959 /* NV40 and NV50 versions are quite different, but register
960 * address is the same. User is supposed to know the card
961 * family anyway... */
962 if (dev_priv->chipset >= 0x40) {
963 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
964 break;
965 }
966 /* FALLTHRU */
6ee73861
BS		 967 default:
968 NV_ERROR(dev, "unknown parameter %lld\n", getparam->param);
969 return -EINVAL;
970 }
971
972 return 0;
973}
974
975int
976nouveau_ioctl_setparam(struct drm_device *dev, void *data,
977 struct drm_file *file_priv)
978{
979 struct drm_nouveau_setparam *setparam = data;
980
6ee73861
BS		 981 switch (setparam->param) {
982 default:
983 NV_ERROR(dev, "unknown parameter %lld\n", setparam->param);
984 return -EINVAL;
985 }
986
987 return 0;
988}
989
990/* Wait until (value(reg) & mask) == val, up until timeout has hit */
991bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout,
992 uint32_t reg, uint32_t mask, uint32_t val)
993{
994 struct drm_nouveau_private *dev_priv = dev->dev_private;
995 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
996 uint64_t start = ptimer->read(dev);
997
998 do {
999 if ((nv_rd32(dev, reg) & mask) == val)
1000 return true;
1001 } while (ptimer->read(dev) - start < timeout);
1002
1003 return false;
1004}
1005
1006/* Waits for PGRAPH to go completely idle */
1007bool nouveau_wait_for_idle(struct drm_device *dev)
1008{
1009 if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) {
1010 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1011 nv_rd32(dev, NV04_PGRAPH_STATUS));
1012 return false;
1013 }
1014
1015 return true;
1016}
1017
Linux kernel - Deliverables
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