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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin | |
3 | * Copyright 2008 Stuart Bennett | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include <linux/swab.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
6ee73861 BS |
28 | #include "drmP.h" |
29 | #include "drm.h" | |
30 | #include "drm_sarea.h" | |
31 | #include "drm_crtc_helper.h" | |
32 | #include <linux/vgaarb.h> | |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
6ee73861 BS |
34 | |
35 | #include "nouveau_drv.h" | |
36 | #include "nouveau_drm.h" | |
38651674 | 37 | #include "nouveau_fbcon.h" |
a8eaebc6 | 38 | #include "nouveau_ramht.h" |
6ee73861 BS |
39 | #include "nv50_display.h" |
40 | ||
6ee73861 | 41 | static void nouveau_stub_takedown(struct drm_device *dev) {} |
ee2e0131 | 42 | static int nouveau_stub_init(struct drm_device *dev) { return 0; } |
6ee73861 BS |
43 | |
44 | static int nouveau_init_engine_ptrs(struct drm_device *dev) | |
45 | { | |
46 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
47 | struct nouveau_engine *engine = &dev_priv->engine; | |
48 | ||
49 | switch (dev_priv->chipset & 0xf0) { | |
50 | case 0x00: | |
51 | engine->instmem.init = nv04_instmem_init; | |
52 | engine->instmem.takedown = nv04_instmem_takedown; | |
53 | engine->instmem.suspend = nv04_instmem_suspend; | |
54 | engine->instmem.resume = nv04_instmem_resume; | |
55 | engine->instmem.populate = nv04_instmem_populate; | |
56 | engine->instmem.clear = nv04_instmem_clear; | |
57 | engine->instmem.bind = nv04_instmem_bind; | |
58 | engine->instmem.unbind = nv04_instmem_unbind; | |
f56cb86f | 59 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
60 | engine->mc.init = nv04_mc_init; |
61 | engine->mc.takedown = nv04_mc_takedown; | |
62 | engine->timer.init = nv04_timer_init; | |
63 | engine->timer.read = nv04_timer_read; | |
64 | engine->timer.takedown = nv04_timer_takedown; | |
65 | engine->fb.init = nv04_fb_init; | |
66 | engine->fb.takedown = nv04_fb_takedown; | |
67 | engine->graph.grclass = nv04_graph_grclass; | |
68 | engine->graph.init = nv04_graph_init; | |
69 | engine->graph.takedown = nv04_graph_takedown; | |
70 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
71 | engine->graph.channel = nv04_graph_channel; | |
72 | engine->graph.create_context = nv04_graph_create_context; | |
73 | engine->graph.destroy_context = nv04_graph_destroy_context; | |
74 | engine->graph.load_context = nv04_graph_load_context; | |
75 | engine->graph.unload_context = nv04_graph_unload_context; | |
76 | engine->fifo.channels = 16; | |
77 | engine->fifo.init = nv04_fifo_init; | |
78 | engine->fifo.takedown = nouveau_stub_takedown; | |
79 | engine->fifo.disable = nv04_fifo_disable; | |
80 | engine->fifo.enable = nv04_fifo_enable; | |
81 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 FJ |
82 | engine->fifo.cache_flush = nv04_fifo_cache_flush; |
83 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | |
6ee73861 BS |
84 | engine->fifo.channel_id = nv04_fifo_channel_id; |
85 | engine->fifo.create_context = nv04_fifo_create_context; | |
86 | engine->fifo.destroy_context = nv04_fifo_destroy_context; | |
87 | engine->fifo.load_context = nv04_fifo_load_context; | |
88 | engine->fifo.unload_context = nv04_fifo_unload_context; | |
c88c2e06 FJ |
89 | engine->display.early_init = nv04_display_early_init; |
90 | engine->display.late_takedown = nv04_display_late_takedown; | |
91 | engine->display.create = nv04_display_create; | |
92 | engine->display.init = nv04_display_init; | |
93 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
94 | engine->gpio.init = nouveau_stub_init; |
95 | engine->gpio.takedown = nouveau_stub_takedown; | |
96 | engine->gpio.get = NULL; | |
97 | engine->gpio.set = NULL; | |
98 | engine->gpio.irq_enable = NULL; | |
6ee73861 BS |
99 | break; |
100 | case 0x10: | |
101 | engine->instmem.init = nv04_instmem_init; | |
102 | engine->instmem.takedown = nv04_instmem_takedown; | |
103 | engine->instmem.suspend = nv04_instmem_suspend; | |
104 | engine->instmem.resume = nv04_instmem_resume; | |
105 | engine->instmem.populate = nv04_instmem_populate; | |
106 | engine->instmem.clear = nv04_instmem_clear; | |
107 | engine->instmem.bind = nv04_instmem_bind; | |
108 | engine->instmem.unbind = nv04_instmem_unbind; | |
f56cb86f | 109 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
110 | engine->mc.init = nv04_mc_init; |
111 | engine->mc.takedown = nv04_mc_takedown; | |
112 | engine->timer.init = nv04_timer_init; | |
113 | engine->timer.read = nv04_timer_read; | |
114 | engine->timer.takedown = nv04_timer_takedown; | |
115 | engine->fb.init = nv10_fb_init; | |
116 | engine->fb.takedown = nv10_fb_takedown; | |
cb00f7c1 | 117 | engine->fb.set_region_tiling = nv10_fb_set_region_tiling; |
6ee73861 BS |
118 | engine->graph.grclass = nv10_graph_grclass; |
119 | engine->graph.init = nv10_graph_init; | |
120 | engine->graph.takedown = nv10_graph_takedown; | |
121 | engine->graph.channel = nv10_graph_channel; | |
122 | engine->graph.create_context = nv10_graph_create_context; | |
123 | engine->graph.destroy_context = nv10_graph_destroy_context; | |
124 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
125 | engine->graph.load_context = nv10_graph_load_context; | |
126 | engine->graph.unload_context = nv10_graph_unload_context; | |
cb00f7c1 | 127 | engine->graph.set_region_tiling = nv10_graph_set_region_tiling; |
6ee73861 BS |
128 | engine->fifo.channels = 32; |
129 | engine->fifo.init = nv10_fifo_init; | |
130 | engine->fifo.takedown = nouveau_stub_takedown; | |
131 | engine->fifo.disable = nv04_fifo_disable; | |
132 | engine->fifo.enable = nv04_fifo_enable; | |
133 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 FJ |
134 | engine->fifo.cache_flush = nv04_fifo_cache_flush; |
135 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | |
6ee73861 BS |
136 | engine->fifo.channel_id = nv10_fifo_channel_id; |
137 | engine->fifo.create_context = nv10_fifo_create_context; | |
138 | engine->fifo.destroy_context = nv10_fifo_destroy_context; | |
139 | engine->fifo.load_context = nv10_fifo_load_context; | |
140 | engine->fifo.unload_context = nv10_fifo_unload_context; | |
c88c2e06 FJ |
141 | engine->display.early_init = nv04_display_early_init; |
142 | engine->display.late_takedown = nv04_display_late_takedown; | |
143 | engine->display.create = nv04_display_create; | |
144 | engine->display.init = nv04_display_init; | |
145 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
146 | engine->gpio.init = nouveau_stub_init; |
147 | engine->gpio.takedown = nouveau_stub_takedown; | |
148 | engine->gpio.get = nv10_gpio_get; | |
149 | engine->gpio.set = nv10_gpio_set; | |
150 | engine->gpio.irq_enable = NULL; | |
6ee73861 BS |
151 | break; |
152 | case 0x20: | |
153 | engine->instmem.init = nv04_instmem_init; | |
154 | engine->instmem.takedown = nv04_instmem_takedown; | |
155 | engine->instmem.suspend = nv04_instmem_suspend; | |
156 | engine->instmem.resume = nv04_instmem_resume; | |
157 | engine->instmem.populate = nv04_instmem_populate; | |
158 | engine->instmem.clear = nv04_instmem_clear; | |
159 | engine->instmem.bind = nv04_instmem_bind; | |
160 | engine->instmem.unbind = nv04_instmem_unbind; | |
f56cb86f | 161 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
162 | engine->mc.init = nv04_mc_init; |
163 | engine->mc.takedown = nv04_mc_takedown; | |
164 | engine->timer.init = nv04_timer_init; | |
165 | engine->timer.read = nv04_timer_read; | |
166 | engine->timer.takedown = nv04_timer_takedown; | |
167 | engine->fb.init = nv10_fb_init; | |
168 | engine->fb.takedown = nv10_fb_takedown; | |
cb00f7c1 | 169 | engine->fb.set_region_tiling = nv10_fb_set_region_tiling; |
6ee73861 BS |
170 | engine->graph.grclass = nv20_graph_grclass; |
171 | engine->graph.init = nv20_graph_init; | |
172 | engine->graph.takedown = nv20_graph_takedown; | |
173 | engine->graph.channel = nv10_graph_channel; | |
174 | engine->graph.create_context = nv20_graph_create_context; | |
175 | engine->graph.destroy_context = nv20_graph_destroy_context; | |
176 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
177 | engine->graph.load_context = nv20_graph_load_context; | |
178 | engine->graph.unload_context = nv20_graph_unload_context; | |
cb00f7c1 | 179 | engine->graph.set_region_tiling = nv20_graph_set_region_tiling; |
6ee73861 BS |
180 | engine->fifo.channels = 32; |
181 | engine->fifo.init = nv10_fifo_init; | |
182 | engine->fifo.takedown = nouveau_stub_takedown; | |
183 | engine->fifo.disable = nv04_fifo_disable; | |
184 | engine->fifo.enable = nv04_fifo_enable; | |
185 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 FJ |
186 | engine->fifo.cache_flush = nv04_fifo_cache_flush; |
187 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | |
6ee73861 BS |
188 | engine->fifo.channel_id = nv10_fifo_channel_id; |
189 | engine->fifo.create_context = nv10_fifo_create_context; | |
190 | engine->fifo.destroy_context = nv10_fifo_destroy_context; | |
191 | engine->fifo.load_context = nv10_fifo_load_context; | |
192 | engine->fifo.unload_context = nv10_fifo_unload_context; | |
c88c2e06 FJ |
193 | engine->display.early_init = nv04_display_early_init; |
194 | engine->display.late_takedown = nv04_display_late_takedown; | |
195 | engine->display.create = nv04_display_create; | |
196 | engine->display.init = nv04_display_init; | |
197 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
198 | engine->gpio.init = nouveau_stub_init; |
199 | engine->gpio.takedown = nouveau_stub_takedown; | |
200 | engine->gpio.get = nv10_gpio_get; | |
201 | engine->gpio.set = nv10_gpio_set; | |
202 | engine->gpio.irq_enable = NULL; | |
6ee73861 BS |
203 | break; |
204 | case 0x30: | |
205 | engine->instmem.init = nv04_instmem_init; | |
206 | engine->instmem.takedown = nv04_instmem_takedown; | |
207 | engine->instmem.suspend = nv04_instmem_suspend; | |
208 | engine->instmem.resume = nv04_instmem_resume; | |
209 | engine->instmem.populate = nv04_instmem_populate; | |
210 | engine->instmem.clear = nv04_instmem_clear; | |
211 | engine->instmem.bind = nv04_instmem_bind; | |
212 | engine->instmem.unbind = nv04_instmem_unbind; | |
f56cb86f | 213 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
214 | engine->mc.init = nv04_mc_init; |
215 | engine->mc.takedown = nv04_mc_takedown; | |
216 | engine->timer.init = nv04_timer_init; | |
217 | engine->timer.read = nv04_timer_read; | |
218 | engine->timer.takedown = nv04_timer_takedown; | |
8bded189 FJ |
219 | engine->fb.init = nv30_fb_init; |
220 | engine->fb.takedown = nv30_fb_takedown; | |
cb00f7c1 | 221 | engine->fb.set_region_tiling = nv10_fb_set_region_tiling; |
6ee73861 BS |
222 | engine->graph.grclass = nv30_graph_grclass; |
223 | engine->graph.init = nv30_graph_init; | |
224 | engine->graph.takedown = nv20_graph_takedown; | |
225 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
226 | engine->graph.channel = nv10_graph_channel; | |
227 | engine->graph.create_context = nv20_graph_create_context; | |
228 | engine->graph.destroy_context = nv20_graph_destroy_context; | |
229 | engine->graph.load_context = nv20_graph_load_context; | |
230 | engine->graph.unload_context = nv20_graph_unload_context; | |
cb00f7c1 | 231 | engine->graph.set_region_tiling = nv20_graph_set_region_tiling; |
6ee73861 BS |
232 | engine->fifo.channels = 32; |
233 | engine->fifo.init = nv10_fifo_init; | |
234 | engine->fifo.takedown = nouveau_stub_takedown; | |
235 | engine->fifo.disable = nv04_fifo_disable; | |
236 | engine->fifo.enable = nv04_fifo_enable; | |
237 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 FJ |
238 | engine->fifo.cache_flush = nv04_fifo_cache_flush; |
239 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | |
6ee73861 BS |
240 | engine->fifo.channel_id = nv10_fifo_channel_id; |
241 | engine->fifo.create_context = nv10_fifo_create_context; | |
242 | engine->fifo.destroy_context = nv10_fifo_destroy_context; | |
243 | engine->fifo.load_context = nv10_fifo_load_context; | |
244 | engine->fifo.unload_context = nv10_fifo_unload_context; | |
c88c2e06 FJ |
245 | engine->display.early_init = nv04_display_early_init; |
246 | engine->display.late_takedown = nv04_display_late_takedown; | |
247 | engine->display.create = nv04_display_create; | |
248 | engine->display.init = nv04_display_init; | |
249 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
250 | engine->gpio.init = nouveau_stub_init; |
251 | engine->gpio.takedown = nouveau_stub_takedown; | |
252 | engine->gpio.get = nv10_gpio_get; | |
253 | engine->gpio.set = nv10_gpio_set; | |
254 | engine->gpio.irq_enable = NULL; | |
6ee73861 BS |
255 | break; |
256 | case 0x40: | |
257 | case 0x60: | |
258 | engine->instmem.init = nv04_instmem_init; | |
259 | engine->instmem.takedown = nv04_instmem_takedown; | |
260 | engine->instmem.suspend = nv04_instmem_suspend; | |
261 | engine->instmem.resume = nv04_instmem_resume; | |
262 | engine->instmem.populate = nv04_instmem_populate; | |
263 | engine->instmem.clear = nv04_instmem_clear; | |
264 | engine->instmem.bind = nv04_instmem_bind; | |
265 | engine->instmem.unbind = nv04_instmem_unbind; | |
f56cb86f | 266 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
267 | engine->mc.init = nv40_mc_init; |
268 | engine->mc.takedown = nv40_mc_takedown; | |
269 | engine->timer.init = nv04_timer_init; | |
270 | engine->timer.read = nv04_timer_read; | |
271 | engine->timer.takedown = nv04_timer_takedown; | |
272 | engine->fb.init = nv40_fb_init; | |
273 | engine->fb.takedown = nv40_fb_takedown; | |
cb00f7c1 | 274 | engine->fb.set_region_tiling = nv40_fb_set_region_tiling; |
6ee73861 BS |
275 | engine->graph.grclass = nv40_graph_grclass; |
276 | engine->graph.init = nv40_graph_init; | |
277 | engine->graph.takedown = nv40_graph_takedown; | |
278 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
279 | engine->graph.channel = nv40_graph_channel; | |
280 | engine->graph.create_context = nv40_graph_create_context; | |
281 | engine->graph.destroy_context = nv40_graph_destroy_context; | |
282 | engine->graph.load_context = nv40_graph_load_context; | |
283 | engine->graph.unload_context = nv40_graph_unload_context; | |
cb00f7c1 | 284 | engine->graph.set_region_tiling = nv40_graph_set_region_tiling; |
6ee73861 BS |
285 | engine->fifo.channels = 32; |
286 | engine->fifo.init = nv40_fifo_init; | |
287 | engine->fifo.takedown = nouveau_stub_takedown; | |
288 | engine->fifo.disable = nv04_fifo_disable; | |
289 | engine->fifo.enable = nv04_fifo_enable; | |
290 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 FJ |
291 | engine->fifo.cache_flush = nv04_fifo_cache_flush; |
292 | engine->fifo.cache_pull = nv04_fifo_cache_pull; | |
6ee73861 BS |
293 | engine->fifo.channel_id = nv10_fifo_channel_id; |
294 | engine->fifo.create_context = nv40_fifo_create_context; | |
295 | engine->fifo.destroy_context = nv40_fifo_destroy_context; | |
296 | engine->fifo.load_context = nv40_fifo_load_context; | |
297 | engine->fifo.unload_context = nv40_fifo_unload_context; | |
c88c2e06 FJ |
298 | engine->display.early_init = nv04_display_early_init; |
299 | engine->display.late_takedown = nv04_display_late_takedown; | |
300 | engine->display.create = nv04_display_create; | |
301 | engine->display.init = nv04_display_init; | |
302 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
303 | engine->gpio.init = nouveau_stub_init; |
304 | engine->gpio.takedown = nouveau_stub_takedown; | |
305 | engine->gpio.get = nv10_gpio_get; | |
306 | engine->gpio.set = nv10_gpio_set; | |
307 | engine->gpio.irq_enable = NULL; | |
6ee73861 BS |
308 | break; |
309 | case 0x50: | |
310 | case 0x80: /* gotta love NVIDIA's consistency.. */ | |
311 | case 0x90: | |
312 | case 0xA0: | |
313 | engine->instmem.init = nv50_instmem_init; | |
314 | engine->instmem.takedown = nv50_instmem_takedown; | |
315 | engine->instmem.suspend = nv50_instmem_suspend; | |
316 | engine->instmem.resume = nv50_instmem_resume; | |
317 | engine->instmem.populate = nv50_instmem_populate; | |
318 | engine->instmem.clear = nv50_instmem_clear; | |
319 | engine->instmem.bind = nv50_instmem_bind; | |
320 | engine->instmem.unbind = nv50_instmem_unbind; | |
734ee835 BS |
321 | if (dev_priv->chipset == 0x50) |
322 | engine->instmem.flush = nv50_instmem_flush; | |
323 | else | |
324 | engine->instmem.flush = nv84_instmem_flush; | |
6ee73861 BS |
325 | engine->mc.init = nv50_mc_init; |
326 | engine->mc.takedown = nv50_mc_takedown; | |
327 | engine->timer.init = nv04_timer_init; | |
328 | engine->timer.read = nv04_timer_read; | |
329 | engine->timer.takedown = nv04_timer_takedown; | |
304424e1 MK |
330 | engine->fb.init = nv50_fb_init; |
331 | engine->fb.takedown = nv50_fb_takedown; | |
6ee73861 BS |
332 | engine->graph.grclass = nv50_graph_grclass; |
333 | engine->graph.init = nv50_graph_init; | |
334 | engine->graph.takedown = nv50_graph_takedown; | |
335 | engine->graph.fifo_access = nv50_graph_fifo_access; | |
336 | engine->graph.channel = nv50_graph_channel; | |
337 | engine->graph.create_context = nv50_graph_create_context; | |
338 | engine->graph.destroy_context = nv50_graph_destroy_context; | |
339 | engine->graph.load_context = nv50_graph_load_context; | |
340 | engine->graph.unload_context = nv50_graph_unload_context; | |
341 | engine->fifo.channels = 128; | |
342 | engine->fifo.init = nv50_fifo_init; | |
343 | engine->fifo.takedown = nv50_fifo_takedown; | |
344 | engine->fifo.disable = nv04_fifo_disable; | |
345 | engine->fifo.enable = nv04_fifo_enable; | |
346 | engine->fifo.reassign = nv04_fifo_reassign; | |
347 | engine->fifo.channel_id = nv50_fifo_channel_id; | |
348 | engine->fifo.create_context = nv50_fifo_create_context; | |
349 | engine->fifo.destroy_context = nv50_fifo_destroy_context; | |
350 | engine->fifo.load_context = nv50_fifo_load_context; | |
351 | engine->fifo.unload_context = nv50_fifo_unload_context; | |
c88c2e06 FJ |
352 | engine->display.early_init = nv50_display_early_init; |
353 | engine->display.late_takedown = nv50_display_late_takedown; | |
354 | engine->display.create = nv50_display_create; | |
355 | engine->display.init = nv50_display_init; | |
356 | engine->display.destroy = nv50_display_destroy; | |
ee2e0131 BS |
357 | engine->gpio.init = nv50_gpio_init; |
358 | engine->gpio.takedown = nouveau_stub_takedown; | |
359 | engine->gpio.get = nv50_gpio_get; | |
360 | engine->gpio.set = nv50_gpio_set; | |
361 | engine->gpio.irq_enable = nv50_gpio_irq_enable; | |
6ee73861 | 362 | break; |
4b223eef BS |
363 | case 0xC0: |
364 | engine->instmem.init = nvc0_instmem_init; | |
365 | engine->instmem.takedown = nvc0_instmem_takedown; | |
366 | engine->instmem.suspend = nvc0_instmem_suspend; | |
367 | engine->instmem.resume = nvc0_instmem_resume; | |
368 | engine->instmem.populate = nvc0_instmem_populate; | |
369 | engine->instmem.clear = nvc0_instmem_clear; | |
370 | engine->instmem.bind = nvc0_instmem_bind; | |
371 | engine->instmem.unbind = nvc0_instmem_unbind; | |
372 | engine->instmem.flush = nvc0_instmem_flush; | |
373 | engine->mc.init = nv50_mc_init; | |
374 | engine->mc.takedown = nv50_mc_takedown; | |
375 | engine->timer.init = nv04_timer_init; | |
376 | engine->timer.read = nv04_timer_read; | |
377 | engine->timer.takedown = nv04_timer_takedown; | |
378 | engine->fb.init = nvc0_fb_init; | |
379 | engine->fb.takedown = nvc0_fb_takedown; | |
380 | engine->graph.grclass = NULL; //nvc0_graph_grclass; | |
381 | engine->graph.init = nvc0_graph_init; | |
382 | engine->graph.takedown = nvc0_graph_takedown; | |
383 | engine->graph.fifo_access = nvc0_graph_fifo_access; | |
384 | engine->graph.channel = nvc0_graph_channel; | |
385 | engine->graph.create_context = nvc0_graph_create_context; | |
386 | engine->graph.destroy_context = nvc0_graph_destroy_context; | |
387 | engine->graph.load_context = nvc0_graph_load_context; | |
388 | engine->graph.unload_context = nvc0_graph_unload_context; | |
389 | engine->fifo.channels = 128; | |
390 | engine->fifo.init = nvc0_fifo_init; | |
391 | engine->fifo.takedown = nvc0_fifo_takedown; | |
392 | engine->fifo.disable = nvc0_fifo_disable; | |
393 | engine->fifo.enable = nvc0_fifo_enable; | |
394 | engine->fifo.reassign = nvc0_fifo_reassign; | |
395 | engine->fifo.channel_id = nvc0_fifo_channel_id; | |
396 | engine->fifo.create_context = nvc0_fifo_create_context; | |
397 | engine->fifo.destroy_context = nvc0_fifo_destroy_context; | |
398 | engine->fifo.load_context = nvc0_fifo_load_context; | |
399 | engine->fifo.unload_context = nvc0_fifo_unload_context; | |
400 | engine->display.early_init = nv50_display_early_init; | |
401 | engine->display.late_takedown = nv50_display_late_takedown; | |
402 | engine->display.create = nv50_display_create; | |
403 | engine->display.init = nv50_display_init; | |
404 | engine->display.destroy = nv50_display_destroy; | |
405 | engine->gpio.init = nv50_gpio_init; | |
406 | engine->gpio.takedown = nouveau_stub_takedown; | |
407 | engine->gpio.get = nv50_gpio_get; | |
408 | engine->gpio.set = nv50_gpio_set; | |
409 | engine->gpio.irq_enable = nv50_gpio_irq_enable; | |
410 | break; | |
6ee73861 BS |
411 | default: |
412 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); | |
413 | return 1; | |
414 | } | |
415 | ||
416 | return 0; | |
417 | } | |
418 | ||
419 | static unsigned int | |
420 | nouveau_vga_set_decode(void *priv, bool state) | |
421 | { | |
9967b948 MK |
422 | struct drm_device *dev = priv; |
423 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
424 | ||
425 | if (dev_priv->chipset >= 0x40) | |
426 | nv_wr32(dev, 0x88054, state); | |
427 | else | |
428 | nv_wr32(dev, 0x1854, state); | |
429 | ||
6ee73861 BS |
430 | if (state) |
431 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
432 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
433 | else | |
434 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
435 | } | |
436 | ||
0735f62e BS |
437 | static int |
438 | nouveau_card_init_channel(struct drm_device *dev) | |
439 | { | |
440 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a8eaebc6 | 441 | struct nouveau_gpuobj *gpuobj = NULL; |
0735f62e BS |
442 | int ret; |
443 | ||
444 | ret = nouveau_channel_alloc(dev, &dev_priv->channel, | |
a8eaebc6 | 445 | (struct drm_file *)-2, NvDmaFB, NvDmaTT); |
0735f62e BS |
446 | if (ret) |
447 | return ret; | |
448 | ||
0735f62e | 449 | ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY, |
a76fb4e8 | 450 | 0, dev_priv->vram_size, |
0735f62e BS |
451 | NV_DMA_ACCESS_RW, NV_DMA_TARGET_VIDMEM, |
452 | &gpuobj); | |
453 | if (ret) | |
454 | goto out_err; | |
455 | ||
a8eaebc6 BS |
456 | ret = nouveau_ramht_insert(dev_priv->channel, NvDmaVRAM, gpuobj); |
457 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
0735f62e BS |
458 | if (ret) |
459 | goto out_err; | |
460 | ||
0735f62e BS |
461 | ret = nouveau_gpuobj_gart_dma_new(dev_priv->channel, 0, |
462 | dev_priv->gart_info.aper_size, | |
463 | NV_DMA_ACCESS_RW, &gpuobj, NULL); | |
464 | if (ret) | |
465 | goto out_err; | |
466 | ||
a8eaebc6 BS |
467 | ret = nouveau_ramht_insert(dev_priv->channel, NvDmaGART, gpuobj); |
468 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
0735f62e BS |
469 | if (ret) |
470 | goto out_err; | |
471 | ||
472 | return 0; | |
a8eaebc6 | 473 | |
0735f62e | 474 | out_err: |
0735f62e BS |
475 | nouveau_channel_free(dev_priv->channel); |
476 | dev_priv->channel = NULL; | |
477 | return ret; | |
478 | } | |
479 | ||
6a9ee8af DA |
480 | static void nouveau_switcheroo_set_state(struct pci_dev *pdev, |
481 | enum vga_switcheroo_state state) | |
482 | { | |
fbf81762 | 483 | struct drm_device *dev = pci_get_drvdata(pdev); |
6a9ee8af DA |
484 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
485 | if (state == VGA_SWITCHEROO_ON) { | |
486 | printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); | |
487 | nouveau_pci_resume(pdev); | |
fbf81762 | 488 | drm_kms_helper_poll_enable(dev); |
6a9ee8af DA |
489 | } else { |
490 | printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); | |
fbf81762 | 491 | drm_kms_helper_poll_disable(dev); |
6a9ee8af DA |
492 | nouveau_pci_suspend(pdev, pmm); |
493 | } | |
494 | } | |
495 | ||
496 | static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) | |
497 | { | |
498 | struct drm_device *dev = pci_get_drvdata(pdev); | |
499 | bool can_switch; | |
500 | ||
501 | spin_lock(&dev->count_lock); | |
502 | can_switch = (dev->open_count == 0); | |
503 | spin_unlock(&dev->count_lock); | |
504 | return can_switch; | |
505 | } | |
506 | ||
6ee73861 BS |
507 | int |
508 | nouveau_card_init(struct drm_device *dev) | |
509 | { | |
510 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
511 | struct nouveau_engine *engine; | |
6ee73861 BS |
512 | int ret; |
513 | ||
6ee73861 | 514 | vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); |
6a9ee8af DA |
515 | vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state, |
516 | nouveau_switcheroo_can_switch); | |
6ee73861 BS |
517 | |
518 | /* Initialise internal driver API hooks */ | |
519 | ret = nouveau_init_engine_ptrs(dev); | |
520 | if (ret) | |
c5804be0 | 521 | goto out; |
6ee73861 | 522 | engine = &dev_priv->engine; |
ff9e5279 | 523 | spin_lock_init(&dev_priv->context_switch_lock); |
6ee73861 | 524 | |
c88c2e06 FJ |
525 | /* Make the CRTCs and I2C buses accessible */ |
526 | ret = engine->display.early_init(dev); | |
527 | if (ret) | |
528 | goto out; | |
529 | ||
6ee73861 | 530 | /* Parse BIOS tables / Run init tables if card not POSTed */ |
cd0b072f BS |
531 | ret = nouveau_bios_init(dev); |
532 | if (ret) | |
c88c2e06 | 533 | goto out_display_early; |
6ee73861 | 534 | |
fbd2895e | 535 | ret = nouveau_mem_vram_init(dev); |
a76fb4e8 BS |
536 | if (ret) |
537 | goto out_bios; | |
538 | ||
fbd2895e | 539 | ret = nouveau_gpuobj_init(dev); |
6ee73861 | 540 | if (ret) |
fbd2895e | 541 | goto out_vram; |
6ee73861 | 542 | |
6ee73861 BS |
543 | ret = engine->instmem.init(dev); |
544 | if (ret) | |
fbd2895e | 545 | goto out_gpuobj; |
6ee73861 | 546 | |
fbd2895e | 547 | ret = nouveau_mem_gart_init(dev); |
6ee73861 | 548 | if (ret) |
c5804be0 | 549 | goto out_instmem; |
6ee73861 | 550 | |
6ee73861 BS |
551 | /* PMC */ |
552 | ret = engine->mc.init(dev); | |
553 | if (ret) | |
fbd2895e | 554 | goto out_gart; |
6ee73861 | 555 | |
ee2e0131 BS |
556 | /* PGPIO */ |
557 | ret = engine->gpio.init(dev); | |
558 | if (ret) | |
559 | goto out_mc; | |
560 | ||
6ee73861 BS |
561 | /* PTIMER */ |
562 | ret = engine->timer.init(dev); | |
563 | if (ret) | |
ee2e0131 | 564 | goto out_gpio; |
6ee73861 BS |
565 | |
566 | /* PFB */ | |
567 | ret = engine->fb.init(dev); | |
568 | if (ret) | |
c5804be0 | 569 | goto out_timer; |
6ee73861 | 570 | |
a32ed69d MK |
571 | if (nouveau_noaccel) |
572 | engine->graph.accel_blocked = true; | |
573 | else { | |
574 | /* PGRAPH */ | |
575 | ret = engine->graph.init(dev); | |
576 | if (ret) | |
577 | goto out_fb; | |
6ee73861 | 578 | |
a32ed69d MK |
579 | /* PFIFO */ |
580 | ret = engine->fifo.init(dev); | |
581 | if (ret) | |
582 | goto out_graph; | |
583 | } | |
6ee73861 | 584 | |
c88c2e06 | 585 | ret = engine->display.create(dev); |
e88efe05 BS |
586 | if (ret) |
587 | goto out_fifo; | |
588 | ||
6ee73861 BS |
589 | /* this call irq_preinstall, register irq handler and |
590 | * call irq_postinstall | |
591 | */ | |
592 | ret = drm_irq_install(dev); | |
593 | if (ret) | |
e88efe05 | 594 | goto out_display; |
6ee73861 BS |
595 | |
596 | ret = drm_vblank_init(dev, 0); | |
597 | if (ret) | |
c5804be0 | 598 | goto out_irq; |
6ee73861 BS |
599 | |
600 | /* what about PVIDEO/PCRTC/PRAMDAC etc? */ | |
601 | ||
0735f62e BS |
602 | if (!engine->graph.accel_blocked) { |
603 | ret = nouveau_card_init_channel(dev); | |
604 | if (ret) | |
605 | goto out_irq; | |
6ee73861 BS |
606 | } |
607 | ||
6ee73861 BS |
608 | ret = nouveau_backlight_init(dev); |
609 | if (ret) | |
610 | NV_ERROR(dev, "Error %d registering backlight\n", ret); | |
611 | ||
cd0b072f BS |
612 | nouveau_fbcon_init(dev); |
613 | drm_kms_helper_poll_init(dev); | |
6ee73861 | 614 | return 0; |
c5804be0 MK |
615 | |
616 | out_irq: | |
617 | drm_irq_uninstall(dev); | |
e88efe05 | 618 | out_display: |
c88c2e06 | 619 | engine->display.destroy(dev); |
c5804be0 | 620 | out_fifo: |
a32ed69d MK |
621 | if (!nouveau_noaccel) |
622 | engine->fifo.takedown(dev); | |
c5804be0 | 623 | out_graph: |
a32ed69d MK |
624 | if (!nouveau_noaccel) |
625 | engine->graph.takedown(dev); | |
c5804be0 MK |
626 | out_fb: |
627 | engine->fb.takedown(dev); | |
628 | out_timer: | |
629 | engine->timer.takedown(dev); | |
ee2e0131 BS |
630 | out_gpio: |
631 | engine->gpio.takedown(dev); | |
c5804be0 MK |
632 | out_mc: |
633 | engine->mc.takedown(dev); | |
fbd2895e BS |
634 | out_gart: |
635 | nouveau_mem_gart_fini(dev); | |
c5804be0 MK |
636 | out_instmem: |
637 | engine->instmem.takedown(dev); | |
fbd2895e BS |
638 | out_gpuobj: |
639 | nouveau_gpuobj_takedown(dev); | |
640 | out_vram: | |
641 | nouveau_mem_vram_fini(dev); | |
c5804be0 MK |
642 | out_bios: |
643 | nouveau_bios_takedown(dev); | |
c88c2e06 FJ |
644 | out_display_early: |
645 | engine->display.late_takedown(dev); | |
c5804be0 MK |
646 | out: |
647 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
648 | return ret; | |
6ee73861 BS |
649 | } |
650 | ||
651 | static void nouveau_card_takedown(struct drm_device *dev) | |
652 | { | |
653 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
654 | struct nouveau_engine *engine = &dev_priv->engine; | |
655 | ||
b6d3d871 | 656 | nouveau_backlight_exit(dev); |
38651674 | 657 | |
b6d3d871 BS |
658 | if (dev_priv->channel) { |
659 | nouveau_channel_free(dev_priv->channel); | |
660 | dev_priv->channel = NULL; | |
661 | } | |
6ee73861 | 662 | |
b6d3d871 BS |
663 | if (!nouveau_noaccel) { |
664 | engine->fifo.takedown(dev); | |
665 | engine->graph.takedown(dev); | |
666 | } | |
667 | engine->fb.takedown(dev); | |
668 | engine->timer.takedown(dev); | |
ee2e0131 | 669 | engine->gpio.takedown(dev); |
b6d3d871 | 670 | engine->mc.takedown(dev); |
c88c2e06 | 671 | engine->display.late_takedown(dev); |
6ee73861 | 672 | |
b6d3d871 BS |
673 | mutex_lock(&dev->struct_mutex); |
674 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM); | |
675 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT); | |
676 | mutex_unlock(&dev->struct_mutex); | |
fbd2895e | 677 | nouveau_mem_gart_fini(dev); |
6ee73861 | 678 | |
b6d3d871 | 679 | engine->instmem.takedown(dev); |
fbd2895e BS |
680 | nouveau_gpuobj_takedown(dev); |
681 | nouveau_mem_vram_fini(dev); | |
6ee73861 | 682 | |
b6d3d871 | 683 | drm_irq_uninstall(dev); |
6ee73861 | 684 | |
b6d3d871 | 685 | nouveau_bios_takedown(dev); |
6ee73861 | 686 | |
b6d3d871 | 687 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
6ee73861 BS |
688 | } |
689 | ||
690 | /* here a client dies, release the stuff that was allocated for its | |
691 | * file_priv */ | |
692 | void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) | |
693 | { | |
694 | nouveau_channel_cleanup(dev, file_priv); | |
695 | } | |
696 | ||
697 | /* first module load, setup the mmio/fb mapping */ | |
698 | /* KMS: we need mmio at load time, not when the first drm client opens. */ | |
699 | int nouveau_firstopen(struct drm_device *dev) | |
700 | { | |
701 | return 0; | |
702 | } | |
703 | ||
704 | /* if we have an OF card, copy vbios to RAMIN */ | |
705 | static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev) | |
706 | { | |
707 | #if defined(__powerpc__) | |
708 | int size, i; | |
709 | const uint32_t *bios; | |
710 | struct device_node *dn = pci_device_to_OF_node(dev->pdev); | |
711 | if (!dn) { | |
712 | NV_INFO(dev, "Unable to get the OF node\n"); | |
713 | return; | |
714 | } | |
715 | ||
716 | bios = of_get_property(dn, "NVDA,BMP", &size); | |
717 | if (bios) { | |
718 | for (i = 0; i < size; i += 4) | |
719 | nv_wi32(dev, i, bios[i/4]); | |
720 | NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size); | |
721 | } else { | |
722 | NV_INFO(dev, "Unable to get the OF bios\n"); | |
723 | } | |
724 | #endif | |
725 | } | |
726 | ||
06415c56 MS |
727 | static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev) |
728 | { | |
729 | struct pci_dev *pdev = dev->pdev; | |
730 | struct apertures_struct *aper = alloc_apertures(3); | |
731 | if (!aper) | |
732 | return NULL; | |
733 | ||
734 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
735 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
736 | aper->count = 1; | |
737 | ||
738 | if (pci_resource_len(pdev, 2)) { | |
739 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
740 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
741 | aper->count++; | |
742 | } | |
743 | ||
744 | if (pci_resource_len(pdev, 3)) { | |
745 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
746 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
747 | aper->count++; | |
748 | } | |
749 | ||
750 | return aper; | |
751 | } | |
752 | ||
753 | static int nouveau_remove_conflicting_drivers(struct drm_device *dev) | |
754 | { | |
755 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
3b9676e7 | 756 | bool primary = false; |
06415c56 MS |
757 | dev_priv->apertures = nouveau_get_apertures(dev); |
758 | if (!dev_priv->apertures) | |
759 | return -ENOMEM; | |
760 | ||
3b9676e7 MS |
761 | #ifdef CONFIG_X86 |
762 | primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
763 | #endif | |
764 | ||
765 | remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary); | |
06415c56 MS |
766 | return 0; |
767 | } | |
768 | ||
6ee73861 BS |
769 | int nouveau_load(struct drm_device *dev, unsigned long flags) |
770 | { | |
771 | struct drm_nouveau_private *dev_priv; | |
772 | uint32_t reg0; | |
773 | resource_size_t mmio_start_offs; | |
cd0b072f | 774 | int ret; |
6ee73861 BS |
775 | |
776 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
a0d069ea DC |
777 | if (!dev_priv) { |
778 | ret = -ENOMEM; | |
779 | goto err_out; | |
780 | } | |
6ee73861 BS |
781 | dev->dev_private = dev_priv; |
782 | dev_priv->dev = dev; | |
783 | ||
784 | dev_priv->flags = flags & NOUVEAU_FLAGS; | |
6ee73861 BS |
785 | |
786 | NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", | |
787 | dev->pci_vendor, dev->pci_device, dev->pdev->class); | |
788 | ||
6ee73861 | 789 | dev_priv->wq = create_workqueue("nouveau"); |
a0d069ea DC |
790 | if (!dev_priv->wq) { |
791 | ret = -EINVAL; | |
792 | goto err_priv; | |
793 | } | |
6ee73861 BS |
794 | |
795 | /* resource 0 is mmio regs */ | |
796 | /* resource 1 is linear FB */ | |
797 | /* resource 2 is RAMIN (mmio regs + 0x1000000) */ | |
798 | /* resource 6 is bios */ | |
799 | ||
800 | /* map the mmio regs */ | |
801 | mmio_start_offs = pci_resource_start(dev->pdev, 0); | |
802 | dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000); | |
803 | if (!dev_priv->mmio) { | |
804 | NV_ERROR(dev, "Unable to initialize the mmio mapping. " | |
805 | "Please report your setup to " DRIVER_EMAIL "\n"); | |
a0d069ea DC |
806 | ret = -EINVAL; |
807 | goto err_wq; | |
6ee73861 BS |
808 | } |
809 | NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", | |
810 | (unsigned long long)mmio_start_offs); | |
811 | ||
812 | #ifdef __BIG_ENDIAN | |
813 | /* Put the card in BE mode if it's not */ | |
814 | if (nv_rd32(dev, NV03_PMC_BOOT_1)) | |
815 | nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001); | |
816 | ||
817 | DRM_MEMORYBARRIER(); | |
818 | #endif | |
819 | ||
820 | /* Time to determine the card architecture */ | |
821 | reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); | |
822 | ||
823 | /* We're dealing with >=NV10 */ | |
824 | if ((reg0 & 0x0f000000) > 0) { | |
825 | /* Bit 27-20 contain the architecture in hex */ | |
826 | dev_priv->chipset = (reg0 & 0xff00000) >> 20; | |
827 | /* NV04 or NV05 */ | |
828 | } else if ((reg0 & 0xff00fff0) == 0x20004000) { | |
1dee7a93 BS |
829 | if (reg0 & 0x00f00000) |
830 | dev_priv->chipset = 0x05; | |
831 | else | |
832 | dev_priv->chipset = 0x04; | |
6ee73861 BS |
833 | } else |
834 | dev_priv->chipset = 0xff; | |
835 | ||
836 | switch (dev_priv->chipset & 0xf0) { | |
837 | case 0x00: | |
838 | case 0x10: | |
839 | case 0x20: | |
840 | case 0x30: | |
841 | dev_priv->card_type = dev_priv->chipset & 0xf0; | |
842 | break; | |
843 | case 0x40: | |
844 | case 0x60: | |
845 | dev_priv->card_type = NV_40; | |
846 | break; | |
847 | case 0x50: | |
848 | case 0x80: | |
849 | case 0x90: | |
850 | case 0xa0: | |
851 | dev_priv->card_type = NV_50; | |
852 | break; | |
4b223eef BS |
853 | case 0xc0: |
854 | dev_priv->card_type = NV_C0; | |
855 | break; | |
6ee73861 BS |
856 | default: |
857 | NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0); | |
a0d069ea DC |
858 | ret = -EINVAL; |
859 | goto err_mmio; | |
6ee73861 BS |
860 | } |
861 | ||
862 | NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n", | |
863 | dev_priv->card_type, reg0); | |
864 | ||
cd0b072f BS |
865 | ret = nouveau_remove_conflicting_drivers(dev); |
866 | if (ret) | |
a0d069ea | 867 | goto err_mmio; |
06415c56 | 868 | |
6d696305 | 869 | /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */ |
6ee73861 BS |
870 | if (dev_priv->card_type >= NV_40) { |
871 | int ramin_bar = 2; | |
872 | if (pci_resource_len(dev->pdev, ramin_bar) == 0) | |
873 | ramin_bar = 3; | |
874 | ||
875 | dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar); | |
6d696305 BS |
876 | dev_priv->ramin = |
877 | ioremap(pci_resource_start(dev->pdev, ramin_bar), | |
6ee73861 BS |
878 | dev_priv->ramin_size); |
879 | if (!dev_priv->ramin) { | |
6d696305 | 880 | NV_ERROR(dev, "Failed to PRAMIN BAR"); |
a0d069ea DC |
881 | ret = -ENOMEM; |
882 | goto err_mmio; | |
6ee73861 | 883 | } |
6d696305 | 884 | } else { |
6ee73861 BS |
885 | dev_priv->ramin_size = 1 * 1024 * 1024; |
886 | dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN, | |
6d696305 | 887 | dev_priv->ramin_size); |
6ee73861 BS |
888 | if (!dev_priv->ramin) { |
889 | NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n"); | |
a0d069ea DC |
890 | ret = -ENOMEM; |
891 | goto err_mmio; | |
6ee73861 BS |
892 | } |
893 | } | |
894 | ||
895 | nouveau_OF_copy_vbios_to_ramin(dev); | |
896 | ||
897 | /* Special flags */ | |
898 | if (dev->pci_device == 0x01a0) | |
899 | dev_priv->flags |= NV_NFORCE; | |
900 | else if (dev->pci_device == 0x01f0) | |
901 | dev_priv->flags |= NV_NFORCE2; | |
902 | ||
903 | /* For kernel modesetting, init card now and bring up fbcon */ | |
cd0b072f BS |
904 | ret = nouveau_card_init(dev); |
905 | if (ret) | |
a0d069ea | 906 | goto err_ramin; |
6ee73861 BS |
907 | |
908 | return 0; | |
a0d069ea DC |
909 | |
910 | err_ramin: | |
911 | iounmap(dev_priv->ramin); | |
912 | err_mmio: | |
913 | iounmap(dev_priv->mmio); | |
914 | err_wq: | |
915 | destroy_workqueue(dev_priv->wq); | |
916 | err_priv: | |
917 | kfree(dev_priv); | |
918 | dev->dev_private = NULL; | |
919 | err_out: | |
920 | return ret; | |
6ee73861 BS |
921 | } |
922 | ||
6ee73861 BS |
923 | void nouveau_lastclose(struct drm_device *dev) |
924 | { | |
6ee73861 BS |
925 | } |
926 | ||
927 | int nouveau_unload(struct drm_device *dev) | |
928 | { | |
929 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
c88c2e06 | 930 | struct nouveau_engine *engine = &dev_priv->engine; |
6ee73861 | 931 | |
cd0b072f BS |
932 | drm_kms_helper_poll_fini(dev); |
933 | nouveau_fbcon_fini(dev); | |
c88c2e06 | 934 | engine->display.destroy(dev); |
cd0b072f | 935 | nouveau_card_takedown(dev); |
6ee73861 BS |
936 | |
937 | iounmap(dev_priv->mmio); | |
938 | iounmap(dev_priv->ramin); | |
939 | ||
940 | kfree(dev_priv); | |
941 | dev->dev_private = NULL; | |
942 | return 0; | |
943 | } | |
944 | ||
6ee73861 BS |
945 | int nouveau_ioctl_getparam(struct drm_device *dev, void *data, |
946 | struct drm_file *file_priv) | |
947 | { | |
948 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
949 | struct drm_nouveau_getparam *getparam = data; | |
950 | ||
6ee73861 BS |
951 | switch (getparam->param) { |
952 | case NOUVEAU_GETPARAM_CHIPSET_ID: | |
953 | getparam->value = dev_priv->chipset; | |
954 | break; | |
955 | case NOUVEAU_GETPARAM_PCI_VENDOR: | |
956 | getparam->value = dev->pci_vendor; | |
957 | break; | |
958 | case NOUVEAU_GETPARAM_PCI_DEVICE: | |
959 | getparam->value = dev->pci_device; | |
960 | break; | |
961 | case NOUVEAU_GETPARAM_BUS_TYPE: | |
962 | if (drm_device_is_agp(dev)) | |
963 | getparam->value = NV_AGP; | |
964 | else if (drm_device_is_pcie(dev)) | |
965 | getparam->value = NV_PCIE; | |
966 | else | |
967 | getparam->value = NV_PCI; | |
968 | break; | |
969 | case NOUVEAU_GETPARAM_FB_PHYSICAL: | |
970 | getparam->value = dev_priv->fb_phys; | |
971 | break; | |
972 | case NOUVEAU_GETPARAM_AGP_PHYSICAL: | |
973 | getparam->value = dev_priv->gart_info.aper_base; | |
974 | break; | |
975 | case NOUVEAU_GETPARAM_PCI_PHYSICAL: | |
976 | if (dev->sg) { | |
977 | getparam->value = (unsigned long)dev->sg->virtual; | |
978 | } else { | |
979 | NV_ERROR(dev, "Requested PCIGART address, " | |
980 | "while no PCIGART was created\n"); | |
981 | return -EINVAL; | |
982 | } | |
983 | break; | |
984 | case NOUVEAU_GETPARAM_FB_SIZE: | |
985 | getparam->value = dev_priv->fb_available_size; | |
986 | break; | |
987 | case NOUVEAU_GETPARAM_AGP_SIZE: | |
988 | getparam->value = dev_priv->gart_info.aper_size; | |
989 | break; | |
990 | case NOUVEAU_GETPARAM_VM_VRAM_BASE: | |
991 | getparam->value = dev_priv->vm_vram_base; | |
992 | break; | |
7fc74f17 MK |
993 | case NOUVEAU_GETPARAM_PTIMER_TIME: |
994 | getparam->value = dev_priv->engine.timer.read(dev); | |
995 | break; | |
69c9700b MK |
996 | case NOUVEAU_GETPARAM_GRAPH_UNITS: |
997 | /* NV40 and NV50 versions are quite different, but register | |
998 | * address is the same. User is supposed to know the card | |
999 | * family anyway... */ | |
1000 | if (dev_priv->chipset >= 0x40) { | |
1001 | getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS); | |
1002 | break; | |
1003 | } | |
1004 | /* FALLTHRU */ | |
6ee73861 BS |
1005 | default: |
1006 | NV_ERROR(dev, "unknown parameter %lld\n", getparam->param); | |
1007 | return -EINVAL; | |
1008 | } | |
1009 | ||
1010 | return 0; | |
1011 | } | |
1012 | ||
1013 | int | |
1014 | nouveau_ioctl_setparam(struct drm_device *dev, void *data, | |
1015 | struct drm_file *file_priv) | |
1016 | { | |
1017 | struct drm_nouveau_setparam *setparam = data; | |
1018 | ||
6ee73861 BS |
1019 | switch (setparam->param) { |
1020 | default: | |
1021 | NV_ERROR(dev, "unknown parameter %lld\n", setparam->param); | |
1022 | return -EINVAL; | |
1023 | } | |
1024 | ||
1025 | return 0; | |
1026 | } | |
1027 | ||
1028 | /* Wait until (value(reg) & mask) == val, up until timeout has hit */ | |
1029 | bool nouveau_wait_until(struct drm_device *dev, uint64_t timeout, | |
1030 | uint32_t reg, uint32_t mask, uint32_t val) | |
1031 | { | |
1032 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1033 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1034 | uint64_t start = ptimer->read(dev); | |
1035 | ||
1036 | do { | |
1037 | if ((nv_rd32(dev, reg) & mask) == val) | |
1038 | return true; | |
1039 | } while (ptimer->read(dev) - start < timeout); | |
1040 | ||
1041 | return false; | |
1042 | } | |
1043 | ||
1044 | /* Waits for PGRAPH to go completely idle */ | |
1045 | bool nouveau_wait_for_idle(struct drm_device *dev) | |
1046 | { | |
1047 | if (!nv_wait(NV04_PGRAPH_STATUS, 0xffffffff, 0x00000000)) { | |
1048 | NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n", | |
1049 | nv_rd32(dev, NV04_PGRAPH_STATUS)); | |
1050 | return false; | |
1051 | } | |
1052 | ||
1053 | return true; | |
1054 | } | |
1055 |