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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin | |
3 | * Copyright 2008 Stuart Bennett | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include <linux/swab.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
6ee73861 BS |
28 | #include "drmP.h" |
29 | #include "drm.h" | |
30 | #include "drm_sarea.h" | |
31 | #include "drm_crtc_helper.h" | |
32 | #include <linux/vgaarb.h> | |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
6ee73861 BS |
34 | |
35 | #include "nouveau_drv.h" | |
36 | #include "nouveau_drm.h" | |
38651674 | 37 | #include "nouveau_fbcon.h" |
a8eaebc6 | 38 | #include "nouveau_ramht.h" |
a0b25635 | 39 | #include "nouveau_gpio.h" |
330c5988 | 40 | #include "nouveau_pm.h" |
6ee73861 BS |
41 | #include "nv50_display.h" |
42 | ||
6ee73861 | 43 | static void nouveau_stub_takedown(struct drm_device *dev) {} |
ee2e0131 | 44 | static int nouveau_stub_init(struct drm_device *dev) { return 0; } |
6ee73861 BS |
45 | |
46 | static int nouveau_init_engine_ptrs(struct drm_device *dev) | |
47 | { | |
48 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
49 | struct nouveau_engine *engine = &dev_priv->engine; | |
50 | ||
51 | switch (dev_priv->chipset & 0xf0) { | |
52 | case 0x00: | |
53 | engine->instmem.init = nv04_instmem_init; | |
54 | engine->instmem.takedown = nv04_instmem_takedown; | |
55 | engine->instmem.suspend = nv04_instmem_suspend; | |
56 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
57 | engine->instmem.get = nv04_instmem_get; |
58 | engine->instmem.put = nv04_instmem_put; | |
59 | engine->instmem.map = nv04_instmem_map; | |
60 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 61 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
62 | engine->mc.init = nv04_mc_init; |
63 | engine->mc.takedown = nv04_mc_takedown; | |
64 | engine->timer.init = nv04_timer_init; | |
65 | engine->timer.read = nv04_timer_read; | |
66 | engine->timer.takedown = nv04_timer_takedown; | |
67 | engine->fb.init = nv04_fb_init; | |
68 | engine->fb.takedown = nv04_fb_takedown; | |
6ee73861 BS |
69 | engine->fifo.channels = 16; |
70 | engine->fifo.init = nv04_fifo_init; | |
5178d40d | 71 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
72 | engine->fifo.disable = nv04_fifo_disable; |
73 | engine->fifo.enable = nv04_fifo_enable; | |
74 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 75 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
76 | engine->fifo.channel_id = nv04_fifo_channel_id; |
77 | engine->fifo.create_context = nv04_fifo_create_context; | |
78 | engine->fifo.destroy_context = nv04_fifo_destroy_context; | |
79 | engine->fifo.load_context = nv04_fifo_load_context; | |
80 | engine->fifo.unload_context = nv04_fifo_unload_context; | |
c88c2e06 FJ |
81 | engine->display.early_init = nv04_display_early_init; |
82 | engine->display.late_takedown = nv04_display_late_takedown; | |
83 | engine->display.create = nv04_display_create; | |
c88c2e06 | 84 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
85 | engine->display.init = nv04_display_init; |
86 | engine->display.fini = nv04_display_fini; | |
36f1317e BS |
87 | engine->pm.clocks_get = nv04_pm_clocks_get; |
88 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
89 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
7ad2d31c | 90 | engine->vram.init = nv04_fb_vram_init; |
24f246ac | 91 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 92 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
93 | break; |
94 | case 0x10: | |
95 | engine->instmem.init = nv04_instmem_init; | |
96 | engine->instmem.takedown = nv04_instmem_takedown; | |
97 | engine->instmem.suspend = nv04_instmem_suspend; | |
98 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
99 | engine->instmem.get = nv04_instmem_get; |
100 | engine->instmem.put = nv04_instmem_put; | |
101 | engine->instmem.map = nv04_instmem_map; | |
102 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 103 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
104 | engine->mc.init = nv04_mc_init; |
105 | engine->mc.takedown = nv04_mc_takedown; | |
106 | engine->timer.init = nv04_timer_init; | |
107 | engine->timer.read = nv04_timer_read; | |
108 | engine->timer.takedown = nv04_timer_takedown; | |
109 | engine->fb.init = nv10_fb_init; | |
110 | engine->fb.takedown = nv10_fb_takedown; | |
a5cf68b0 FJ |
111 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
112 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
113 | engine->fb.free_tile_region = nv10_fb_free_tile_region; | |
6ee73861 BS |
114 | engine->fifo.channels = 32; |
115 | engine->fifo.init = nv10_fifo_init; | |
5178d40d | 116 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
117 | engine->fifo.disable = nv04_fifo_disable; |
118 | engine->fifo.enable = nv04_fifo_enable; | |
119 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 120 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
121 | engine->fifo.channel_id = nv10_fifo_channel_id; |
122 | engine->fifo.create_context = nv10_fifo_create_context; | |
3945e475 | 123 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
6ee73861 BS |
124 | engine->fifo.load_context = nv10_fifo_load_context; |
125 | engine->fifo.unload_context = nv10_fifo_unload_context; | |
c88c2e06 FJ |
126 | engine->display.early_init = nv04_display_early_init; |
127 | engine->display.late_takedown = nv04_display_late_takedown; | |
128 | engine->display.create = nv04_display_create; | |
c88c2e06 | 129 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
130 | engine->display.init = nv04_display_init; |
131 | engine->display.fini = nv04_display_fini; | |
a0b25635 BS |
132 | engine->gpio.drive = nv10_gpio_drive; |
133 | engine->gpio.sense = nv10_gpio_sense; | |
36f1317e BS |
134 | engine->pm.clocks_get = nv04_pm_clocks_get; |
135 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
136 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
7ad2d31c BS |
137 | if (dev_priv->chipset == 0x1a || |
138 | dev_priv->chipset == 0x1f) | |
139 | engine->vram.init = nv1a_fb_vram_init; | |
140 | else | |
141 | engine->vram.init = nv10_fb_vram_init; | |
24f246ac | 142 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 143 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
144 | break; |
145 | case 0x20: | |
146 | engine->instmem.init = nv04_instmem_init; | |
147 | engine->instmem.takedown = nv04_instmem_takedown; | |
148 | engine->instmem.suspend = nv04_instmem_suspend; | |
149 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
150 | engine->instmem.get = nv04_instmem_get; |
151 | engine->instmem.put = nv04_instmem_put; | |
152 | engine->instmem.map = nv04_instmem_map; | |
153 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 154 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
155 | engine->mc.init = nv04_mc_init; |
156 | engine->mc.takedown = nv04_mc_takedown; | |
157 | engine->timer.init = nv04_timer_init; | |
158 | engine->timer.read = nv04_timer_read; | |
159 | engine->timer.takedown = nv04_timer_takedown; | |
160 | engine->fb.init = nv10_fb_init; | |
161 | engine->fb.takedown = nv10_fb_takedown; | |
a5cf68b0 FJ |
162 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
163 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
164 | engine->fb.free_tile_region = nv10_fb_free_tile_region; | |
6ee73861 BS |
165 | engine->fifo.channels = 32; |
166 | engine->fifo.init = nv10_fifo_init; | |
5178d40d | 167 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
168 | engine->fifo.disable = nv04_fifo_disable; |
169 | engine->fifo.enable = nv04_fifo_enable; | |
170 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 171 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
172 | engine->fifo.channel_id = nv10_fifo_channel_id; |
173 | engine->fifo.create_context = nv10_fifo_create_context; | |
3945e475 | 174 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
6ee73861 BS |
175 | engine->fifo.load_context = nv10_fifo_load_context; |
176 | engine->fifo.unload_context = nv10_fifo_unload_context; | |
c88c2e06 FJ |
177 | engine->display.early_init = nv04_display_early_init; |
178 | engine->display.late_takedown = nv04_display_late_takedown; | |
179 | engine->display.create = nv04_display_create; | |
c88c2e06 | 180 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
181 | engine->display.init = nv04_display_init; |
182 | engine->display.fini = nv04_display_fini; | |
a0b25635 BS |
183 | engine->gpio.drive = nv10_gpio_drive; |
184 | engine->gpio.sense = nv10_gpio_sense; | |
36f1317e BS |
185 | engine->pm.clocks_get = nv04_pm_clocks_get; |
186 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
187 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
7ad2d31c | 188 | engine->vram.init = nv10_fb_vram_init; |
24f246ac | 189 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 190 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
191 | break; |
192 | case 0x30: | |
193 | engine->instmem.init = nv04_instmem_init; | |
194 | engine->instmem.takedown = nv04_instmem_takedown; | |
195 | engine->instmem.suspend = nv04_instmem_suspend; | |
196 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
197 | engine->instmem.get = nv04_instmem_get; |
198 | engine->instmem.put = nv04_instmem_put; | |
199 | engine->instmem.map = nv04_instmem_map; | |
200 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 201 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
202 | engine->mc.init = nv04_mc_init; |
203 | engine->mc.takedown = nv04_mc_takedown; | |
204 | engine->timer.init = nv04_timer_init; | |
205 | engine->timer.read = nv04_timer_read; | |
206 | engine->timer.takedown = nv04_timer_takedown; | |
8bded189 FJ |
207 | engine->fb.init = nv30_fb_init; |
208 | engine->fb.takedown = nv30_fb_takedown; | |
a5cf68b0 FJ |
209 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
210 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
211 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | |
6ee73861 BS |
212 | engine->fifo.channels = 32; |
213 | engine->fifo.init = nv10_fifo_init; | |
5178d40d | 214 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
215 | engine->fifo.disable = nv04_fifo_disable; |
216 | engine->fifo.enable = nv04_fifo_enable; | |
217 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 218 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
219 | engine->fifo.channel_id = nv10_fifo_channel_id; |
220 | engine->fifo.create_context = nv10_fifo_create_context; | |
3945e475 | 221 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
6ee73861 BS |
222 | engine->fifo.load_context = nv10_fifo_load_context; |
223 | engine->fifo.unload_context = nv10_fifo_unload_context; | |
c88c2e06 FJ |
224 | engine->display.early_init = nv04_display_early_init; |
225 | engine->display.late_takedown = nv04_display_late_takedown; | |
226 | engine->display.create = nv04_display_create; | |
c88c2e06 | 227 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
228 | engine->display.init = nv04_display_init; |
229 | engine->display.fini = nv04_display_fini; | |
a0b25635 BS |
230 | engine->gpio.drive = nv10_gpio_drive; |
231 | engine->gpio.sense = nv10_gpio_sense; | |
36f1317e BS |
232 | engine->pm.clocks_get = nv04_pm_clocks_get; |
233 | engine->pm.clocks_pre = nv04_pm_clocks_pre; | |
234 | engine->pm.clocks_set = nv04_pm_clocks_set; | |
442b626e BS |
235 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
236 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
7ad2d31c | 237 | engine->vram.init = nv10_fb_vram_init; |
24f246ac | 238 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 239 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
240 | break; |
241 | case 0x40: | |
242 | case 0x60: | |
243 | engine->instmem.init = nv04_instmem_init; | |
244 | engine->instmem.takedown = nv04_instmem_takedown; | |
245 | engine->instmem.suspend = nv04_instmem_suspend; | |
246 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
247 | engine->instmem.get = nv04_instmem_get; |
248 | engine->instmem.put = nv04_instmem_put; | |
249 | engine->instmem.map = nv04_instmem_map; | |
250 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 251 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
252 | engine->mc.init = nv40_mc_init; |
253 | engine->mc.takedown = nv40_mc_takedown; | |
254 | engine->timer.init = nv04_timer_init; | |
255 | engine->timer.read = nv04_timer_read; | |
256 | engine->timer.takedown = nv04_timer_takedown; | |
257 | engine->fb.init = nv40_fb_init; | |
258 | engine->fb.takedown = nv40_fb_takedown; | |
a5cf68b0 FJ |
259 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
260 | engine->fb.set_tile_region = nv40_fb_set_tile_region; | |
261 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | |
6ee73861 BS |
262 | engine->fifo.channels = 32; |
263 | engine->fifo.init = nv40_fifo_init; | |
5178d40d | 264 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
265 | engine->fifo.disable = nv04_fifo_disable; |
266 | engine->fifo.enable = nv04_fifo_enable; | |
267 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 268 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
269 | engine->fifo.channel_id = nv10_fifo_channel_id; |
270 | engine->fifo.create_context = nv40_fifo_create_context; | |
3945e475 | 271 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
6ee73861 BS |
272 | engine->fifo.load_context = nv40_fifo_load_context; |
273 | engine->fifo.unload_context = nv40_fifo_unload_context; | |
c88c2e06 FJ |
274 | engine->display.early_init = nv04_display_early_init; |
275 | engine->display.late_takedown = nv04_display_late_takedown; | |
276 | engine->display.create = nv04_display_create; | |
c88c2e06 | 277 | engine->display.destroy = nv04_display_destroy; |
2a44e499 BS |
278 | engine->display.init = nv04_display_init; |
279 | engine->display.fini = nv04_display_fini; | |
47e5d5cb BS |
280 | engine->gpio.init = nv10_gpio_init; |
281 | engine->gpio.fini = nv10_gpio_fini; | |
a0b25635 BS |
282 | engine->gpio.drive = nv10_gpio_drive; |
283 | engine->gpio.sense = nv10_gpio_sense; | |
47e5d5cb | 284 | engine->gpio.irq_enable = nv10_gpio_irq_enable; |
1262a206 BS |
285 | engine->pm.clocks_get = nv40_pm_clocks_get; |
286 | engine->pm.clocks_pre = nv40_pm_clocks_pre; | |
287 | engine->pm.clocks_set = nv40_pm_clocks_set; | |
442b626e BS |
288 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
289 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 | 290 | engine->pm.temp_get = nv40_temp_get; |
69346180 BS |
291 | engine->pm.pwm_get = nv40_pm_pwm_get; |
292 | engine->pm.pwm_set = nv40_pm_pwm_set; | |
7ad2d31c | 293 | engine->vram.init = nv10_fb_vram_init; |
24f246ac | 294 | engine->vram.takedown = nouveau_stub_takedown; |
60d2a88a | 295 | engine->vram.flags_valid = nouveau_mem_flags_valid; |
6ee73861 BS |
296 | break; |
297 | case 0x50: | |
298 | case 0x80: /* gotta love NVIDIA's consistency.. */ | |
299 | case 0x90: | |
d9f61c2d | 300 | case 0xa0: |
6ee73861 BS |
301 | engine->instmem.init = nv50_instmem_init; |
302 | engine->instmem.takedown = nv50_instmem_takedown; | |
303 | engine->instmem.suspend = nv50_instmem_suspend; | |
304 | engine->instmem.resume = nv50_instmem_resume; | |
e41115d0 BS |
305 | engine->instmem.get = nv50_instmem_get; |
306 | engine->instmem.put = nv50_instmem_put; | |
307 | engine->instmem.map = nv50_instmem_map; | |
308 | engine->instmem.unmap = nv50_instmem_unmap; | |
734ee835 BS |
309 | if (dev_priv->chipset == 0x50) |
310 | engine->instmem.flush = nv50_instmem_flush; | |
311 | else | |
312 | engine->instmem.flush = nv84_instmem_flush; | |
6ee73861 BS |
313 | engine->mc.init = nv50_mc_init; |
314 | engine->mc.takedown = nv50_mc_takedown; | |
315 | engine->timer.init = nv04_timer_init; | |
316 | engine->timer.read = nv04_timer_read; | |
317 | engine->timer.takedown = nv04_timer_takedown; | |
304424e1 MK |
318 | engine->fb.init = nv50_fb_init; |
319 | engine->fb.takedown = nv50_fb_takedown; | |
6ee73861 BS |
320 | engine->fifo.channels = 128; |
321 | engine->fifo.init = nv50_fifo_init; | |
322 | engine->fifo.takedown = nv50_fifo_takedown; | |
323 | engine->fifo.disable = nv04_fifo_disable; | |
324 | engine->fifo.enable = nv04_fifo_enable; | |
325 | engine->fifo.reassign = nv04_fifo_reassign; | |
326 | engine->fifo.channel_id = nv50_fifo_channel_id; | |
327 | engine->fifo.create_context = nv50_fifo_create_context; | |
328 | engine->fifo.destroy_context = nv50_fifo_destroy_context; | |
329 | engine->fifo.load_context = nv50_fifo_load_context; | |
330 | engine->fifo.unload_context = nv50_fifo_unload_context; | |
56ac7475 | 331 | engine->fifo.tlb_flush = nv50_fifo_tlb_flush; |
c88c2e06 FJ |
332 | engine->display.early_init = nv50_display_early_init; |
333 | engine->display.late_takedown = nv50_display_late_takedown; | |
334 | engine->display.create = nv50_display_create; | |
c88c2e06 | 335 | engine->display.destroy = nv50_display_destroy; |
2a44e499 BS |
336 | engine->display.init = nv50_display_init; |
337 | engine->display.fini = nv50_display_fini; | |
ee2e0131 | 338 | engine->gpio.init = nv50_gpio_init; |
a0b25635 BS |
339 | engine->gpio.fini = nv50_gpio_fini; |
340 | engine->gpio.drive = nv50_gpio_drive; | |
341 | engine->gpio.sense = nv50_gpio_sense; | |
ee2e0131 | 342 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
fade7ad5 | 343 | switch (dev_priv->chipset) { |
bd2e597d BS |
344 | case 0x84: |
345 | case 0x86: | |
346 | case 0x92: | |
347 | case 0x94: | |
348 | case 0x96: | |
349 | case 0x98: | |
350 | case 0xa0: | |
5f80198e BS |
351 | case 0xaa: |
352 | case 0xac: | |
bd2e597d | 353 | case 0x50: |
f3fbaf34 BS |
354 | engine->pm.clocks_get = nv50_pm_clocks_get; |
355 | engine->pm.clocks_pre = nv50_pm_clocks_pre; | |
356 | engine->pm.clocks_set = nv50_pm_clocks_set; | |
fade7ad5 | 357 | break; |
bd2e597d | 358 | default: |
ca94a71f BS |
359 | engine->pm.clocks_get = nva3_pm_clocks_get; |
360 | engine->pm.clocks_pre = nva3_pm_clocks_pre; | |
361 | engine->pm.clocks_set = nva3_pm_clocks_set; | |
bd2e597d | 362 | break; |
fade7ad5 | 363 | } |
02c30ca0 BS |
364 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
365 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 FJ |
366 | if (dev_priv->chipset >= 0x84) |
367 | engine->pm.temp_get = nv84_temp_get; | |
368 | else | |
369 | engine->pm.temp_get = nv40_temp_get; | |
5a4267ab BS |
370 | engine->pm.pwm_get = nv50_pm_pwm_get; |
371 | engine->pm.pwm_set = nv50_pm_pwm_set; | |
60d2a88a | 372 | engine->vram.init = nv50_vram_init; |
24f246ac | 373 | engine->vram.takedown = nv50_vram_fini; |
60d2a88a BS |
374 | engine->vram.get = nv50_vram_new; |
375 | engine->vram.put = nv50_vram_del; | |
376 | engine->vram.flags_valid = nv50_vram_flags_valid; | |
6ee73861 | 377 | break; |
d9f61c2d | 378 | case 0xc0: |
4b223eef BS |
379 | engine->instmem.init = nvc0_instmem_init; |
380 | engine->instmem.takedown = nvc0_instmem_takedown; | |
381 | engine->instmem.suspend = nvc0_instmem_suspend; | |
382 | engine->instmem.resume = nvc0_instmem_resume; | |
8984e046 BS |
383 | engine->instmem.get = nv50_instmem_get; |
384 | engine->instmem.put = nv50_instmem_put; | |
385 | engine->instmem.map = nv50_instmem_map; | |
386 | engine->instmem.unmap = nv50_instmem_unmap; | |
387 | engine->instmem.flush = nv84_instmem_flush; | |
4b223eef BS |
388 | engine->mc.init = nv50_mc_init; |
389 | engine->mc.takedown = nv50_mc_takedown; | |
390 | engine->timer.init = nv04_timer_init; | |
391 | engine->timer.read = nv04_timer_read; | |
392 | engine->timer.takedown = nv04_timer_takedown; | |
393 | engine->fb.init = nvc0_fb_init; | |
394 | engine->fb.takedown = nvc0_fb_takedown; | |
4b223eef BS |
395 | engine->fifo.channels = 128; |
396 | engine->fifo.init = nvc0_fifo_init; | |
397 | engine->fifo.takedown = nvc0_fifo_takedown; | |
398 | engine->fifo.disable = nvc0_fifo_disable; | |
399 | engine->fifo.enable = nvc0_fifo_enable; | |
400 | engine->fifo.reassign = nvc0_fifo_reassign; | |
401 | engine->fifo.channel_id = nvc0_fifo_channel_id; | |
402 | engine->fifo.create_context = nvc0_fifo_create_context; | |
403 | engine->fifo.destroy_context = nvc0_fifo_destroy_context; | |
404 | engine->fifo.load_context = nvc0_fifo_load_context; | |
405 | engine->fifo.unload_context = nvc0_fifo_unload_context; | |
406 | engine->display.early_init = nv50_display_early_init; | |
407 | engine->display.late_takedown = nv50_display_late_takedown; | |
408 | engine->display.create = nv50_display_create; | |
4b223eef | 409 | engine->display.destroy = nv50_display_destroy; |
2a44e499 BS |
410 | engine->display.init = nv50_display_init; |
411 | engine->display.fini = nv50_display_fini; | |
4b223eef | 412 | engine->gpio.init = nv50_gpio_init; |
a0b25635 BS |
413 | engine->gpio.fini = nv50_gpio_fini; |
414 | engine->gpio.drive = nv50_gpio_drive; | |
415 | engine->gpio.sense = nv50_gpio_sense; | |
4b223eef | 416 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
8984e046 | 417 | engine->vram.init = nvc0_vram_init; |
24f246ac | 418 | engine->vram.takedown = nv50_vram_fini; |
8984e046 BS |
419 | engine->vram.get = nvc0_vram_new; |
420 | engine->vram.put = nv50_vram_del; | |
421 | engine->vram.flags_valid = nvc0_vram_flags_valid; | |
74cfad18 | 422 | engine->pm.temp_get = nv84_temp_get; |
354d0781 | 423 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
045da4e5 BS |
424 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
425 | engine->pm.clocks_set = nvc0_pm_clocks_set; | |
3c71c233 | 426 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
da1dc4cf | 427 | engine->pm.voltage_set = nouveau_voltage_gpio_set; |
5a4267ab BS |
428 | engine->pm.pwm_get = nv50_pm_pwm_get; |
429 | engine->pm.pwm_set = nv50_pm_pwm_set; | |
4b223eef | 430 | break; |
d9f61c2d BS |
431 | case 0xd0: |
432 | engine->instmem.init = nvc0_instmem_init; | |
433 | engine->instmem.takedown = nvc0_instmem_takedown; | |
434 | engine->instmem.suspend = nvc0_instmem_suspend; | |
435 | engine->instmem.resume = nvc0_instmem_resume; | |
436 | engine->instmem.get = nv50_instmem_get; | |
437 | engine->instmem.put = nv50_instmem_put; | |
438 | engine->instmem.map = nv50_instmem_map; | |
439 | engine->instmem.unmap = nv50_instmem_unmap; | |
440 | engine->instmem.flush = nv84_instmem_flush; | |
441 | engine->mc.init = nv50_mc_init; | |
442 | engine->mc.takedown = nv50_mc_takedown; | |
443 | engine->timer.init = nv04_timer_init; | |
444 | engine->timer.read = nv04_timer_read; | |
445 | engine->timer.takedown = nv04_timer_takedown; | |
446 | engine->fb.init = nvc0_fb_init; | |
447 | engine->fb.takedown = nvc0_fb_takedown; | |
448 | engine->fifo.channels = 128; | |
449 | engine->fifo.init = nvc0_fifo_init; | |
450 | engine->fifo.takedown = nvc0_fifo_takedown; | |
451 | engine->fifo.disable = nvc0_fifo_disable; | |
452 | engine->fifo.enable = nvc0_fifo_enable; | |
453 | engine->fifo.reassign = nvc0_fifo_reassign; | |
454 | engine->fifo.channel_id = nvc0_fifo_channel_id; | |
455 | engine->fifo.create_context = nvc0_fifo_create_context; | |
456 | engine->fifo.destroy_context = nvc0_fifo_destroy_context; | |
457 | engine->fifo.load_context = nvc0_fifo_load_context; | |
458 | engine->fifo.unload_context = nvc0_fifo_unload_context; | |
459 | engine->display.early_init = nouveau_stub_init; | |
460 | engine->display.late_takedown = nouveau_stub_takedown; | |
26f6d88b | 461 | engine->display.create = nvd0_display_create; |
26f6d88b | 462 | engine->display.destroy = nvd0_display_destroy; |
2a44e499 BS |
463 | engine->display.init = nvd0_display_init; |
464 | engine->display.fini = nvd0_display_fini; | |
d7f8172c | 465 | engine->gpio.init = nv50_gpio_init; |
a0b25635 BS |
466 | engine->gpio.fini = nv50_gpio_fini; |
467 | engine->gpio.drive = nvd0_gpio_drive; | |
468 | engine->gpio.sense = nvd0_gpio_sense; | |
d7f8172c | 469 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
d9f61c2d BS |
470 | engine->vram.init = nvc0_vram_init; |
471 | engine->vram.takedown = nv50_vram_fini; | |
472 | engine->vram.get = nvc0_vram_new; | |
473 | engine->vram.put = nv50_vram_del; | |
474 | engine->vram.flags_valid = nvc0_vram_flags_valid; | |
61091837 | 475 | engine->pm.temp_get = nv84_temp_get; |
4784e4aa | 476 | engine->pm.clocks_get = nvc0_pm_clocks_get; |
045da4e5 BS |
477 | engine->pm.clocks_pre = nvc0_pm_clocks_pre; |
478 | engine->pm.clocks_set = nvc0_pm_clocks_set; | |
4784e4aa BS |
479 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
480 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
d9f61c2d | 481 | break; |
6ee73861 BS |
482 | default: |
483 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); | |
484 | return 1; | |
485 | } | |
486 | ||
03bc9675 BS |
487 | /* headless mode */ |
488 | if (nouveau_modeset == 2) { | |
489 | engine->display.early_init = nouveau_stub_init; | |
490 | engine->display.late_takedown = nouveau_stub_takedown; | |
491 | engine->display.create = nouveau_stub_init; | |
492 | engine->display.init = nouveau_stub_init; | |
493 | engine->display.destroy = nouveau_stub_takedown; | |
494 | } | |
495 | ||
6ee73861 BS |
496 | return 0; |
497 | } | |
498 | ||
499 | static unsigned int | |
500 | nouveau_vga_set_decode(void *priv, bool state) | |
501 | { | |
9967b948 MK |
502 | struct drm_device *dev = priv; |
503 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
504 | ||
505 | if (dev_priv->chipset >= 0x40) | |
506 | nv_wr32(dev, 0x88054, state); | |
507 | else | |
508 | nv_wr32(dev, 0x1854, state); | |
509 | ||
6ee73861 BS |
510 | if (state) |
511 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
512 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
513 | else | |
514 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
515 | } | |
516 | ||
6a9ee8af DA |
517 | static void nouveau_switcheroo_set_state(struct pci_dev *pdev, |
518 | enum vga_switcheroo_state state) | |
519 | { | |
fbf81762 | 520 | struct drm_device *dev = pci_get_drvdata(pdev); |
6a9ee8af DA |
521 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
522 | if (state == VGA_SWITCHEROO_ON) { | |
523 | printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); | |
5bcf719b | 524 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 525 | nouveau_pci_resume(pdev); |
fbf81762 | 526 | drm_kms_helper_poll_enable(dev); |
5bcf719b | 527 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af DA |
528 | } else { |
529 | printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); | |
5bcf719b | 530 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
fbf81762 | 531 | drm_kms_helper_poll_disable(dev); |
d099230c | 532 | nouveau_switcheroo_optimus_dsm(); |
6a9ee8af | 533 | nouveau_pci_suspend(pdev, pmm); |
5bcf719b | 534 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
535 | } |
536 | } | |
537 | ||
8d608aa6 DA |
538 | static void nouveau_switcheroo_reprobe(struct pci_dev *pdev) |
539 | { | |
540 | struct drm_device *dev = pci_get_drvdata(pdev); | |
541 | nouveau_fbcon_output_poll_changed(dev); | |
542 | } | |
543 | ||
6a9ee8af DA |
544 | static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) |
545 | { | |
546 | struct drm_device *dev = pci_get_drvdata(pdev); | |
547 | bool can_switch; | |
548 | ||
549 | spin_lock(&dev->count_lock); | |
550 | can_switch = (dev->open_count == 0); | |
551 | spin_unlock(&dev->count_lock); | |
552 | return can_switch; | |
553 | } | |
554 | ||
6ee73861 BS |
555 | int |
556 | nouveau_card_init(struct drm_device *dev) | |
557 | { | |
558 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
559 | struct nouveau_engine *engine; | |
eea55c89 | 560 | int ret, e = 0; |
6ee73861 | 561 | |
6ee73861 | 562 | vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); |
6a9ee8af | 563 | vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state, |
8d608aa6 | 564 | nouveau_switcheroo_reprobe, |
6a9ee8af | 565 | nouveau_switcheroo_can_switch); |
6ee73861 BS |
566 | |
567 | /* Initialise internal driver API hooks */ | |
568 | ret = nouveau_init_engine_ptrs(dev); | |
569 | if (ret) | |
c5804be0 | 570 | goto out; |
6ee73861 | 571 | engine = &dev_priv->engine; |
cff5c133 | 572 | spin_lock_init(&dev_priv->channels.lock); |
a5cf68b0 | 573 | spin_lock_init(&dev_priv->tile.lock); |
ff9e5279 | 574 | spin_lock_init(&dev_priv->context_switch_lock); |
04eb34a4 | 575 | spin_lock_init(&dev_priv->vm_lock); |
6ee73861 | 576 | |
c88c2e06 FJ |
577 | /* Make the CRTCs and I2C buses accessible */ |
578 | ret = engine->display.early_init(dev); | |
579 | if (ret) | |
580 | goto out; | |
581 | ||
6ee73861 | 582 | /* Parse BIOS tables / Run init tables if card not POSTed */ |
cd0b072f BS |
583 | ret = nouveau_bios_init(dev); |
584 | if (ret) | |
c88c2e06 | 585 | goto out_display_early; |
6ee73861 | 586 | |
4c5df493 BS |
587 | /* workaround an odd issue on nvc1 by disabling the device's |
588 | * nosnoop capability. hopefully won't cause issues until a | |
589 | * better fix is found - assuming there is one... | |
590 | */ | |
591 | if (dev_priv->chipset == 0xc1) { | |
592 | nv_mask(dev, 0x00088080, 0x00000800, 0x00000000); | |
593 | } | |
594 | ||
330c5988 BS |
595 | nouveau_pm_init(dev); |
596 | ||
24f246ac | 597 | ret = engine->vram.init(dev); |
a76fb4e8 BS |
598 | if (ret) |
599 | goto out_bios; | |
600 | ||
fbd2895e | 601 | ret = nouveau_gpuobj_init(dev); |
6ee73861 | 602 | if (ret) |
fbd2895e | 603 | goto out_vram; |
6ee73861 | 604 | |
6ee73861 BS |
605 | ret = engine->instmem.init(dev); |
606 | if (ret) | |
fbd2895e | 607 | goto out_gpuobj; |
6ee73861 | 608 | |
24f246ac | 609 | ret = nouveau_mem_vram_init(dev); |
6ee73861 | 610 | if (ret) |
c5804be0 | 611 | goto out_instmem; |
6ee73861 | 612 | |
24f246ac BS |
613 | ret = nouveau_mem_gart_init(dev); |
614 | if (ret) | |
615 | goto out_ttmvram; | |
616 | ||
6ee73861 BS |
617 | /* PMC */ |
618 | ret = engine->mc.init(dev); | |
619 | if (ret) | |
fbd2895e | 620 | goto out_gart; |
6ee73861 | 621 | |
ee2e0131 | 622 | /* PGPIO */ |
a0b25635 | 623 | ret = nouveau_gpio_create(dev); |
ee2e0131 BS |
624 | if (ret) |
625 | goto out_mc; | |
626 | ||
6ee73861 BS |
627 | /* PTIMER */ |
628 | ret = engine->timer.init(dev); | |
629 | if (ret) | |
ee2e0131 | 630 | goto out_gpio; |
6ee73861 BS |
631 | |
632 | /* PFB */ | |
633 | ret = engine->fb.init(dev); | |
634 | if (ret) | |
c5804be0 | 635 | goto out_timer; |
6ee73861 | 636 | |
aba99a84 | 637 | if (!dev_priv->noaccel) { |
18b54c4d BS |
638 | switch (dev_priv->card_type) { |
639 | case NV_04: | |
640 | nv04_graph_create(dev); | |
641 | break; | |
642 | case NV_10: | |
643 | nv10_graph_create(dev); | |
644 | break; | |
645 | case NV_20: | |
646 | case NV_30: | |
647 | nv20_graph_create(dev); | |
648 | break; | |
649 | case NV_40: | |
650 | nv40_graph_create(dev); | |
651 | break; | |
652 | case NV_50: | |
653 | nv50_graph_create(dev); | |
654 | break; | |
655 | case NV_C0: | |
06784090 | 656 | case NV_D0: |
18b54c4d BS |
657 | nvc0_graph_create(dev); |
658 | break; | |
659 | default: | |
660 | break; | |
661 | } | |
6dfdd7a6 | 662 | |
7ff5441e | 663 | switch (dev_priv->chipset) { |
18b54c4d BS |
664 | case 0x84: |
665 | case 0x86: | |
666 | case 0x92: | |
667 | case 0x94: | |
668 | case 0x96: | |
669 | case 0xa0: | |
670 | nv84_crypt_create(dev); | |
7ff5441e | 671 | break; |
8f27c543 BS |
672 | case 0x98: |
673 | case 0xaa: | |
674 | case 0xac: | |
675 | nv98_crypt_create(dev); | |
676 | break; | |
7ff5441e | 677 | } |
7ff5441e | 678 | |
18b54c4d BS |
679 | switch (dev_priv->card_type) { |
680 | case NV_50: | |
681 | switch (dev_priv->chipset) { | |
682 | case 0xa3: | |
683 | case 0xa5: | |
684 | case 0xa8: | |
685 | case 0xaf: | |
686 | nva3_copy_create(dev); | |
687 | break; | |
688 | } | |
689 | break; | |
690 | case NV_C0: | |
691 | nvc0_copy_create(dev, 0); | |
692 | nvc0_copy_create(dev, 1); | |
693 | break; | |
694 | default: | |
695 | break; | |
696 | } | |
697 | ||
8f27c543 BS |
698 | if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) { |
699 | nv84_bsp_create(dev); | |
700 | nv84_vp_create(dev); | |
701 | nv98_ppp_create(dev); | |
702 | } else | |
703 | if (dev_priv->chipset >= 0x84) { | |
704 | nv50_mpeg_create(dev); | |
705 | nv84_bsp_create(dev); | |
706 | nv84_vp_create(dev); | |
707 | } else | |
708 | if (dev_priv->chipset >= 0x50) { | |
709 | nv50_mpeg_create(dev); | |
710 | } else | |
52d07331 BS |
711 | if (dev_priv->card_type == NV_40 || |
712 | dev_priv->chipset == 0x31 || | |
713 | dev_priv->chipset == 0x34 || | |
8f27c543 | 714 | dev_priv->chipset == 0x36) { |
323dcac5 | 715 | nv31_mpeg_create(dev); |
8f27c543 | 716 | } |
a02ccc7f | 717 | |
6dfdd7a6 BS |
718 | for (e = 0; e < NVOBJ_ENGINE_NR; e++) { |
719 | if (dev_priv->eng[e]) { | |
720 | ret = dev_priv->eng[e]->init(dev, e); | |
721 | if (ret) | |
722 | goto out_engine; | |
723 | } | |
724 | } | |
725 | ||
a32ed69d MK |
726 | /* PFIFO */ |
727 | ret = engine->fifo.init(dev); | |
728 | if (ret) | |
a82dd49f | 729 | goto out_engine; |
a32ed69d | 730 | } |
6ee73861 | 731 | |
1575b364 BS |
732 | ret = nouveau_irq_init(dev); |
733 | if (ret) | |
734 | goto out_fifo; | |
735 | ||
27d5030a | 736 | ret = nouveau_display_create(dev); |
e88efe05 | 737 | if (ret) |
1575b364 | 738 | goto out_irq; |
6ee73861 | 739 | |
10b461e4 BS |
740 | nouveau_backlight_init(dev); |
741 | ||
a82dd49f | 742 | if (dev_priv->eng[NVOBJ_ENGINE_GR]) { |
0c6c1c2f | 743 | ret = nouveau_fence_init(dev); |
0735f62e | 744 | if (ret) |
1575b364 | 745 | goto out_disp; |
0c6c1c2f | 746 | |
1575b364 BS |
747 | ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL, |
748 | NvDmaFB, NvDmaTT); | |
0c6c1c2f FJ |
749 | if (ret) |
750 | goto out_fence; | |
1575b364 BS |
751 | |
752 | mutex_unlock(&dev_priv->channel->mutex); | |
753 | } | |
754 | ||
755 | if (dev->mode_config.num_crtc) { | |
f62b27db | 756 | ret = nouveau_display_init(dev); |
1575b364 BS |
757 | if (ret) |
758 | goto out_chan; | |
759 | ||
760 | nouveau_fbcon_init(dev); | |
6ee73861 BS |
761 | } |
762 | ||
6ee73861 | 763 | return 0; |
c5804be0 | 764 | |
1575b364 BS |
765 | out_chan: |
766 | nouveau_channel_put_unlocked(&dev_priv->channel); | |
0c6c1c2f FJ |
767 | out_fence: |
768 | nouveau_fence_fini(dev); | |
1575b364 | 769 | out_disp: |
10b461e4 | 770 | nouveau_backlight_exit(dev); |
27d5030a | 771 | nouveau_display_destroy(dev); |
c5804be0 | 772 | out_irq: |
35fa2f2a | 773 | nouveau_irq_fini(dev); |
c5804be0 | 774 | out_fifo: |
aba99a84 | 775 | if (!dev_priv->noaccel) |
a32ed69d | 776 | engine->fifo.takedown(dev); |
6dfdd7a6 | 777 | out_engine: |
aba99a84 | 778 | if (!dev_priv->noaccel) { |
6dfdd7a6 | 779 | for (e = e - 1; e >= 0; e--) { |
2703c21a BS |
780 | if (!dev_priv->eng[e]) |
781 | continue; | |
6c320fef | 782 | dev_priv->eng[e]->fini(dev, e, false); |
2703c21a | 783 | dev_priv->eng[e]->destroy(dev,e ); |
6dfdd7a6 BS |
784 | } |
785 | } | |
786 | ||
c5804be0 MK |
787 | engine->fb.takedown(dev); |
788 | out_timer: | |
789 | engine->timer.takedown(dev); | |
ee2e0131 | 790 | out_gpio: |
a0b25635 | 791 | nouveau_gpio_destroy(dev); |
c5804be0 MK |
792 | out_mc: |
793 | engine->mc.takedown(dev); | |
fbd2895e BS |
794 | out_gart: |
795 | nouveau_mem_gart_fini(dev); | |
24f246ac BS |
796 | out_ttmvram: |
797 | nouveau_mem_vram_fini(dev); | |
c5804be0 MK |
798 | out_instmem: |
799 | engine->instmem.takedown(dev); | |
fbd2895e BS |
800 | out_gpuobj: |
801 | nouveau_gpuobj_takedown(dev); | |
802 | out_vram: | |
24f246ac | 803 | engine->vram.takedown(dev); |
c5804be0 | 804 | out_bios: |
330c5988 | 805 | nouveau_pm_fini(dev); |
c5804be0 | 806 | nouveau_bios_takedown(dev); |
c88c2e06 FJ |
807 | out_display_early: |
808 | engine->display.late_takedown(dev); | |
c5804be0 MK |
809 | out: |
810 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
811 | return ret; | |
6ee73861 BS |
812 | } |
813 | ||
814 | static void nouveau_card_takedown(struct drm_device *dev) | |
815 | { | |
816 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
817 | struct nouveau_engine *engine = &dev_priv->engine; | |
6dfdd7a6 | 818 | int e; |
6ee73861 | 819 | |
1575b364 | 820 | if (dev->mode_config.num_crtc) { |
1575b364 | 821 | nouveau_fbcon_fini(dev); |
f62b27db | 822 | nouveau_display_fini(dev); |
1575b364 | 823 | } |
06b75e35 | 824 | |
a82dd49f | 825 | if (dev_priv->channel) { |
36c952e8 | 826 | nouveau_channel_put_unlocked(&dev_priv->channel); |
06b75e35 | 827 | nouveau_fence_fini(dev); |
b6d3d871 | 828 | } |
6ee73861 | 829 | |
10b461e4 | 830 | nouveau_backlight_exit(dev); |
27d5030a | 831 | nouveau_display_destroy(dev); |
06b75e35 | 832 | |
aba99a84 | 833 | if (!dev_priv->noaccel) { |
b6d3d871 | 834 | engine->fifo.takedown(dev); |
6dfdd7a6 BS |
835 | for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) { |
836 | if (dev_priv->eng[e]) { | |
6c320fef | 837 | dev_priv->eng[e]->fini(dev, e, false); |
6dfdd7a6 BS |
838 | dev_priv->eng[e]->destroy(dev,e ); |
839 | } | |
840 | } | |
b6d3d871 BS |
841 | } |
842 | engine->fb.takedown(dev); | |
843 | engine->timer.takedown(dev); | |
a0b25635 | 844 | nouveau_gpio_destroy(dev); |
b6d3d871 | 845 | engine->mc.takedown(dev); |
c88c2e06 | 846 | engine->display.late_takedown(dev); |
6ee73861 | 847 | |
97666109 JR |
848 | if (dev_priv->vga_ram) { |
849 | nouveau_bo_unpin(dev_priv->vga_ram); | |
850 | nouveau_bo_ref(NULL, &dev_priv->vga_ram); | |
851 | } | |
852 | ||
b6d3d871 BS |
853 | mutex_lock(&dev->struct_mutex); |
854 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM); | |
855 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT); | |
856 | mutex_unlock(&dev->struct_mutex); | |
fbd2895e | 857 | nouveau_mem_gart_fini(dev); |
24f246ac | 858 | nouveau_mem_vram_fini(dev); |
6ee73861 | 859 | |
b6d3d871 | 860 | engine->instmem.takedown(dev); |
fbd2895e | 861 | nouveau_gpuobj_takedown(dev); |
24f246ac | 862 | engine->vram.takedown(dev); |
6ee73861 | 863 | |
35fa2f2a | 864 | nouveau_irq_fini(dev); |
6ee73861 | 865 | |
330c5988 | 866 | nouveau_pm_fini(dev); |
b6d3d871 | 867 | nouveau_bios_takedown(dev); |
6ee73861 | 868 | |
b6d3d871 | 869 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
6ee73861 BS |
870 | } |
871 | ||
3f0a68d8 BS |
872 | int |
873 | nouveau_open(struct drm_device *dev, struct drm_file *file_priv) | |
874 | { | |
fe32b16e | 875 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
3f0a68d8 | 876 | struct nouveau_fpriv *fpriv; |
e41f26e7 | 877 | int ret; |
3f0a68d8 BS |
878 | |
879 | fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); | |
880 | if (unlikely(!fpriv)) | |
881 | return -ENOMEM; | |
882 | ||
883 | spin_lock_init(&fpriv->lock); | |
e8a863c1 BS |
884 | INIT_LIST_HEAD(&fpriv->channels); |
885 | ||
e41f26e7 BS |
886 | if (dev_priv->card_type == NV_50) { |
887 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL, | |
888 | &fpriv->vm); | |
889 | if (ret) { | |
890 | kfree(fpriv); | |
891 | return ret; | |
892 | } | |
893 | } else | |
894 | if (dev_priv->card_type >= NV_C0) { | |
5de8037a BS |
895 | ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL, |
896 | &fpriv->vm); | |
897 | if (ret) { | |
898 | kfree(fpriv); | |
899 | return ret; | |
900 | } | |
e41f26e7 | 901 | } |
fe32b16e | 902 | |
3f0a68d8 BS |
903 | file_priv->driver_priv = fpriv; |
904 | return 0; | |
905 | } | |
906 | ||
6ee73861 BS |
907 | /* here a client dies, release the stuff that was allocated for its |
908 | * file_priv */ | |
909 | void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) | |
910 | { | |
911 | nouveau_channel_cleanup(dev, file_priv); | |
912 | } | |
913 | ||
3f0a68d8 BS |
914 | void |
915 | nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv) | |
916 | { | |
917 | struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv); | |
fe32b16e | 918 | nouveau_vm_ref(NULL, &fpriv->vm, NULL); |
3f0a68d8 BS |
919 | kfree(fpriv); |
920 | } | |
921 | ||
6ee73861 BS |
922 | /* first module load, setup the mmio/fb mapping */ |
923 | /* KMS: we need mmio at load time, not when the first drm client opens. */ | |
924 | int nouveau_firstopen(struct drm_device *dev) | |
925 | { | |
926 | return 0; | |
927 | } | |
928 | ||
929 | /* if we have an OF card, copy vbios to RAMIN */ | |
930 | static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev) | |
931 | { | |
932 | #if defined(__powerpc__) | |
933 | int size, i; | |
934 | const uint32_t *bios; | |
935 | struct device_node *dn = pci_device_to_OF_node(dev->pdev); | |
936 | if (!dn) { | |
937 | NV_INFO(dev, "Unable to get the OF node\n"); | |
938 | return; | |
939 | } | |
940 | ||
941 | bios = of_get_property(dn, "NVDA,BMP", &size); | |
942 | if (bios) { | |
943 | for (i = 0; i < size; i += 4) | |
944 | nv_wi32(dev, i, bios[i/4]); | |
945 | NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size); | |
946 | } else { | |
947 | NV_INFO(dev, "Unable to get the OF bios\n"); | |
948 | } | |
949 | #endif | |
950 | } | |
951 | ||
06415c56 MS |
952 | static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev) |
953 | { | |
954 | struct pci_dev *pdev = dev->pdev; | |
955 | struct apertures_struct *aper = alloc_apertures(3); | |
956 | if (!aper) | |
957 | return NULL; | |
958 | ||
959 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
960 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
961 | aper->count = 1; | |
962 | ||
963 | if (pci_resource_len(pdev, 2)) { | |
964 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
965 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
966 | aper->count++; | |
967 | } | |
968 | ||
969 | if (pci_resource_len(pdev, 3)) { | |
970 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
971 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
972 | aper->count++; | |
973 | } | |
974 | ||
975 | return aper; | |
976 | } | |
977 | ||
978 | static int nouveau_remove_conflicting_drivers(struct drm_device *dev) | |
979 | { | |
980 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
3b9676e7 | 981 | bool primary = false; |
06415c56 MS |
982 | dev_priv->apertures = nouveau_get_apertures(dev); |
983 | if (!dev_priv->apertures) | |
984 | return -ENOMEM; | |
985 | ||
3b9676e7 MS |
986 | #ifdef CONFIG_X86 |
987 | primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
988 | #endif | |
f212949c | 989 | |
3b9676e7 | 990 | remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary); |
06415c56 MS |
991 | return 0; |
992 | } | |
993 | ||
6ee73861 BS |
994 | int nouveau_load(struct drm_device *dev, unsigned long flags) |
995 | { | |
996 | struct drm_nouveau_private *dev_priv; | |
f2cbe46f | 997 | uint32_t reg0, strap; |
6ee73861 | 998 | resource_size_t mmio_start_offs; |
cd0b072f | 999 | int ret; |
6ee73861 BS |
1000 | |
1001 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
a0d069ea DC |
1002 | if (!dev_priv) { |
1003 | ret = -ENOMEM; | |
1004 | goto err_out; | |
1005 | } | |
6ee73861 BS |
1006 | dev->dev_private = dev_priv; |
1007 | dev_priv->dev = dev; | |
1008 | ||
466e69b8 DA |
1009 | pci_set_master(dev->pdev); |
1010 | ||
6ee73861 | 1011 | dev_priv->flags = flags & NOUVEAU_FLAGS; |
6ee73861 BS |
1012 | |
1013 | NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", | |
1014 | dev->pci_vendor, dev->pci_device, dev->pdev->class); | |
1015 | ||
6ee73861 BS |
1016 | /* resource 0 is mmio regs */ |
1017 | /* resource 1 is linear FB */ | |
1018 | /* resource 2 is RAMIN (mmio regs + 0x1000000) */ | |
1019 | /* resource 6 is bios */ | |
1020 | ||
1021 | /* map the mmio regs */ | |
1022 | mmio_start_offs = pci_resource_start(dev->pdev, 0); | |
1023 | dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000); | |
1024 | if (!dev_priv->mmio) { | |
1025 | NV_ERROR(dev, "Unable to initialize the mmio mapping. " | |
1026 | "Please report your setup to " DRIVER_EMAIL "\n"); | |
a0d069ea | 1027 | ret = -EINVAL; |
d82f8e6c | 1028 | goto err_priv; |
6ee73861 BS |
1029 | } |
1030 | NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", | |
1031 | (unsigned long long)mmio_start_offs); | |
1032 | ||
1033 | #ifdef __BIG_ENDIAN | |
1034 | /* Put the card in BE mode if it's not */ | |
0897554c BS |
1035 | if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001) |
1036 | nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001); | |
6ee73861 BS |
1037 | |
1038 | DRM_MEMORYBARRIER(); | |
1039 | #endif | |
1040 | ||
1041 | /* Time to determine the card architecture */ | |
1042 | reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); | |
1043 | ||
1044 | /* We're dealing with >=NV10 */ | |
1045 | if ((reg0 & 0x0f000000) > 0) { | |
1046 | /* Bit 27-20 contain the architecture in hex */ | |
1047 | dev_priv->chipset = (reg0 & 0xff00000) >> 20; | |
1048 | /* NV04 or NV05 */ | |
1049 | } else if ((reg0 & 0xff00fff0) == 0x20004000) { | |
1dee7a93 BS |
1050 | if (reg0 & 0x00f00000) |
1051 | dev_priv->chipset = 0x05; | |
1052 | else | |
1053 | dev_priv->chipset = 0x04; | |
6ee73861 BS |
1054 | } else |
1055 | dev_priv->chipset = 0xff; | |
1056 | ||
1057 | switch (dev_priv->chipset & 0xf0) { | |
1058 | case 0x00: | |
1059 | case 0x10: | |
1060 | case 0x20: | |
1061 | case 0x30: | |
1062 | dev_priv->card_type = dev_priv->chipset & 0xf0; | |
1063 | break; | |
1064 | case 0x40: | |
1065 | case 0x60: | |
1066 | dev_priv->card_type = NV_40; | |
1067 | break; | |
1068 | case 0x50: | |
1069 | case 0x80: | |
1070 | case 0x90: | |
1071 | case 0xa0: | |
1072 | dev_priv->card_type = NV_50; | |
1073 | break; | |
4b223eef BS |
1074 | case 0xc0: |
1075 | dev_priv->card_type = NV_C0; | |
1076 | break; | |
d9f61c2d BS |
1077 | case 0xd0: |
1078 | dev_priv->card_type = NV_D0; | |
1079 | break; | |
6ee73861 BS |
1080 | default: |
1081 | NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0); | |
a0d069ea DC |
1082 | ret = -EINVAL; |
1083 | goto err_mmio; | |
6ee73861 BS |
1084 | } |
1085 | ||
1086 | NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n", | |
1087 | dev_priv->card_type, reg0); | |
1088 | ||
f2cbe46f BS |
1089 | /* determine frequency of timing crystal */ |
1090 | strap = nv_rd32(dev, 0x101000); | |
1091 | if ( dev_priv->chipset < 0x17 || | |
1092 | (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25)) | |
1093 | strap &= 0x00000040; | |
1094 | else | |
1095 | strap &= 0x00400040; | |
1096 | ||
1097 | switch (strap) { | |
1098 | case 0x00000000: dev_priv->crystal = 13500; break; | |
1099 | case 0x00000040: dev_priv->crystal = 14318; break; | |
1100 | case 0x00400000: dev_priv->crystal = 27000; break; | |
1101 | case 0x00400040: dev_priv->crystal = 25000; break; | |
1102 | } | |
1103 | ||
1104 | NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal); | |
1105 | ||
aba99a84 BS |
1106 | /* Determine whether we'll attempt acceleration or not, some |
1107 | * cards are disabled by default here due to them being known | |
1108 | * non-functional, or never been tested due to lack of hw. | |
1109 | */ | |
1110 | dev_priv->noaccel = !!nouveau_noaccel; | |
1111 | if (nouveau_noaccel == -1) { | |
1112 | switch (dev_priv->chipset) { | |
06784090 | 1113 | case 0xd9: /* known broken */ |
ad830d23 BS |
1114 | NV_INFO(dev, "acceleration disabled by default, pass " |
1115 | "noaccel=0 to force enable\n"); | |
aba99a84 BS |
1116 | dev_priv->noaccel = true; |
1117 | break; | |
1118 | default: | |
1119 | dev_priv->noaccel = false; | |
1120 | break; | |
1121 | } | |
1122 | } | |
1123 | ||
cd0b072f BS |
1124 | ret = nouveau_remove_conflicting_drivers(dev); |
1125 | if (ret) | |
a0d069ea | 1126 | goto err_mmio; |
06415c56 | 1127 | |
25985edc | 1128 | /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */ |
6ee73861 BS |
1129 | if (dev_priv->card_type >= NV_40) { |
1130 | int ramin_bar = 2; | |
1131 | if (pci_resource_len(dev->pdev, ramin_bar) == 0) | |
1132 | ramin_bar = 3; | |
1133 | ||
1134 | dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar); | |
6d696305 BS |
1135 | dev_priv->ramin = |
1136 | ioremap(pci_resource_start(dev->pdev, ramin_bar), | |
6ee73861 BS |
1137 | dev_priv->ramin_size); |
1138 | if (!dev_priv->ramin) { | |
ff920bfb | 1139 | NV_ERROR(dev, "Failed to map PRAMIN BAR\n"); |
a0d069ea DC |
1140 | ret = -ENOMEM; |
1141 | goto err_mmio; | |
6ee73861 | 1142 | } |
6d696305 | 1143 | } else { |
6ee73861 BS |
1144 | dev_priv->ramin_size = 1 * 1024 * 1024; |
1145 | dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN, | |
6d696305 | 1146 | dev_priv->ramin_size); |
6ee73861 BS |
1147 | if (!dev_priv->ramin) { |
1148 | NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n"); | |
a0d069ea DC |
1149 | ret = -ENOMEM; |
1150 | goto err_mmio; | |
6ee73861 BS |
1151 | } |
1152 | } | |
1153 | ||
1154 | nouveau_OF_copy_vbios_to_ramin(dev); | |
1155 | ||
1156 | /* Special flags */ | |
1157 | if (dev->pci_device == 0x01a0) | |
1158 | dev_priv->flags |= NV_NFORCE; | |
1159 | else if (dev->pci_device == 0x01f0) | |
1160 | dev_priv->flags |= NV_NFORCE2; | |
1161 | ||
1162 | /* For kernel modesetting, init card now and bring up fbcon */ | |
cd0b072f BS |
1163 | ret = nouveau_card_init(dev); |
1164 | if (ret) | |
a0d069ea | 1165 | goto err_ramin; |
6ee73861 BS |
1166 | |
1167 | return 0; | |
a0d069ea DC |
1168 | |
1169 | err_ramin: | |
1170 | iounmap(dev_priv->ramin); | |
1171 | err_mmio: | |
1172 | iounmap(dev_priv->mmio); | |
a0d069ea DC |
1173 | err_priv: |
1174 | kfree(dev_priv); | |
1175 | dev->dev_private = NULL; | |
1176 | err_out: | |
1177 | return ret; | |
6ee73861 BS |
1178 | } |
1179 | ||
6ee73861 BS |
1180 | void nouveau_lastclose(struct drm_device *dev) |
1181 | { | |
5ccb377f | 1182 | vga_switcheroo_process_delayed_switch(); |
6ee73861 BS |
1183 | } |
1184 | ||
1185 | int nouveau_unload(struct drm_device *dev) | |
1186 | { | |
1187 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1188 | ||
cd0b072f | 1189 | nouveau_card_takedown(dev); |
6ee73861 BS |
1190 | |
1191 | iounmap(dev_priv->mmio); | |
1192 | iounmap(dev_priv->ramin); | |
1193 | ||
1194 | kfree(dev_priv); | |
1195 | dev->dev_private = NULL; | |
1196 | return 0; | |
1197 | } | |
1198 | ||
6ee73861 BS |
1199 | int nouveau_ioctl_getparam(struct drm_device *dev, void *data, |
1200 | struct drm_file *file_priv) | |
1201 | { | |
1202 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1203 | struct drm_nouveau_getparam *getparam = data; | |
1204 | ||
6ee73861 BS |
1205 | switch (getparam->param) { |
1206 | case NOUVEAU_GETPARAM_CHIPSET_ID: | |
1207 | getparam->value = dev_priv->chipset; | |
1208 | break; | |
1209 | case NOUVEAU_GETPARAM_PCI_VENDOR: | |
1210 | getparam->value = dev->pci_vendor; | |
1211 | break; | |
1212 | case NOUVEAU_GETPARAM_PCI_DEVICE: | |
1213 | getparam->value = dev->pci_device; | |
1214 | break; | |
1215 | case NOUVEAU_GETPARAM_BUS_TYPE: | |
8410ea3b | 1216 | if (drm_pci_device_is_agp(dev)) |
6ee73861 | 1217 | getparam->value = NV_AGP; |
58b6542b | 1218 | else if (pci_is_pcie(dev->pdev)) |
6ee73861 BS |
1219 | getparam->value = NV_PCIE; |
1220 | else | |
1221 | getparam->value = NV_PCI; | |
1222 | break; | |
6ee73861 BS |
1223 | case NOUVEAU_GETPARAM_FB_SIZE: |
1224 | getparam->value = dev_priv->fb_available_size; | |
1225 | break; | |
1226 | case NOUVEAU_GETPARAM_AGP_SIZE: | |
1227 | getparam->value = dev_priv->gart_info.aper_size; | |
1228 | break; | |
1229 | case NOUVEAU_GETPARAM_VM_VRAM_BASE: | |
6d6c5a15 | 1230 | getparam->value = 0; /* deprecated */ |
6ee73861 | 1231 | break; |
7fc74f17 MK |
1232 | case NOUVEAU_GETPARAM_PTIMER_TIME: |
1233 | getparam->value = dev_priv->engine.timer.read(dev); | |
1234 | break; | |
f13b3263 FJ |
1235 | case NOUVEAU_GETPARAM_HAS_BO_USAGE: |
1236 | getparam->value = 1; | |
1237 | break; | |
332b242f | 1238 | case NOUVEAU_GETPARAM_HAS_PAGEFLIP: |
3376ee37 | 1239 | getparam->value = 1; |
332b242f | 1240 | break; |
69c9700b MK |
1241 | case NOUVEAU_GETPARAM_GRAPH_UNITS: |
1242 | /* NV40 and NV50 versions are quite different, but register | |
1243 | * address is the same. User is supposed to know the card | |
1244 | * family anyway... */ | |
1245 | if (dev_priv->chipset >= 0x40) { | |
1246 | getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS); | |
1247 | break; | |
1248 | } | |
1249 | /* FALLTHRU */ | |
6ee73861 | 1250 | default: |
1397b42b | 1251 | NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param); |
6ee73861 BS |
1252 | return -EINVAL; |
1253 | } | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | ||
1258 | int | |
1259 | nouveau_ioctl_setparam(struct drm_device *dev, void *data, | |
1260 | struct drm_file *file_priv) | |
1261 | { | |
1262 | struct drm_nouveau_setparam *setparam = data; | |
1263 | ||
6ee73861 BS |
1264 | switch (setparam->param) { |
1265 | default: | |
1397b42b | 1266 | NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param); |
6ee73861 BS |
1267 | return -EINVAL; |
1268 | } | |
1269 | ||
1270 | return 0; | |
1271 | } | |
1272 | ||
1273 | /* Wait until (value(reg) & mask) == val, up until timeout has hit */ | |
12fb9525 BS |
1274 | bool |
1275 | nouveau_wait_eq(struct drm_device *dev, uint64_t timeout, | |
1276 | uint32_t reg, uint32_t mask, uint32_t val) | |
6ee73861 BS |
1277 | { |
1278 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1279 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1280 | uint64_t start = ptimer->read(dev); | |
1281 | ||
1282 | do { | |
1283 | if ((nv_rd32(dev, reg) & mask) == val) | |
1284 | return true; | |
1285 | } while (ptimer->read(dev) - start < timeout); | |
1286 | ||
1287 | return false; | |
1288 | } | |
1289 | ||
12fb9525 BS |
1290 | /* Wait until (value(reg) & mask) != val, up until timeout has hit */ |
1291 | bool | |
1292 | nouveau_wait_ne(struct drm_device *dev, uint64_t timeout, | |
1293 | uint32_t reg, uint32_t mask, uint32_t val) | |
1294 | { | |
1295 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1296 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1297 | uint64_t start = ptimer->read(dev); | |
1298 | ||
1299 | do { | |
1300 | if ((nv_rd32(dev, reg) & mask) != val) | |
1301 | return true; | |
1302 | } while (ptimer->read(dev) - start < timeout); | |
1303 | ||
1304 | return false; | |
1305 | } | |
1306 | ||
78e2933d BS |
1307 | /* Wait until cond(data) == true, up until timeout has hit */ |
1308 | bool | |
1309 | nouveau_wait_cb(struct drm_device *dev, u64 timeout, | |
1310 | bool (*cond)(void *), void *data) | |
1311 | { | |
1312 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1313 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1314 | u64 start = ptimer->read(dev); | |
1315 | ||
1316 | do { | |
1317 | if (cond(data) == true) | |
1318 | return true; | |
1319 | } while (ptimer->read(dev) - start < timeout); | |
1320 | ||
1321 | return false; | |
1322 | } | |
1323 | ||
6ee73861 BS |
1324 | /* Waits for PGRAPH to go completely idle */ |
1325 | bool nouveau_wait_for_idle(struct drm_device *dev) | |
1326 | { | |
0541324a FJ |
1327 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
1328 | uint32_t mask = ~0; | |
1329 | ||
1330 | if (dev_priv->card_type == NV_40) | |
1331 | mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; | |
1332 | ||
1333 | if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) { | |
6ee73861 BS |
1334 | NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n", |
1335 | nv_rd32(dev, NV04_PGRAPH_STATUS)); | |
1336 | return false; | |
1337 | } | |
1338 | ||
1339 | return true; | |
1340 | } | |
1341 |