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6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin | |
3 | * Copyright 2008 Stuart Bennett | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
21 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
22 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include <linux/swab.h> | |
5a0e3ad6 | 27 | #include <linux/slab.h> |
6ee73861 BS |
28 | #include "drmP.h" |
29 | #include "drm.h" | |
30 | #include "drm_sarea.h" | |
31 | #include "drm_crtc_helper.h" | |
32 | #include <linux/vgaarb.h> | |
6a9ee8af | 33 | #include <linux/vga_switcheroo.h> |
6ee73861 BS |
34 | |
35 | #include "nouveau_drv.h" | |
36 | #include "nouveau_drm.h" | |
38651674 | 37 | #include "nouveau_fbcon.h" |
a8eaebc6 | 38 | #include "nouveau_ramht.h" |
330c5988 | 39 | #include "nouveau_pm.h" |
6ee73861 BS |
40 | #include "nv50_display.h" |
41 | ||
6ee73861 | 42 | static void nouveau_stub_takedown(struct drm_device *dev) {} |
ee2e0131 | 43 | static int nouveau_stub_init(struct drm_device *dev) { return 0; } |
6ee73861 BS |
44 | |
45 | static int nouveau_init_engine_ptrs(struct drm_device *dev) | |
46 | { | |
47 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
48 | struct nouveau_engine *engine = &dev_priv->engine; | |
49 | ||
50 | switch (dev_priv->chipset & 0xf0) { | |
51 | case 0x00: | |
52 | engine->instmem.init = nv04_instmem_init; | |
53 | engine->instmem.takedown = nv04_instmem_takedown; | |
54 | engine->instmem.suspend = nv04_instmem_suspend; | |
55 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
56 | engine->instmem.get = nv04_instmem_get; |
57 | engine->instmem.put = nv04_instmem_put; | |
58 | engine->instmem.map = nv04_instmem_map; | |
59 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 60 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
61 | engine->mc.init = nv04_mc_init; |
62 | engine->mc.takedown = nv04_mc_takedown; | |
63 | engine->timer.init = nv04_timer_init; | |
64 | engine->timer.read = nv04_timer_read; | |
65 | engine->timer.takedown = nv04_timer_takedown; | |
66 | engine->fb.init = nv04_fb_init; | |
67 | engine->fb.takedown = nv04_fb_takedown; | |
6ee73861 BS |
68 | engine->graph.init = nv04_graph_init; |
69 | engine->graph.takedown = nv04_graph_takedown; | |
70 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
71 | engine->graph.channel = nv04_graph_channel; | |
72 | engine->graph.create_context = nv04_graph_create_context; | |
73 | engine->graph.destroy_context = nv04_graph_destroy_context; | |
74 | engine->graph.load_context = nv04_graph_load_context; | |
75 | engine->graph.unload_context = nv04_graph_unload_context; | |
76 | engine->fifo.channels = 16; | |
77 | engine->fifo.init = nv04_fifo_init; | |
5178d40d | 78 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
79 | engine->fifo.disable = nv04_fifo_disable; |
80 | engine->fifo.enable = nv04_fifo_enable; | |
81 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 82 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
83 | engine->fifo.channel_id = nv04_fifo_channel_id; |
84 | engine->fifo.create_context = nv04_fifo_create_context; | |
85 | engine->fifo.destroy_context = nv04_fifo_destroy_context; | |
86 | engine->fifo.load_context = nv04_fifo_load_context; | |
87 | engine->fifo.unload_context = nv04_fifo_unload_context; | |
c88c2e06 FJ |
88 | engine->display.early_init = nv04_display_early_init; |
89 | engine->display.late_takedown = nv04_display_late_takedown; | |
90 | engine->display.create = nv04_display_create; | |
91 | engine->display.init = nv04_display_init; | |
92 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
93 | engine->gpio.init = nouveau_stub_init; |
94 | engine->gpio.takedown = nouveau_stub_takedown; | |
95 | engine->gpio.get = NULL; | |
96 | engine->gpio.set = NULL; | |
97 | engine->gpio.irq_enable = NULL; | |
442b626e BS |
98 | engine->pm.clock_get = nv04_pm_clock_get; |
99 | engine->pm.clock_pre = nv04_pm_clock_pre; | |
100 | engine->pm.clock_set = nv04_pm_clock_set; | |
bd2e597d BS |
101 | engine->crypt.init = nouveau_stub_init; |
102 | engine->crypt.takedown = nouveau_stub_takedown; | |
60d2a88a BS |
103 | engine->vram.init = nouveau_mem_detect; |
104 | engine->vram.flags_valid = nouveau_mem_flags_valid; | |
6ee73861 BS |
105 | break; |
106 | case 0x10: | |
107 | engine->instmem.init = nv04_instmem_init; | |
108 | engine->instmem.takedown = nv04_instmem_takedown; | |
109 | engine->instmem.suspend = nv04_instmem_suspend; | |
110 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
111 | engine->instmem.get = nv04_instmem_get; |
112 | engine->instmem.put = nv04_instmem_put; | |
113 | engine->instmem.map = nv04_instmem_map; | |
114 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 115 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
116 | engine->mc.init = nv04_mc_init; |
117 | engine->mc.takedown = nv04_mc_takedown; | |
118 | engine->timer.init = nv04_timer_init; | |
119 | engine->timer.read = nv04_timer_read; | |
120 | engine->timer.takedown = nv04_timer_takedown; | |
121 | engine->fb.init = nv10_fb_init; | |
122 | engine->fb.takedown = nv10_fb_takedown; | |
a5cf68b0 FJ |
123 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
124 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
125 | engine->fb.free_tile_region = nv10_fb_free_tile_region; | |
6ee73861 BS |
126 | engine->graph.init = nv10_graph_init; |
127 | engine->graph.takedown = nv10_graph_takedown; | |
128 | engine->graph.channel = nv10_graph_channel; | |
129 | engine->graph.create_context = nv10_graph_create_context; | |
130 | engine->graph.destroy_context = nv10_graph_destroy_context; | |
131 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
132 | engine->graph.load_context = nv10_graph_load_context; | |
133 | engine->graph.unload_context = nv10_graph_unload_context; | |
a5cf68b0 | 134 | engine->graph.set_tile_region = nv10_graph_set_tile_region; |
6ee73861 BS |
135 | engine->fifo.channels = 32; |
136 | engine->fifo.init = nv10_fifo_init; | |
5178d40d | 137 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
138 | engine->fifo.disable = nv04_fifo_disable; |
139 | engine->fifo.enable = nv04_fifo_enable; | |
140 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 141 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
142 | engine->fifo.channel_id = nv10_fifo_channel_id; |
143 | engine->fifo.create_context = nv10_fifo_create_context; | |
3945e475 | 144 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
6ee73861 BS |
145 | engine->fifo.load_context = nv10_fifo_load_context; |
146 | engine->fifo.unload_context = nv10_fifo_unload_context; | |
c88c2e06 FJ |
147 | engine->display.early_init = nv04_display_early_init; |
148 | engine->display.late_takedown = nv04_display_late_takedown; | |
149 | engine->display.create = nv04_display_create; | |
150 | engine->display.init = nv04_display_init; | |
151 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
152 | engine->gpio.init = nouveau_stub_init; |
153 | engine->gpio.takedown = nouveau_stub_takedown; | |
154 | engine->gpio.get = nv10_gpio_get; | |
155 | engine->gpio.set = nv10_gpio_set; | |
156 | engine->gpio.irq_enable = NULL; | |
442b626e BS |
157 | engine->pm.clock_get = nv04_pm_clock_get; |
158 | engine->pm.clock_pre = nv04_pm_clock_pre; | |
159 | engine->pm.clock_set = nv04_pm_clock_set; | |
bd2e597d BS |
160 | engine->crypt.init = nouveau_stub_init; |
161 | engine->crypt.takedown = nouveau_stub_takedown; | |
60d2a88a BS |
162 | engine->vram.init = nouveau_mem_detect; |
163 | engine->vram.flags_valid = nouveau_mem_flags_valid; | |
6ee73861 BS |
164 | break; |
165 | case 0x20: | |
166 | engine->instmem.init = nv04_instmem_init; | |
167 | engine->instmem.takedown = nv04_instmem_takedown; | |
168 | engine->instmem.suspend = nv04_instmem_suspend; | |
169 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
170 | engine->instmem.get = nv04_instmem_get; |
171 | engine->instmem.put = nv04_instmem_put; | |
172 | engine->instmem.map = nv04_instmem_map; | |
173 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 174 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
175 | engine->mc.init = nv04_mc_init; |
176 | engine->mc.takedown = nv04_mc_takedown; | |
177 | engine->timer.init = nv04_timer_init; | |
178 | engine->timer.read = nv04_timer_read; | |
179 | engine->timer.takedown = nv04_timer_takedown; | |
180 | engine->fb.init = nv10_fb_init; | |
181 | engine->fb.takedown = nv10_fb_takedown; | |
a5cf68b0 FJ |
182 | engine->fb.init_tile_region = nv10_fb_init_tile_region; |
183 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
184 | engine->fb.free_tile_region = nv10_fb_free_tile_region; | |
6ee73861 BS |
185 | engine->graph.init = nv20_graph_init; |
186 | engine->graph.takedown = nv20_graph_takedown; | |
187 | engine->graph.channel = nv10_graph_channel; | |
188 | engine->graph.create_context = nv20_graph_create_context; | |
189 | engine->graph.destroy_context = nv20_graph_destroy_context; | |
190 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
191 | engine->graph.load_context = nv20_graph_load_context; | |
192 | engine->graph.unload_context = nv20_graph_unload_context; | |
a5cf68b0 | 193 | engine->graph.set_tile_region = nv20_graph_set_tile_region; |
6ee73861 BS |
194 | engine->fifo.channels = 32; |
195 | engine->fifo.init = nv10_fifo_init; | |
5178d40d | 196 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
197 | engine->fifo.disable = nv04_fifo_disable; |
198 | engine->fifo.enable = nv04_fifo_enable; | |
199 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 200 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
201 | engine->fifo.channel_id = nv10_fifo_channel_id; |
202 | engine->fifo.create_context = nv10_fifo_create_context; | |
3945e475 | 203 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
6ee73861 BS |
204 | engine->fifo.load_context = nv10_fifo_load_context; |
205 | engine->fifo.unload_context = nv10_fifo_unload_context; | |
c88c2e06 FJ |
206 | engine->display.early_init = nv04_display_early_init; |
207 | engine->display.late_takedown = nv04_display_late_takedown; | |
208 | engine->display.create = nv04_display_create; | |
209 | engine->display.init = nv04_display_init; | |
210 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
211 | engine->gpio.init = nouveau_stub_init; |
212 | engine->gpio.takedown = nouveau_stub_takedown; | |
213 | engine->gpio.get = nv10_gpio_get; | |
214 | engine->gpio.set = nv10_gpio_set; | |
215 | engine->gpio.irq_enable = NULL; | |
442b626e BS |
216 | engine->pm.clock_get = nv04_pm_clock_get; |
217 | engine->pm.clock_pre = nv04_pm_clock_pre; | |
218 | engine->pm.clock_set = nv04_pm_clock_set; | |
bd2e597d BS |
219 | engine->crypt.init = nouveau_stub_init; |
220 | engine->crypt.takedown = nouveau_stub_takedown; | |
60d2a88a BS |
221 | engine->vram.init = nouveau_mem_detect; |
222 | engine->vram.flags_valid = nouveau_mem_flags_valid; | |
6ee73861 BS |
223 | break; |
224 | case 0x30: | |
225 | engine->instmem.init = nv04_instmem_init; | |
226 | engine->instmem.takedown = nv04_instmem_takedown; | |
227 | engine->instmem.suspend = nv04_instmem_suspend; | |
228 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
229 | engine->instmem.get = nv04_instmem_get; |
230 | engine->instmem.put = nv04_instmem_put; | |
231 | engine->instmem.map = nv04_instmem_map; | |
232 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 233 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
234 | engine->mc.init = nv04_mc_init; |
235 | engine->mc.takedown = nv04_mc_takedown; | |
236 | engine->timer.init = nv04_timer_init; | |
237 | engine->timer.read = nv04_timer_read; | |
238 | engine->timer.takedown = nv04_timer_takedown; | |
8bded189 FJ |
239 | engine->fb.init = nv30_fb_init; |
240 | engine->fb.takedown = nv30_fb_takedown; | |
a5cf68b0 FJ |
241 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
242 | engine->fb.set_tile_region = nv10_fb_set_tile_region; | |
243 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | |
6ee73861 BS |
244 | engine->graph.init = nv30_graph_init; |
245 | engine->graph.takedown = nv20_graph_takedown; | |
246 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
247 | engine->graph.channel = nv10_graph_channel; | |
248 | engine->graph.create_context = nv20_graph_create_context; | |
249 | engine->graph.destroy_context = nv20_graph_destroy_context; | |
250 | engine->graph.load_context = nv20_graph_load_context; | |
251 | engine->graph.unload_context = nv20_graph_unload_context; | |
a5cf68b0 | 252 | engine->graph.set_tile_region = nv20_graph_set_tile_region; |
6ee73861 BS |
253 | engine->fifo.channels = 32; |
254 | engine->fifo.init = nv10_fifo_init; | |
5178d40d | 255 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
256 | engine->fifo.disable = nv04_fifo_disable; |
257 | engine->fifo.enable = nv04_fifo_enable; | |
258 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 259 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
260 | engine->fifo.channel_id = nv10_fifo_channel_id; |
261 | engine->fifo.create_context = nv10_fifo_create_context; | |
3945e475 | 262 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
6ee73861 BS |
263 | engine->fifo.load_context = nv10_fifo_load_context; |
264 | engine->fifo.unload_context = nv10_fifo_unload_context; | |
c88c2e06 FJ |
265 | engine->display.early_init = nv04_display_early_init; |
266 | engine->display.late_takedown = nv04_display_late_takedown; | |
267 | engine->display.create = nv04_display_create; | |
268 | engine->display.init = nv04_display_init; | |
269 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
270 | engine->gpio.init = nouveau_stub_init; |
271 | engine->gpio.takedown = nouveau_stub_takedown; | |
272 | engine->gpio.get = nv10_gpio_get; | |
273 | engine->gpio.set = nv10_gpio_set; | |
274 | engine->gpio.irq_enable = NULL; | |
442b626e BS |
275 | engine->pm.clock_get = nv04_pm_clock_get; |
276 | engine->pm.clock_pre = nv04_pm_clock_pre; | |
277 | engine->pm.clock_set = nv04_pm_clock_set; | |
278 | engine->pm.voltage_get = nouveau_voltage_gpio_get; | |
279 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
bd2e597d BS |
280 | engine->crypt.init = nouveau_stub_init; |
281 | engine->crypt.takedown = nouveau_stub_takedown; | |
60d2a88a BS |
282 | engine->vram.init = nouveau_mem_detect; |
283 | engine->vram.flags_valid = nouveau_mem_flags_valid; | |
6ee73861 BS |
284 | break; |
285 | case 0x40: | |
286 | case 0x60: | |
287 | engine->instmem.init = nv04_instmem_init; | |
288 | engine->instmem.takedown = nv04_instmem_takedown; | |
289 | engine->instmem.suspend = nv04_instmem_suspend; | |
290 | engine->instmem.resume = nv04_instmem_resume; | |
e41115d0 BS |
291 | engine->instmem.get = nv04_instmem_get; |
292 | engine->instmem.put = nv04_instmem_put; | |
293 | engine->instmem.map = nv04_instmem_map; | |
294 | engine->instmem.unmap = nv04_instmem_unmap; | |
f56cb86f | 295 | engine->instmem.flush = nv04_instmem_flush; |
6ee73861 BS |
296 | engine->mc.init = nv40_mc_init; |
297 | engine->mc.takedown = nv40_mc_takedown; | |
298 | engine->timer.init = nv04_timer_init; | |
299 | engine->timer.read = nv04_timer_read; | |
300 | engine->timer.takedown = nv04_timer_takedown; | |
301 | engine->fb.init = nv40_fb_init; | |
302 | engine->fb.takedown = nv40_fb_takedown; | |
a5cf68b0 FJ |
303 | engine->fb.init_tile_region = nv30_fb_init_tile_region; |
304 | engine->fb.set_tile_region = nv40_fb_set_tile_region; | |
305 | engine->fb.free_tile_region = nv30_fb_free_tile_region; | |
6ee73861 BS |
306 | engine->graph.init = nv40_graph_init; |
307 | engine->graph.takedown = nv40_graph_takedown; | |
308 | engine->graph.fifo_access = nv04_graph_fifo_access; | |
309 | engine->graph.channel = nv40_graph_channel; | |
310 | engine->graph.create_context = nv40_graph_create_context; | |
311 | engine->graph.destroy_context = nv40_graph_destroy_context; | |
312 | engine->graph.load_context = nv40_graph_load_context; | |
313 | engine->graph.unload_context = nv40_graph_unload_context; | |
a5cf68b0 | 314 | engine->graph.set_tile_region = nv40_graph_set_tile_region; |
6ee73861 BS |
315 | engine->fifo.channels = 32; |
316 | engine->fifo.init = nv40_fifo_init; | |
5178d40d | 317 | engine->fifo.takedown = nv04_fifo_fini; |
6ee73861 BS |
318 | engine->fifo.disable = nv04_fifo_disable; |
319 | engine->fifo.enable = nv04_fifo_enable; | |
320 | engine->fifo.reassign = nv04_fifo_reassign; | |
588d7d12 | 321 | engine->fifo.cache_pull = nv04_fifo_cache_pull; |
6ee73861 BS |
322 | engine->fifo.channel_id = nv10_fifo_channel_id; |
323 | engine->fifo.create_context = nv40_fifo_create_context; | |
3945e475 | 324 | engine->fifo.destroy_context = nv04_fifo_destroy_context; |
6ee73861 BS |
325 | engine->fifo.load_context = nv40_fifo_load_context; |
326 | engine->fifo.unload_context = nv40_fifo_unload_context; | |
c88c2e06 FJ |
327 | engine->display.early_init = nv04_display_early_init; |
328 | engine->display.late_takedown = nv04_display_late_takedown; | |
329 | engine->display.create = nv04_display_create; | |
330 | engine->display.init = nv04_display_init; | |
331 | engine->display.destroy = nv04_display_destroy; | |
ee2e0131 BS |
332 | engine->gpio.init = nouveau_stub_init; |
333 | engine->gpio.takedown = nouveau_stub_takedown; | |
334 | engine->gpio.get = nv10_gpio_get; | |
335 | engine->gpio.set = nv10_gpio_set; | |
336 | engine->gpio.irq_enable = NULL; | |
442b626e BS |
337 | engine->pm.clock_get = nv04_pm_clock_get; |
338 | engine->pm.clock_pre = nv04_pm_clock_pre; | |
339 | engine->pm.clock_set = nv04_pm_clock_set; | |
340 | engine->pm.voltage_get = nouveau_voltage_gpio_get; | |
341 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 | 342 | engine->pm.temp_get = nv40_temp_get; |
bd2e597d BS |
343 | engine->crypt.init = nouveau_stub_init; |
344 | engine->crypt.takedown = nouveau_stub_takedown; | |
60d2a88a BS |
345 | engine->vram.init = nouveau_mem_detect; |
346 | engine->vram.flags_valid = nouveau_mem_flags_valid; | |
6ee73861 BS |
347 | break; |
348 | case 0x50: | |
349 | case 0x80: /* gotta love NVIDIA's consistency.. */ | |
350 | case 0x90: | |
351 | case 0xA0: | |
352 | engine->instmem.init = nv50_instmem_init; | |
353 | engine->instmem.takedown = nv50_instmem_takedown; | |
354 | engine->instmem.suspend = nv50_instmem_suspend; | |
355 | engine->instmem.resume = nv50_instmem_resume; | |
e41115d0 BS |
356 | engine->instmem.get = nv50_instmem_get; |
357 | engine->instmem.put = nv50_instmem_put; | |
358 | engine->instmem.map = nv50_instmem_map; | |
359 | engine->instmem.unmap = nv50_instmem_unmap; | |
734ee835 BS |
360 | if (dev_priv->chipset == 0x50) |
361 | engine->instmem.flush = nv50_instmem_flush; | |
362 | else | |
363 | engine->instmem.flush = nv84_instmem_flush; | |
6ee73861 BS |
364 | engine->mc.init = nv50_mc_init; |
365 | engine->mc.takedown = nv50_mc_takedown; | |
366 | engine->timer.init = nv04_timer_init; | |
367 | engine->timer.read = nv04_timer_read; | |
368 | engine->timer.takedown = nv04_timer_takedown; | |
304424e1 MK |
369 | engine->fb.init = nv50_fb_init; |
370 | engine->fb.takedown = nv50_fb_takedown; | |
6ee73861 BS |
371 | engine->graph.init = nv50_graph_init; |
372 | engine->graph.takedown = nv50_graph_takedown; | |
373 | engine->graph.fifo_access = nv50_graph_fifo_access; | |
374 | engine->graph.channel = nv50_graph_channel; | |
375 | engine->graph.create_context = nv50_graph_create_context; | |
376 | engine->graph.destroy_context = nv50_graph_destroy_context; | |
377 | engine->graph.load_context = nv50_graph_load_context; | |
378 | engine->graph.unload_context = nv50_graph_unload_context; | |
56ac7475 BS |
379 | if (dev_priv->chipset != 0x86) |
380 | engine->graph.tlb_flush = nv50_graph_tlb_flush; | |
381 | else { | |
382 | /* from what i can see nvidia do this on every | |
383 | * pre-NVA3 board except NVAC, but, we've only | |
384 | * ever seen problems on NV86 | |
385 | */ | |
386 | engine->graph.tlb_flush = nv86_graph_tlb_flush; | |
387 | } | |
6ee73861 BS |
388 | engine->fifo.channels = 128; |
389 | engine->fifo.init = nv50_fifo_init; | |
390 | engine->fifo.takedown = nv50_fifo_takedown; | |
391 | engine->fifo.disable = nv04_fifo_disable; | |
392 | engine->fifo.enable = nv04_fifo_enable; | |
393 | engine->fifo.reassign = nv04_fifo_reassign; | |
394 | engine->fifo.channel_id = nv50_fifo_channel_id; | |
395 | engine->fifo.create_context = nv50_fifo_create_context; | |
396 | engine->fifo.destroy_context = nv50_fifo_destroy_context; | |
397 | engine->fifo.load_context = nv50_fifo_load_context; | |
398 | engine->fifo.unload_context = nv50_fifo_unload_context; | |
56ac7475 | 399 | engine->fifo.tlb_flush = nv50_fifo_tlb_flush; |
c88c2e06 FJ |
400 | engine->display.early_init = nv50_display_early_init; |
401 | engine->display.late_takedown = nv50_display_late_takedown; | |
402 | engine->display.create = nv50_display_create; | |
403 | engine->display.init = nv50_display_init; | |
404 | engine->display.destroy = nv50_display_destroy; | |
ee2e0131 | 405 | engine->gpio.init = nv50_gpio_init; |
2cbd4c81 | 406 | engine->gpio.takedown = nv50_gpio_fini; |
ee2e0131 BS |
407 | engine->gpio.get = nv50_gpio_get; |
408 | engine->gpio.set = nv50_gpio_set; | |
fce2bad0 BS |
409 | engine->gpio.irq_register = nv50_gpio_irq_register; |
410 | engine->gpio.irq_unregister = nv50_gpio_irq_unregister; | |
ee2e0131 | 411 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
fade7ad5 | 412 | switch (dev_priv->chipset) { |
bd2e597d BS |
413 | case 0x84: |
414 | case 0x86: | |
415 | case 0x92: | |
416 | case 0x94: | |
417 | case 0x96: | |
418 | case 0x98: | |
419 | case 0xa0: | |
5f80198e BS |
420 | case 0xaa: |
421 | case 0xac: | |
bd2e597d | 422 | case 0x50: |
fade7ad5 BS |
423 | engine->pm.clock_get = nv50_pm_clock_get; |
424 | engine->pm.clock_pre = nv50_pm_clock_pre; | |
425 | engine->pm.clock_set = nv50_pm_clock_set; | |
426 | break; | |
bd2e597d BS |
427 | default: |
428 | engine->pm.clock_get = nva3_pm_clock_get; | |
429 | engine->pm.clock_pre = nva3_pm_clock_pre; | |
430 | engine->pm.clock_set = nva3_pm_clock_set; | |
431 | break; | |
fade7ad5 | 432 | } |
02c30ca0 BS |
433 | engine->pm.voltage_get = nouveau_voltage_gpio_get; |
434 | engine->pm.voltage_set = nouveau_voltage_gpio_set; | |
8155cac4 FJ |
435 | if (dev_priv->chipset >= 0x84) |
436 | engine->pm.temp_get = nv84_temp_get; | |
437 | else | |
438 | engine->pm.temp_get = nv40_temp_get; | |
bd2e597d BS |
439 | switch (dev_priv->chipset) { |
440 | case 0x84: | |
441 | case 0x86: | |
442 | case 0x92: | |
443 | case 0x94: | |
444 | case 0x96: | |
445 | case 0xa0: | |
446 | engine->crypt.init = nv84_crypt_init; | |
447 | engine->crypt.takedown = nv84_crypt_fini; | |
448 | engine->crypt.create_context = nv84_crypt_create_context; | |
449 | engine->crypt.destroy_context = nv84_crypt_destroy_context; | |
2cb3d3b6 | 450 | engine->crypt.tlb_flush = nv84_crypt_tlb_flush; |
bd2e597d BS |
451 | break; |
452 | default: | |
453 | engine->crypt.init = nouveau_stub_init; | |
454 | engine->crypt.takedown = nouveau_stub_takedown; | |
455 | break; | |
456 | } | |
60d2a88a BS |
457 | engine->vram.init = nv50_vram_init; |
458 | engine->vram.get = nv50_vram_new; | |
459 | engine->vram.put = nv50_vram_del; | |
460 | engine->vram.flags_valid = nv50_vram_flags_valid; | |
6ee73861 | 461 | break; |
4b223eef BS |
462 | case 0xC0: |
463 | engine->instmem.init = nvc0_instmem_init; | |
464 | engine->instmem.takedown = nvc0_instmem_takedown; | |
465 | engine->instmem.suspend = nvc0_instmem_suspend; | |
466 | engine->instmem.resume = nvc0_instmem_resume; | |
8984e046 BS |
467 | engine->instmem.get = nv50_instmem_get; |
468 | engine->instmem.put = nv50_instmem_put; | |
469 | engine->instmem.map = nv50_instmem_map; | |
470 | engine->instmem.unmap = nv50_instmem_unmap; | |
471 | engine->instmem.flush = nv84_instmem_flush; | |
4b223eef BS |
472 | engine->mc.init = nv50_mc_init; |
473 | engine->mc.takedown = nv50_mc_takedown; | |
474 | engine->timer.init = nv04_timer_init; | |
475 | engine->timer.read = nv04_timer_read; | |
476 | engine->timer.takedown = nv04_timer_takedown; | |
477 | engine->fb.init = nvc0_fb_init; | |
478 | engine->fb.takedown = nvc0_fb_takedown; | |
4b223eef BS |
479 | engine->graph.init = nvc0_graph_init; |
480 | engine->graph.takedown = nvc0_graph_takedown; | |
481 | engine->graph.fifo_access = nvc0_graph_fifo_access; | |
482 | engine->graph.channel = nvc0_graph_channel; | |
483 | engine->graph.create_context = nvc0_graph_create_context; | |
484 | engine->graph.destroy_context = nvc0_graph_destroy_context; | |
485 | engine->graph.load_context = nvc0_graph_load_context; | |
486 | engine->graph.unload_context = nvc0_graph_unload_context; | |
487 | engine->fifo.channels = 128; | |
488 | engine->fifo.init = nvc0_fifo_init; | |
489 | engine->fifo.takedown = nvc0_fifo_takedown; | |
490 | engine->fifo.disable = nvc0_fifo_disable; | |
491 | engine->fifo.enable = nvc0_fifo_enable; | |
492 | engine->fifo.reassign = nvc0_fifo_reassign; | |
493 | engine->fifo.channel_id = nvc0_fifo_channel_id; | |
494 | engine->fifo.create_context = nvc0_fifo_create_context; | |
495 | engine->fifo.destroy_context = nvc0_fifo_destroy_context; | |
496 | engine->fifo.load_context = nvc0_fifo_load_context; | |
497 | engine->fifo.unload_context = nvc0_fifo_unload_context; | |
498 | engine->display.early_init = nv50_display_early_init; | |
499 | engine->display.late_takedown = nv50_display_late_takedown; | |
500 | engine->display.create = nv50_display_create; | |
501 | engine->display.init = nv50_display_init; | |
502 | engine->display.destroy = nv50_display_destroy; | |
503 | engine->gpio.init = nv50_gpio_init; | |
504 | engine->gpio.takedown = nouveau_stub_takedown; | |
505 | engine->gpio.get = nv50_gpio_get; | |
506 | engine->gpio.set = nv50_gpio_set; | |
fce2bad0 BS |
507 | engine->gpio.irq_register = nv50_gpio_irq_register; |
508 | engine->gpio.irq_unregister = nv50_gpio_irq_unregister; | |
4b223eef | 509 | engine->gpio.irq_enable = nv50_gpio_irq_enable; |
bd2e597d BS |
510 | engine->crypt.init = nouveau_stub_init; |
511 | engine->crypt.takedown = nouveau_stub_takedown; | |
8984e046 BS |
512 | engine->vram.init = nvc0_vram_init; |
513 | engine->vram.get = nvc0_vram_new; | |
514 | engine->vram.put = nv50_vram_del; | |
515 | engine->vram.flags_valid = nvc0_vram_flags_valid; | |
4b223eef | 516 | break; |
6ee73861 BS |
517 | default: |
518 | NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset); | |
519 | return 1; | |
520 | } | |
521 | ||
522 | return 0; | |
523 | } | |
524 | ||
525 | static unsigned int | |
526 | nouveau_vga_set_decode(void *priv, bool state) | |
527 | { | |
9967b948 MK |
528 | struct drm_device *dev = priv; |
529 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
530 | ||
531 | if (dev_priv->chipset >= 0x40) | |
532 | nv_wr32(dev, 0x88054, state); | |
533 | else | |
534 | nv_wr32(dev, 0x1854, state); | |
535 | ||
6ee73861 BS |
536 | if (state) |
537 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | | |
538 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
539 | else | |
540 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; | |
541 | } | |
542 | ||
0735f62e BS |
543 | static int |
544 | nouveau_card_init_channel(struct drm_device *dev) | |
545 | { | |
546 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
a8eaebc6 | 547 | struct nouveau_gpuobj *gpuobj = NULL; |
0735f62e BS |
548 | int ret; |
549 | ||
550 | ret = nouveau_channel_alloc(dev, &dev_priv->channel, | |
a8eaebc6 | 551 | (struct drm_file *)-2, NvDmaFB, NvDmaTT); |
0735f62e BS |
552 | if (ret) |
553 | return ret; | |
554 | ||
5216782b BS |
555 | /* no dma objects on fermi... */ |
556 | if (dev_priv->card_type >= NV_C0) | |
557 | goto out_done; | |
558 | ||
0735f62e | 559 | ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY, |
a76fb4e8 | 560 | 0, dev_priv->vram_size, |
7f4a195f | 561 | NV_MEM_ACCESS_RW, NV_MEM_TARGET_VRAM, |
0735f62e BS |
562 | &gpuobj); |
563 | if (ret) | |
564 | goto out_err; | |
565 | ||
a8eaebc6 BS |
566 | ret = nouveau_ramht_insert(dev_priv->channel, NvDmaVRAM, gpuobj); |
567 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
0735f62e BS |
568 | if (ret) |
569 | goto out_err; | |
570 | ||
7f4a195f BS |
571 | ret = nouveau_gpuobj_dma_new(dev_priv->channel, NV_CLASS_DMA_IN_MEMORY, |
572 | 0, dev_priv->gart_info.aper_size, | |
573 | NV_MEM_ACCESS_RW, NV_MEM_TARGET_GART, | |
574 | &gpuobj); | |
0735f62e BS |
575 | if (ret) |
576 | goto out_err; | |
577 | ||
a8eaebc6 BS |
578 | ret = nouveau_ramht_insert(dev_priv->channel, NvDmaGART, gpuobj); |
579 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
0735f62e BS |
580 | if (ret) |
581 | goto out_err; | |
582 | ||
5216782b | 583 | out_done: |
cff5c133 | 584 | mutex_unlock(&dev_priv->channel->mutex); |
0735f62e | 585 | return 0; |
a8eaebc6 | 586 | |
0735f62e | 587 | out_err: |
cff5c133 | 588 | nouveau_channel_put(&dev_priv->channel); |
0735f62e BS |
589 | return ret; |
590 | } | |
591 | ||
6a9ee8af DA |
592 | static void nouveau_switcheroo_set_state(struct pci_dev *pdev, |
593 | enum vga_switcheroo_state state) | |
594 | { | |
fbf81762 | 595 | struct drm_device *dev = pci_get_drvdata(pdev); |
6a9ee8af DA |
596 | pm_message_t pmm = { .event = PM_EVENT_SUSPEND }; |
597 | if (state == VGA_SWITCHEROO_ON) { | |
598 | printk(KERN_ERR "VGA switcheroo: switched nouveau on\n"); | |
5bcf719b | 599 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
6a9ee8af | 600 | nouveau_pci_resume(pdev); |
fbf81762 | 601 | drm_kms_helper_poll_enable(dev); |
5bcf719b | 602 | dev->switch_power_state = DRM_SWITCH_POWER_ON; |
6a9ee8af DA |
603 | } else { |
604 | printk(KERN_ERR "VGA switcheroo: switched nouveau off\n"); | |
5bcf719b | 605 | dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; |
fbf81762 | 606 | drm_kms_helper_poll_disable(dev); |
6a9ee8af | 607 | nouveau_pci_suspend(pdev, pmm); |
5bcf719b | 608 | dev->switch_power_state = DRM_SWITCH_POWER_OFF; |
6a9ee8af DA |
609 | } |
610 | } | |
611 | ||
8d608aa6 DA |
612 | static void nouveau_switcheroo_reprobe(struct pci_dev *pdev) |
613 | { | |
614 | struct drm_device *dev = pci_get_drvdata(pdev); | |
615 | nouveau_fbcon_output_poll_changed(dev); | |
616 | } | |
617 | ||
6a9ee8af DA |
618 | static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev) |
619 | { | |
620 | struct drm_device *dev = pci_get_drvdata(pdev); | |
621 | bool can_switch; | |
622 | ||
623 | spin_lock(&dev->count_lock); | |
624 | can_switch = (dev->open_count == 0); | |
625 | spin_unlock(&dev->count_lock); | |
626 | return can_switch; | |
627 | } | |
628 | ||
6ee73861 BS |
629 | int |
630 | nouveau_card_init(struct drm_device *dev) | |
631 | { | |
632 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
633 | struct nouveau_engine *engine; | |
6ee73861 BS |
634 | int ret; |
635 | ||
6ee73861 | 636 | vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode); |
6a9ee8af | 637 | vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state, |
8d608aa6 | 638 | nouveau_switcheroo_reprobe, |
6a9ee8af | 639 | nouveau_switcheroo_can_switch); |
6ee73861 BS |
640 | |
641 | /* Initialise internal driver API hooks */ | |
642 | ret = nouveau_init_engine_ptrs(dev); | |
643 | if (ret) | |
c5804be0 | 644 | goto out; |
6ee73861 | 645 | engine = &dev_priv->engine; |
cff5c133 | 646 | spin_lock_init(&dev_priv->channels.lock); |
a5cf68b0 | 647 | spin_lock_init(&dev_priv->tile.lock); |
ff9e5279 | 648 | spin_lock_init(&dev_priv->context_switch_lock); |
6ee73861 | 649 | |
c88c2e06 FJ |
650 | /* Make the CRTCs and I2C buses accessible */ |
651 | ret = engine->display.early_init(dev); | |
652 | if (ret) | |
653 | goto out; | |
654 | ||
6ee73861 | 655 | /* Parse BIOS tables / Run init tables if card not POSTed */ |
cd0b072f BS |
656 | ret = nouveau_bios_init(dev); |
657 | if (ret) | |
c88c2e06 | 658 | goto out_display_early; |
6ee73861 | 659 | |
330c5988 BS |
660 | nouveau_pm_init(dev); |
661 | ||
fbd2895e | 662 | ret = nouveau_mem_vram_init(dev); |
a76fb4e8 BS |
663 | if (ret) |
664 | goto out_bios; | |
665 | ||
fbd2895e | 666 | ret = nouveau_gpuobj_init(dev); |
6ee73861 | 667 | if (ret) |
fbd2895e | 668 | goto out_vram; |
6ee73861 | 669 | |
6ee73861 BS |
670 | ret = engine->instmem.init(dev); |
671 | if (ret) | |
fbd2895e | 672 | goto out_gpuobj; |
6ee73861 | 673 | |
fbd2895e | 674 | ret = nouveau_mem_gart_init(dev); |
6ee73861 | 675 | if (ret) |
c5804be0 | 676 | goto out_instmem; |
6ee73861 | 677 | |
6ee73861 BS |
678 | /* PMC */ |
679 | ret = engine->mc.init(dev); | |
680 | if (ret) | |
fbd2895e | 681 | goto out_gart; |
6ee73861 | 682 | |
ee2e0131 BS |
683 | /* PGPIO */ |
684 | ret = engine->gpio.init(dev); | |
685 | if (ret) | |
686 | goto out_mc; | |
687 | ||
6ee73861 BS |
688 | /* PTIMER */ |
689 | ret = engine->timer.init(dev); | |
690 | if (ret) | |
ee2e0131 | 691 | goto out_gpio; |
6ee73861 BS |
692 | |
693 | /* PFB */ | |
694 | ret = engine->fb.init(dev); | |
695 | if (ret) | |
c5804be0 | 696 | goto out_timer; |
6ee73861 | 697 | |
a32ed69d MK |
698 | if (nouveau_noaccel) |
699 | engine->graph.accel_blocked = true; | |
700 | else { | |
701 | /* PGRAPH */ | |
702 | ret = engine->graph.init(dev); | |
703 | if (ret) | |
704 | goto out_fb; | |
6ee73861 | 705 | |
bd2e597d BS |
706 | /* PCRYPT */ |
707 | ret = engine->crypt.init(dev); | |
708 | if (ret) | |
709 | goto out_graph; | |
710 | ||
a32ed69d MK |
711 | /* PFIFO */ |
712 | ret = engine->fifo.init(dev); | |
713 | if (ret) | |
bd2e597d | 714 | goto out_crypt; |
a32ed69d | 715 | } |
6ee73861 | 716 | |
c88c2e06 | 717 | ret = engine->display.create(dev); |
e88efe05 BS |
718 | if (ret) |
719 | goto out_fifo; | |
720 | ||
042206c0 | 721 | ret = drm_vblank_init(dev, nv_two_heads(dev) ? 2 : 1); |
6ee73861 | 722 | if (ret) |
042206c0 | 723 | goto out_vblank; |
6ee73861 | 724 | |
042206c0 | 725 | ret = nouveau_irq_init(dev); |
6ee73861 | 726 | if (ret) |
042206c0 | 727 | goto out_vblank; |
6ee73861 BS |
728 | |
729 | /* what about PVIDEO/PCRTC/PRAMDAC etc? */ | |
730 | ||
0735f62e | 731 | if (!engine->graph.accel_blocked) { |
0c6c1c2f | 732 | ret = nouveau_fence_init(dev); |
0735f62e BS |
733 | if (ret) |
734 | goto out_irq; | |
0c6c1c2f FJ |
735 | |
736 | ret = nouveau_card_init_channel(dev); | |
737 | if (ret) | |
738 | goto out_fence; | |
6ee73861 BS |
739 | } |
740 | ||
6ee73861 BS |
741 | ret = nouveau_backlight_init(dev); |
742 | if (ret) | |
743 | NV_ERROR(dev, "Error %d registering backlight\n", ret); | |
744 | ||
cd0b072f BS |
745 | nouveau_fbcon_init(dev); |
746 | drm_kms_helper_poll_init(dev); | |
6ee73861 | 747 | return 0; |
c5804be0 | 748 | |
0c6c1c2f FJ |
749 | out_fence: |
750 | nouveau_fence_fini(dev); | |
c5804be0 | 751 | out_irq: |
35fa2f2a | 752 | nouveau_irq_fini(dev); |
042206c0 FJ |
753 | out_vblank: |
754 | drm_vblank_cleanup(dev); | |
c88c2e06 | 755 | engine->display.destroy(dev); |
c5804be0 | 756 | out_fifo: |
a32ed69d MK |
757 | if (!nouveau_noaccel) |
758 | engine->fifo.takedown(dev); | |
bd2e597d BS |
759 | out_crypt: |
760 | if (!nouveau_noaccel) | |
761 | engine->crypt.takedown(dev); | |
c5804be0 | 762 | out_graph: |
a32ed69d MK |
763 | if (!nouveau_noaccel) |
764 | engine->graph.takedown(dev); | |
c5804be0 MK |
765 | out_fb: |
766 | engine->fb.takedown(dev); | |
767 | out_timer: | |
768 | engine->timer.takedown(dev); | |
ee2e0131 BS |
769 | out_gpio: |
770 | engine->gpio.takedown(dev); | |
c5804be0 MK |
771 | out_mc: |
772 | engine->mc.takedown(dev); | |
fbd2895e BS |
773 | out_gart: |
774 | nouveau_mem_gart_fini(dev); | |
c5804be0 MK |
775 | out_instmem: |
776 | engine->instmem.takedown(dev); | |
fbd2895e BS |
777 | out_gpuobj: |
778 | nouveau_gpuobj_takedown(dev); | |
779 | out_vram: | |
780 | nouveau_mem_vram_fini(dev); | |
c5804be0 | 781 | out_bios: |
330c5988 | 782 | nouveau_pm_fini(dev); |
c5804be0 | 783 | nouveau_bios_takedown(dev); |
c88c2e06 FJ |
784 | out_display_early: |
785 | engine->display.late_takedown(dev); | |
c5804be0 MK |
786 | out: |
787 | vga_client_register(dev->pdev, NULL, NULL, NULL); | |
788 | return ret; | |
6ee73861 BS |
789 | } |
790 | ||
791 | static void nouveau_card_takedown(struct drm_device *dev) | |
792 | { | |
793 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
794 | struct nouveau_engine *engine = &dev_priv->engine; | |
795 | ||
b6d3d871 | 796 | nouveau_backlight_exit(dev); |
38651674 | 797 | |
0c6c1c2f FJ |
798 | if (!engine->graph.accel_blocked) { |
799 | nouveau_fence_fini(dev); | |
36c952e8 | 800 | nouveau_channel_put_unlocked(&dev_priv->channel); |
b6d3d871 | 801 | } |
6ee73861 | 802 | |
b6d3d871 BS |
803 | if (!nouveau_noaccel) { |
804 | engine->fifo.takedown(dev); | |
bd2e597d | 805 | engine->crypt.takedown(dev); |
b6d3d871 BS |
806 | engine->graph.takedown(dev); |
807 | } | |
808 | engine->fb.takedown(dev); | |
809 | engine->timer.takedown(dev); | |
ee2e0131 | 810 | engine->gpio.takedown(dev); |
b6d3d871 | 811 | engine->mc.takedown(dev); |
c88c2e06 | 812 | engine->display.late_takedown(dev); |
6ee73861 | 813 | |
b6d3d871 BS |
814 | mutex_lock(&dev->struct_mutex); |
815 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM); | |
816 | ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT); | |
817 | mutex_unlock(&dev->struct_mutex); | |
fbd2895e | 818 | nouveau_mem_gart_fini(dev); |
6ee73861 | 819 | |
b6d3d871 | 820 | engine->instmem.takedown(dev); |
fbd2895e BS |
821 | nouveau_gpuobj_takedown(dev); |
822 | nouveau_mem_vram_fini(dev); | |
6ee73861 | 823 | |
35fa2f2a | 824 | nouveau_irq_fini(dev); |
042206c0 | 825 | drm_vblank_cleanup(dev); |
6ee73861 | 826 | |
330c5988 | 827 | nouveau_pm_fini(dev); |
b6d3d871 | 828 | nouveau_bios_takedown(dev); |
6ee73861 | 829 | |
b6d3d871 | 830 | vga_client_register(dev->pdev, NULL, NULL, NULL); |
6ee73861 BS |
831 | } |
832 | ||
833 | /* here a client dies, release the stuff that was allocated for its | |
834 | * file_priv */ | |
835 | void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv) | |
836 | { | |
837 | nouveau_channel_cleanup(dev, file_priv); | |
838 | } | |
839 | ||
840 | /* first module load, setup the mmio/fb mapping */ | |
841 | /* KMS: we need mmio at load time, not when the first drm client opens. */ | |
842 | int nouveau_firstopen(struct drm_device *dev) | |
843 | { | |
844 | return 0; | |
845 | } | |
846 | ||
847 | /* if we have an OF card, copy vbios to RAMIN */ | |
848 | static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev) | |
849 | { | |
850 | #if defined(__powerpc__) | |
851 | int size, i; | |
852 | const uint32_t *bios; | |
853 | struct device_node *dn = pci_device_to_OF_node(dev->pdev); | |
854 | if (!dn) { | |
855 | NV_INFO(dev, "Unable to get the OF node\n"); | |
856 | return; | |
857 | } | |
858 | ||
859 | bios = of_get_property(dn, "NVDA,BMP", &size); | |
860 | if (bios) { | |
861 | for (i = 0; i < size; i += 4) | |
862 | nv_wi32(dev, i, bios[i/4]); | |
863 | NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size); | |
864 | } else { | |
865 | NV_INFO(dev, "Unable to get the OF bios\n"); | |
866 | } | |
867 | #endif | |
868 | } | |
869 | ||
06415c56 MS |
870 | static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev) |
871 | { | |
872 | struct pci_dev *pdev = dev->pdev; | |
873 | struct apertures_struct *aper = alloc_apertures(3); | |
874 | if (!aper) | |
875 | return NULL; | |
876 | ||
877 | aper->ranges[0].base = pci_resource_start(pdev, 1); | |
878 | aper->ranges[0].size = pci_resource_len(pdev, 1); | |
879 | aper->count = 1; | |
880 | ||
881 | if (pci_resource_len(pdev, 2)) { | |
882 | aper->ranges[aper->count].base = pci_resource_start(pdev, 2); | |
883 | aper->ranges[aper->count].size = pci_resource_len(pdev, 2); | |
884 | aper->count++; | |
885 | } | |
886 | ||
887 | if (pci_resource_len(pdev, 3)) { | |
888 | aper->ranges[aper->count].base = pci_resource_start(pdev, 3); | |
889 | aper->ranges[aper->count].size = pci_resource_len(pdev, 3); | |
890 | aper->count++; | |
891 | } | |
892 | ||
893 | return aper; | |
894 | } | |
895 | ||
896 | static int nouveau_remove_conflicting_drivers(struct drm_device *dev) | |
897 | { | |
898 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
3b9676e7 | 899 | bool primary = false; |
06415c56 MS |
900 | dev_priv->apertures = nouveau_get_apertures(dev); |
901 | if (!dev_priv->apertures) | |
902 | return -ENOMEM; | |
903 | ||
3b9676e7 MS |
904 | #ifdef CONFIG_X86 |
905 | primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; | |
906 | #endif | |
907 | ||
908 | remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary); | |
06415c56 MS |
909 | return 0; |
910 | } | |
911 | ||
6ee73861 BS |
912 | int nouveau_load(struct drm_device *dev, unsigned long flags) |
913 | { | |
914 | struct drm_nouveau_private *dev_priv; | |
915 | uint32_t reg0; | |
916 | resource_size_t mmio_start_offs; | |
cd0b072f | 917 | int ret; |
6ee73861 BS |
918 | |
919 | dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); | |
a0d069ea DC |
920 | if (!dev_priv) { |
921 | ret = -ENOMEM; | |
922 | goto err_out; | |
923 | } | |
6ee73861 BS |
924 | dev->dev_private = dev_priv; |
925 | dev_priv->dev = dev; | |
926 | ||
927 | dev_priv->flags = flags & NOUVEAU_FLAGS; | |
6ee73861 BS |
928 | |
929 | NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n", | |
930 | dev->pci_vendor, dev->pci_device, dev->pdev->class); | |
931 | ||
6ee73861 | 932 | dev_priv->wq = create_workqueue("nouveau"); |
a0d069ea DC |
933 | if (!dev_priv->wq) { |
934 | ret = -EINVAL; | |
935 | goto err_priv; | |
936 | } | |
6ee73861 BS |
937 | |
938 | /* resource 0 is mmio regs */ | |
939 | /* resource 1 is linear FB */ | |
940 | /* resource 2 is RAMIN (mmio regs + 0x1000000) */ | |
941 | /* resource 6 is bios */ | |
942 | ||
943 | /* map the mmio regs */ | |
944 | mmio_start_offs = pci_resource_start(dev->pdev, 0); | |
945 | dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000); | |
946 | if (!dev_priv->mmio) { | |
947 | NV_ERROR(dev, "Unable to initialize the mmio mapping. " | |
948 | "Please report your setup to " DRIVER_EMAIL "\n"); | |
a0d069ea DC |
949 | ret = -EINVAL; |
950 | goto err_wq; | |
6ee73861 BS |
951 | } |
952 | NV_DEBUG(dev, "regs mapped ok at 0x%llx\n", | |
953 | (unsigned long long)mmio_start_offs); | |
954 | ||
955 | #ifdef __BIG_ENDIAN | |
956 | /* Put the card in BE mode if it's not */ | |
957 | if (nv_rd32(dev, NV03_PMC_BOOT_1)) | |
958 | nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001); | |
959 | ||
960 | DRM_MEMORYBARRIER(); | |
961 | #endif | |
962 | ||
963 | /* Time to determine the card architecture */ | |
964 | reg0 = nv_rd32(dev, NV03_PMC_BOOT_0); | |
965 | ||
966 | /* We're dealing with >=NV10 */ | |
967 | if ((reg0 & 0x0f000000) > 0) { | |
968 | /* Bit 27-20 contain the architecture in hex */ | |
969 | dev_priv->chipset = (reg0 & 0xff00000) >> 20; | |
970 | /* NV04 or NV05 */ | |
971 | } else if ((reg0 & 0xff00fff0) == 0x20004000) { | |
1dee7a93 BS |
972 | if (reg0 & 0x00f00000) |
973 | dev_priv->chipset = 0x05; | |
974 | else | |
975 | dev_priv->chipset = 0x04; | |
6ee73861 BS |
976 | } else |
977 | dev_priv->chipset = 0xff; | |
978 | ||
979 | switch (dev_priv->chipset & 0xf0) { | |
980 | case 0x00: | |
981 | case 0x10: | |
982 | case 0x20: | |
983 | case 0x30: | |
984 | dev_priv->card_type = dev_priv->chipset & 0xf0; | |
985 | break; | |
986 | case 0x40: | |
987 | case 0x60: | |
988 | dev_priv->card_type = NV_40; | |
989 | break; | |
990 | case 0x50: | |
991 | case 0x80: | |
992 | case 0x90: | |
993 | case 0xa0: | |
994 | dev_priv->card_type = NV_50; | |
995 | break; | |
4b223eef BS |
996 | case 0xc0: |
997 | dev_priv->card_type = NV_C0; | |
998 | break; | |
6ee73861 BS |
999 | default: |
1000 | NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0); | |
a0d069ea DC |
1001 | ret = -EINVAL; |
1002 | goto err_mmio; | |
6ee73861 BS |
1003 | } |
1004 | ||
1005 | NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n", | |
1006 | dev_priv->card_type, reg0); | |
1007 | ||
cd0b072f BS |
1008 | ret = nouveau_remove_conflicting_drivers(dev); |
1009 | if (ret) | |
a0d069ea | 1010 | goto err_mmio; |
06415c56 | 1011 | |
6d696305 | 1012 | /* Map PRAMIN BAR, or on older cards, the aperture withing BAR0 */ |
6ee73861 BS |
1013 | if (dev_priv->card_type >= NV_40) { |
1014 | int ramin_bar = 2; | |
1015 | if (pci_resource_len(dev->pdev, ramin_bar) == 0) | |
1016 | ramin_bar = 3; | |
1017 | ||
1018 | dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar); | |
6d696305 BS |
1019 | dev_priv->ramin = |
1020 | ioremap(pci_resource_start(dev->pdev, ramin_bar), | |
6ee73861 BS |
1021 | dev_priv->ramin_size); |
1022 | if (!dev_priv->ramin) { | |
6d696305 | 1023 | NV_ERROR(dev, "Failed to PRAMIN BAR"); |
a0d069ea DC |
1024 | ret = -ENOMEM; |
1025 | goto err_mmio; | |
6ee73861 | 1026 | } |
6d696305 | 1027 | } else { |
6ee73861 BS |
1028 | dev_priv->ramin_size = 1 * 1024 * 1024; |
1029 | dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN, | |
6d696305 | 1030 | dev_priv->ramin_size); |
6ee73861 BS |
1031 | if (!dev_priv->ramin) { |
1032 | NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n"); | |
a0d069ea DC |
1033 | ret = -ENOMEM; |
1034 | goto err_mmio; | |
6ee73861 BS |
1035 | } |
1036 | } | |
1037 | ||
1038 | nouveau_OF_copy_vbios_to_ramin(dev); | |
1039 | ||
1040 | /* Special flags */ | |
1041 | if (dev->pci_device == 0x01a0) | |
1042 | dev_priv->flags |= NV_NFORCE; | |
1043 | else if (dev->pci_device == 0x01f0) | |
1044 | dev_priv->flags |= NV_NFORCE2; | |
1045 | ||
1046 | /* For kernel modesetting, init card now and bring up fbcon */ | |
cd0b072f BS |
1047 | ret = nouveau_card_init(dev); |
1048 | if (ret) | |
a0d069ea | 1049 | goto err_ramin; |
6ee73861 BS |
1050 | |
1051 | return 0; | |
a0d069ea DC |
1052 | |
1053 | err_ramin: | |
1054 | iounmap(dev_priv->ramin); | |
1055 | err_mmio: | |
1056 | iounmap(dev_priv->mmio); | |
1057 | err_wq: | |
1058 | destroy_workqueue(dev_priv->wq); | |
1059 | err_priv: | |
1060 | kfree(dev_priv); | |
1061 | dev->dev_private = NULL; | |
1062 | err_out: | |
1063 | return ret; | |
6ee73861 BS |
1064 | } |
1065 | ||
6ee73861 BS |
1066 | void nouveau_lastclose(struct drm_device *dev) |
1067 | { | |
5ccb377f | 1068 | vga_switcheroo_process_delayed_switch(); |
6ee73861 BS |
1069 | } |
1070 | ||
1071 | int nouveau_unload(struct drm_device *dev) | |
1072 | { | |
1073 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
c88c2e06 | 1074 | struct nouveau_engine *engine = &dev_priv->engine; |
6ee73861 | 1075 | |
cd0b072f BS |
1076 | drm_kms_helper_poll_fini(dev); |
1077 | nouveau_fbcon_fini(dev); | |
c88c2e06 | 1078 | engine->display.destroy(dev); |
cd0b072f | 1079 | nouveau_card_takedown(dev); |
6ee73861 BS |
1080 | |
1081 | iounmap(dev_priv->mmio); | |
1082 | iounmap(dev_priv->ramin); | |
1083 | ||
1084 | kfree(dev_priv); | |
1085 | dev->dev_private = NULL; | |
1086 | return 0; | |
1087 | } | |
1088 | ||
6ee73861 BS |
1089 | int nouveau_ioctl_getparam(struct drm_device *dev, void *data, |
1090 | struct drm_file *file_priv) | |
1091 | { | |
1092 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1093 | struct drm_nouveau_getparam *getparam = data; | |
1094 | ||
6ee73861 BS |
1095 | switch (getparam->param) { |
1096 | case NOUVEAU_GETPARAM_CHIPSET_ID: | |
1097 | getparam->value = dev_priv->chipset; | |
1098 | break; | |
1099 | case NOUVEAU_GETPARAM_PCI_VENDOR: | |
1100 | getparam->value = dev->pci_vendor; | |
1101 | break; | |
1102 | case NOUVEAU_GETPARAM_PCI_DEVICE: | |
1103 | getparam->value = dev->pci_device; | |
1104 | break; | |
1105 | case NOUVEAU_GETPARAM_BUS_TYPE: | |
8410ea3b | 1106 | if (drm_pci_device_is_agp(dev)) |
6ee73861 | 1107 | getparam->value = NV_AGP; |
8410ea3b | 1108 | else if (drm_pci_device_is_pcie(dev)) |
6ee73861 BS |
1109 | getparam->value = NV_PCIE; |
1110 | else | |
1111 | getparam->value = NV_PCI; | |
1112 | break; | |
6ee73861 BS |
1113 | case NOUVEAU_GETPARAM_FB_SIZE: |
1114 | getparam->value = dev_priv->fb_available_size; | |
1115 | break; | |
1116 | case NOUVEAU_GETPARAM_AGP_SIZE: | |
1117 | getparam->value = dev_priv->gart_info.aper_size; | |
1118 | break; | |
1119 | case NOUVEAU_GETPARAM_VM_VRAM_BASE: | |
6d6c5a15 | 1120 | getparam->value = 0; /* deprecated */ |
6ee73861 | 1121 | break; |
7fc74f17 MK |
1122 | case NOUVEAU_GETPARAM_PTIMER_TIME: |
1123 | getparam->value = dev_priv->engine.timer.read(dev); | |
1124 | break; | |
f13b3263 FJ |
1125 | case NOUVEAU_GETPARAM_HAS_BO_USAGE: |
1126 | getparam->value = 1; | |
1127 | break; | |
332b242f FJ |
1128 | case NOUVEAU_GETPARAM_HAS_PAGEFLIP: |
1129 | getparam->value = (dev_priv->card_type < NV_50); | |
1130 | break; | |
69c9700b MK |
1131 | case NOUVEAU_GETPARAM_GRAPH_UNITS: |
1132 | /* NV40 and NV50 versions are quite different, but register | |
1133 | * address is the same. User is supposed to know the card | |
1134 | * family anyway... */ | |
1135 | if (dev_priv->chipset >= 0x40) { | |
1136 | getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS); | |
1137 | break; | |
1138 | } | |
1139 | /* FALLTHRU */ | |
6ee73861 | 1140 | default: |
1397b42b | 1141 | NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param); |
6ee73861 BS |
1142 | return -EINVAL; |
1143 | } | |
1144 | ||
1145 | return 0; | |
1146 | } | |
1147 | ||
1148 | int | |
1149 | nouveau_ioctl_setparam(struct drm_device *dev, void *data, | |
1150 | struct drm_file *file_priv) | |
1151 | { | |
1152 | struct drm_nouveau_setparam *setparam = data; | |
1153 | ||
6ee73861 BS |
1154 | switch (setparam->param) { |
1155 | default: | |
1397b42b | 1156 | NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param); |
6ee73861 BS |
1157 | return -EINVAL; |
1158 | } | |
1159 | ||
1160 | return 0; | |
1161 | } | |
1162 | ||
1163 | /* Wait until (value(reg) & mask) == val, up until timeout has hit */ | |
12fb9525 BS |
1164 | bool |
1165 | nouveau_wait_eq(struct drm_device *dev, uint64_t timeout, | |
1166 | uint32_t reg, uint32_t mask, uint32_t val) | |
6ee73861 BS |
1167 | { |
1168 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1169 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1170 | uint64_t start = ptimer->read(dev); | |
1171 | ||
1172 | do { | |
1173 | if ((nv_rd32(dev, reg) & mask) == val) | |
1174 | return true; | |
1175 | } while (ptimer->read(dev) - start < timeout); | |
1176 | ||
1177 | return false; | |
1178 | } | |
1179 | ||
12fb9525 BS |
1180 | /* Wait until (value(reg) & mask) != val, up until timeout has hit */ |
1181 | bool | |
1182 | nouveau_wait_ne(struct drm_device *dev, uint64_t timeout, | |
1183 | uint32_t reg, uint32_t mask, uint32_t val) | |
1184 | { | |
1185 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
1186 | struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer; | |
1187 | uint64_t start = ptimer->read(dev); | |
1188 | ||
1189 | do { | |
1190 | if ((nv_rd32(dev, reg) & mask) != val) | |
1191 | return true; | |
1192 | } while (ptimer->read(dev) - start < timeout); | |
1193 | ||
1194 | return false; | |
1195 | } | |
1196 | ||
6ee73861 BS |
1197 | /* Waits for PGRAPH to go completely idle */ |
1198 | bool nouveau_wait_for_idle(struct drm_device *dev) | |
1199 | { | |
0541324a FJ |
1200 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
1201 | uint32_t mask = ~0; | |
1202 | ||
1203 | if (dev_priv->card_type == NV_40) | |
1204 | mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL; | |
1205 | ||
1206 | if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) { | |
6ee73861 BS |
1207 | NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n", |
1208 | nv_rd32(dev, NV04_PGRAPH_STATUS)); | |
1209 | return false; | |
1210 | } | |
1211 | ||
1212 | return true; | |
1213 | } | |
1214 |