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20abd163 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include "drmP.h" | |
35bcf5d5 | 26 | |
20abd163 | 27 | #include "nouveau_drv.h" |
02a841d4 | 28 | #include <core/ramht.h> |
5e120f6e | 29 | #include "nouveau_fence.h" |
20abd163 BS |
30 | #include "nouveau_software.h" |
31 | #include "nouveau_hw.h" | |
32 | ||
33 | struct nv04_software_priv { | |
34 | struct nouveau_software_priv base; | |
35 | }; | |
36 | ||
37 | struct nv04_software_chan { | |
38 | struct nouveau_software_chan base; | |
39 | }; | |
40 | ||
20abd163 BS |
41 | static int |
42 | mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data) | |
43 | { | |
f589be88 BS |
44 | struct nv04_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW]; |
45 | return pch->base.flip(pch->base.flip_data); | |
20abd163 BS |
46 | } |
47 | ||
48 | static int | |
49 | nv04_software_context_new(struct nouveau_channel *chan, int engine) | |
50 | { | |
51 | struct nv04_software_chan *pch; | |
52 | ||
53 | pch = kzalloc(sizeof(*pch), GFP_KERNEL); | |
54 | if (!pch) | |
55 | return -ENOMEM; | |
56 | ||
f589be88 | 57 | nouveau_software_context_new(chan, &pch->base); |
20abd163 BS |
58 | chan->engctx[engine] = pch; |
59 | return 0; | |
60 | } | |
61 | ||
62 | static void | |
63 | nv04_software_context_del(struct nouveau_channel *chan, int engine) | |
64 | { | |
65 | struct nv04_software_chan *pch = chan->engctx[engine]; | |
66 | chan->engctx[engine] = NULL; | |
67 | kfree(pch); | |
68 | } | |
69 | ||
70 | static int | |
71 | nv04_software_object_new(struct nouveau_channel *chan, int engine, | |
72 | u32 handle, u16 class) | |
73 | { | |
74 | struct drm_device *dev = chan->dev; | |
75 | struct nouveau_gpuobj *obj = NULL; | |
76 | int ret; | |
77 | ||
78 | ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj); | |
79 | if (ret) | |
80 | return ret; | |
81 | obj->engine = 0; | |
82 | obj->class = class; | |
83 | ||
84 | ret = nouveau_ramht_insert(chan, handle, obj); | |
85 | nouveau_gpuobj_ref(NULL, &obj); | |
86 | return ret; | |
87 | } | |
88 | ||
89 | static int | |
90 | nv04_software_init(struct drm_device *dev, int engine) | |
91 | { | |
92 | return 0; | |
93 | } | |
94 | ||
95 | static int | |
96 | nv04_software_fini(struct drm_device *dev, int engine, bool suspend) | |
97 | { | |
98 | return 0; | |
99 | } | |
100 | ||
101 | static void | |
102 | nv04_software_destroy(struct drm_device *dev, int engine) | |
103 | { | |
104 | struct nv04_software_priv *psw = nv_engine(dev, engine); | |
105 | ||
106 | NVOBJ_ENGINE_DEL(dev, SW); | |
107 | kfree(psw); | |
108 | } | |
109 | ||
110 | int | |
111 | nv04_software_create(struct drm_device *dev) | |
112 | { | |
113 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
114 | struct nv04_software_priv *psw; | |
115 | ||
116 | psw = kzalloc(sizeof(*psw), GFP_KERNEL); | |
117 | if (!psw) | |
118 | return -ENOMEM; | |
119 | ||
120 | psw->base.base.destroy = nv04_software_destroy; | |
121 | psw->base.base.init = nv04_software_init; | |
122 | psw->base.base.fini = nv04_software_fini; | |
123 | psw->base.base.context_new = nv04_software_context_new; | |
124 | psw->base.base.context_del = nv04_software_context_del; | |
125 | psw->base.base.object_new = nv04_software_object_new; | |
126 | nouveau_software_create(&psw->base); | |
127 | ||
128 | NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base); | |
129 | if (dev_priv->card_type <= NV_04) { | |
130 | NVOBJ_CLASS(dev, 0x006e, SW); | |
5e120f6e | 131 | NVOBJ_MTHD (dev, 0x006e, 0x0150, nv04_fence_mthd); |
20abd163 BS |
132 | NVOBJ_MTHD (dev, 0x006e, 0x0500, mthd_flip); |
133 | } else { | |
134 | NVOBJ_CLASS(dev, 0x016e, SW); | |
135 | NVOBJ_MTHD (dev, 0x016e, 0x0500, mthd_flip); | |
136 | } | |
137 | ||
138 | return 0; | |
139 | } |