[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv17_fence.c

/*
 * Copyright 2012 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs <bskeggs@redhat.com>
 */

#include <core/object.h>
#include <core/class.h>

#include "nouveau_drm.h"
#include "nouveau_dma.h"
#include "nv10_fence.h"

int
nv17_fence_sync(struct nouveau_fence *fence,
		struct nouveau_channel *prev, struct nouveau_channel *chan)
{
	struct nouveau_cli *cli = (void *)nvif_client(&prev->device->base);
	struct nv10_fence_priv *priv = chan->drm->fence;
	struct nv10_fence_chan *fctx = chan->fence;
	u32 value;
	int ret;

	if (!mutex_trylock(&cli->mutex))
		return -EBUSY;

	spin_lock(&priv->lock);
	value = priv->sequence;
	priv->sequence += 2;
	spin_unlock(&priv->lock);

	ret = RING_SPACE(prev, 5);
	if (!ret) {
		BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
		OUT_RING  (prev, fctx->sema.handle);
		OUT_RING  (prev, 0);
		OUT_RING  (prev, value + 0);
		OUT_RING  (prev, value + 1);
		FIRE_RING (prev);
	}

	if (!ret && !(ret = RING_SPACE(chan, 5))) {
		BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
		OUT_RING  (chan, fctx->sema.handle);
		OUT_RING  (chan, 0);
		OUT_RING  (chan, value + 1);
		OUT_RING  (chan, value + 2);
		FIRE_RING (chan);
	}

	mutex_unlock(&cli->mutex);
	return 0;
}

static int
nv17_fence_context_new(struct nouveau_channel *chan)
{
	struct nv10_fence_priv *priv = chan->drm->fence;
	struct nv10_fence_chan *fctx;
	struct ttm_mem_reg *mem = &priv->bo->bo.mem;
	u32 start = mem->start * PAGE_SIZE;
	u32 limit = start + mem->size - 1;
	int ret = 0;

	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
	if (!fctx)
		return -ENOMEM;

	nouveau_fence_context_new(&fctx->base);
	fctx->base.emit = nv10_fence_emit;
	fctx->base.read = nv10_fence_read;
	fctx->base.sync = nv17_fence_sync;

	ret = nvif_object_init(chan->object, NULL, NvSema,
				NV_DMA_FROM_MEMORY_CLASS,
			       &(struct nv_dma_class) {
					.flags = NV_DMA_TARGET_VRAM |
						 NV_DMA_ACCESS_RDWR,
					.start = start,
					.limit = limit,
			       }, sizeof(struct nv_dma_class),
			       &fctx->sema);
	if (ret)
		nv10_fence_context_del(chan);
	return ret;
}

void
nv17_fence_resume(struct nouveau_drm *drm)
{
	struct nv10_fence_priv *priv = drm->fence;

	nouveau_bo_wr32(priv->bo, 0, priv->sequence);
}

int
nv17_fence_create(struct nouveau_drm *drm)
{
	struct nv10_fence_priv *priv;
	int ret = 0;

	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	priv->base.dtor = nv10_fence_destroy;
	priv->base.resume = nv17_fence_resume;
	priv->base.context_new = nv17_fence_context_new;
	priv->base.context_del = nv10_fence_context_del;
	spin_lock_init(&priv->lock);

	ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
			     0, 0x0000, NULL, &priv->bo);
	if (!ret) {
		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
		if (!ret) {
			ret = nouveau_bo_map(priv->bo);
			if (ret)
				nouveau_bo_unpin(priv->bo);
		}
		if (ret)
			nouveau_bo_ref(NULL, &priv->bo);
	}

	if (ret) {
		nv10_fence_destroy(drm);
		return ret;
	}

	nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
	return ret;
}
Commit	Line	Data
60e5cb79 BS	1	/*
	2	* Copyright 2012 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs <bskeggs@redhat.com>
	23	*/
	24
	25	#include <core/object.h>
	26	#include <core/class.h>
	27
	28	#include "nouveau_drm.h"
	29	#include "nouveau_dma.h"
	30	#include "nv10_fence.h"
	31
	32	int
	33	nv17_fence_sync(struct nouveau_fence *fence,
	34	struct nouveau_channel prev, struct nouveau_channel chan)
	35	{
0ad72863	36	struct nouveau_cli cli = (void )nvif_client(&prev->device->base);
60e5cb79	37	struct nv10_fence_priv *priv = chan->drm->fence;
f45f55c4	38	struct nv10_fence_chan *fctx = chan->fence;
60e5cb79 BS	39	u32 value;
	40	int ret;
	41
0ad72863	42	if (!mutex_trylock(&cli->mutex))
60e5cb79 BS	43	return -EBUSY;
	44
	45	spin_lock(&priv->lock);
	46	value = priv->sequence;
	47	priv->sequence += 2;
	48	spin_unlock(&priv->lock);
	49
	50	ret = RING_SPACE(prev, 5);
	51	if (!ret) {
	52	BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
f45f55c4	53	OUT_RING (prev, fctx->sema.handle);
60e5cb79 BS	54	OUT_RING (prev, 0);
	55	OUT_RING (prev, value + 0);
	56	OUT_RING (prev, value + 1);
	57	FIRE_RING (prev);
	58	}
	59
	60	if (!ret && !(ret = RING_SPACE(chan, 5))) {
	61	BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4);
f45f55c4	62	OUT_RING (chan, fctx->sema.handle);
60e5cb79 BS	63	OUT_RING (chan, 0);
	64	OUT_RING (chan, value + 1);
	65	OUT_RING (chan, value + 2);
	66	FIRE_RING (chan);
	67	}
	68
0ad72863	69	mutex_unlock(&cli->mutex);
60e5cb79 BS	70	return 0;
	71	}
	72
	73	static int
	74	nv17_fence_context_new(struct nouveau_channel *chan)
	75	{
	76	struct nv10_fence_priv *priv = chan->drm->fence;
	77	struct nv10_fence_chan *fctx;
	78	struct ttm_mem_reg *mem = &priv->bo->bo.mem;
60e5cb79	79	u32 start = mem->start * PAGE_SIZE;
7a7da592	80	u32 limit = start + mem->size - 1;
60e5cb79 BS	81	int ret = 0;
	82
	83	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
	84	if (!fctx)
	85	return -ENOMEM;
	86
	87	nouveau_fence_context_new(&fctx->base);
827520ce BS	88	fctx->base.emit = nv10_fence_emit;
	89	fctx->base.read = nv10_fence_read;
	90	fctx->base.sync = nv17_fence_sync;
60e5cb79	91
0ad72863 BS	92	ret = nvif_object_init(chan->object, NULL, NvSema,
	93	NV_DMA_FROM_MEMORY_CLASS,
	94	&(struct nv_dma_class) {
60e5cb79 BS	95	.flags = NV_DMA_TARGET_VRAM \|
	96	NV_DMA_ACCESS_RDWR,
	97	.start = start,
	98	.limit = limit,
0ad72863 BS	99	}, sizeof(struct nv_dma_class),
0ad72863 BS	100	&fctx->sema);
60e5cb79 BS	101	if (ret)
	102	nv10_fence_context_del(chan);
	103	return ret;
	104	}
	105
	106	void
	107	nv17_fence_resume(struct nouveau_drm *drm)
	108	{
	109	struct nv10_fence_priv *priv = drm->fence;
	110
	111	nouveau_bo_wr32(priv->bo, 0, priv->sequence);
	112	}
	113
	114	int
	115	nv17_fence_create(struct nouveau_drm *drm)
	116	{
	117	struct nv10_fence_priv *priv;
	118	int ret = 0;
	119
	120	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
	121	if (!priv)
	122	return -ENOMEM;
	123
	124	priv->base.dtor = nv10_fence_destroy;
	125	priv->base.resume = nv17_fence_resume;
	126	priv->base.context_new = nv17_fence_context_new;
	127	priv->base.context_del = nv10_fence_context_del;
60e5cb79 BS	128	spin_lock_init(&priv->lock);
	129
	130	ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
	131	0, 0x0000, NULL, &priv->bo);
	132	if (!ret) {
	133	ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
	134	if (!ret) {
	135	ret = nouveau_bo_map(priv->bo);
	136	if (ret)
	137	nouveau_bo_unpin(priv->bo);
	138	}
	139	if (ret)
	140	nouveau_bo_ref(NULL, &priv->bo);
	141	}
	142
	143	if (ret) {
	144	nv10_fence_destroy(drm);
	145	return ret;
	146	}
	147
	148	nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
	149	return ret;
	150	}