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1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | |
23 | */ | |
24 | ||
fdb751ef BS |
25 | #include <nvif/os.h> |
26 | #include <nvif/class.h> | |
845f2725 | 27 | #include <nvif/cl0002.h> |
60e5cb79 | 28 | |
4dc28134 | 29 | #include "nouveau_drv.h" |
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30 | #include "nouveau_dma.h" |
31 | #include "nv10_fence.h" | |
32 | ||
33 | int | |
34 | nv17_fence_sync(struct nouveau_fence *fence, | |
35 | struct nouveau_channel *prev, struct nouveau_channel *chan) | |
36 | { | |
a01ca78c | 37 | struct nouveau_cli *cli = (void *)prev->user.client; |
60e5cb79 | 38 | struct nv10_fence_priv *priv = chan->drm->fence; |
f45f55c4 | 39 | struct nv10_fence_chan *fctx = chan->fence; |
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40 | u32 value; |
41 | int ret; | |
42 | ||
0ad72863 | 43 | if (!mutex_trylock(&cli->mutex)) |
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44 | return -EBUSY; |
45 | ||
46 | spin_lock(&priv->lock); | |
47 | value = priv->sequence; | |
48 | priv->sequence += 2; | |
49 | spin_unlock(&priv->lock); | |
50 | ||
51 | ret = RING_SPACE(prev, 5); | |
52 | if (!ret) { | |
53 | BEGIN_NV04(prev, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); | |
f45f55c4 | 54 | OUT_RING (prev, fctx->sema.handle); |
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55 | OUT_RING (prev, 0); |
56 | OUT_RING (prev, value + 0); | |
57 | OUT_RING (prev, value + 1); | |
58 | FIRE_RING (prev); | |
59 | } | |
60 | ||
61 | if (!ret && !(ret = RING_SPACE(chan, 5))) { | |
62 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 4); | |
f45f55c4 | 63 | OUT_RING (chan, fctx->sema.handle); |
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64 | OUT_RING (chan, 0); |
65 | OUT_RING (chan, value + 1); | |
66 | OUT_RING (chan, value + 2); | |
67 | FIRE_RING (chan); | |
68 | } | |
69 | ||
0ad72863 | 70 | mutex_unlock(&cli->mutex); |
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71 | return 0; |
72 | } | |
73 | ||
74 | static int | |
75 | nv17_fence_context_new(struct nouveau_channel *chan) | |
76 | { | |
77 | struct nv10_fence_priv *priv = chan->drm->fence; | |
78 | struct nv10_fence_chan *fctx; | |
79 | struct ttm_mem_reg *mem = &priv->bo->bo.mem; | |
60e5cb79 | 80 | u32 start = mem->start * PAGE_SIZE; |
7a7da592 | 81 | u32 limit = start + mem->size - 1; |
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82 | int ret = 0; |
83 | ||
84 | fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); | |
85 | if (!fctx) | |
86 | return -ENOMEM; | |
87 | ||
29ba89b2 | 88 | nouveau_fence_context_new(chan, &fctx->base); |
827520ce BS |
89 | fctx->base.emit = nv10_fence_emit; |
90 | fctx->base.read = nv10_fence_read; | |
91 | fctx->base.sync = nv17_fence_sync; | |
60e5cb79 | 92 | |
a01ca78c | 93 | ret = nvif_object_init(&chan->user, NvSema, NV_DMA_FROM_MEMORY, |
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94 | &(struct nv_dma_v0) { |
95 | .target = NV_DMA_V0_TARGET_VRAM, | |
96 | .access = NV_DMA_V0_ACCESS_RDWR, | |
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97 | .start = start, |
98 | .limit = limit, | |
4acfd707 | 99 | }, sizeof(struct nv_dma_v0), |
0ad72863 | 100 | &fctx->sema); |
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101 | if (ret) |
102 | nv10_fence_context_del(chan); | |
103 | return ret; | |
104 | } | |
105 | ||
106 | void | |
107 | nv17_fence_resume(struct nouveau_drm *drm) | |
108 | { | |
109 | struct nv10_fence_priv *priv = drm->fence; | |
110 | ||
111 | nouveau_bo_wr32(priv->bo, 0, priv->sequence); | |
112 | } | |
113 | ||
114 | int | |
115 | nv17_fence_create(struct nouveau_drm *drm) | |
116 | { | |
117 | struct nv10_fence_priv *priv; | |
118 | int ret = 0; | |
119 | ||
120 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); | |
121 | if (!priv) | |
122 | return -ENOMEM; | |
123 | ||
124 | priv->base.dtor = nv10_fence_destroy; | |
125 | priv->base.resume = nv17_fence_resume; | |
126 | priv->base.context_new = nv17_fence_context_new; | |
127 | priv->base.context_del = nv10_fence_context_del; | |
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128 | priv->base.contexts = 31; |
129 | priv->base.context_base = fence_context_alloc(priv->base.contexts); | |
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130 | spin_lock_init(&priv->lock); |
131 | ||
132 | ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | |
bb6178b0 | 133 | 0, 0x0000, NULL, NULL, &priv->bo); |
60e5cb79 | 134 | if (!ret) { |
ad76b3f7 | 135 | ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM, false); |
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136 | if (!ret) { |
137 | ret = nouveau_bo_map(priv->bo); | |
138 | if (ret) | |
139 | nouveau_bo_unpin(priv->bo); | |
140 | } | |
141 | if (ret) | |
142 | nouveau_bo_ref(NULL, &priv->bo); | |
143 | } | |
144 | ||
145 | if (ret) { | |
146 | nv10_fence_destroy(drm); | |
147 | return ret; | |
148 | } | |
149 | ||
150 | nouveau_bo_wr32(priv->bo, 0x000, 0x00000000); | |
151 | return ret; | |
152 | } |