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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2007 Ben Skeggs. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining | |
6 | * a copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sublicense, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial | |
15 | * portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
6ee73861 BS |
27 | #include "drmP.h" |
28 | #include "drm.h" | |
29 | #include "nouveau_drv.h" | |
054b93e4 | 30 | #include "nouveau_grctx.h" |
6ee73861 BS |
31 | |
32 | struct nouveau_channel * | |
33 | nv40_graph_channel(struct drm_device *dev) | |
34 | { | |
35 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
36 | uint32_t inst; | |
37 | int i; | |
38 | ||
39 | inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR); | |
40 | if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED)) | |
41 | return NULL; | |
42 | inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4; | |
43 | ||
44 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
cff5c133 | 45 | struct nouveau_channel *chan = dev_priv->channels.ptr[i]; |
6ee73861 BS |
46 | |
47 | if (chan && chan->ramin_grctx && | |
a8eaebc6 | 48 | chan->ramin_grctx->pinst == inst) |
6ee73861 BS |
49 | return chan; |
50 | } | |
51 | ||
52 | return NULL; | |
53 | } | |
54 | ||
55 | int | |
56 | nv40_graph_create_context(struct nouveau_channel *chan) | |
57 | { | |
58 | struct drm_device *dev = chan->dev; | |
59 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
054b93e4 | 60 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; |
ec91db26 | 61 | struct nouveau_grctx ctx = {}; |
6ee73861 BS |
62 | int ret; |
63 | ||
a8eaebc6 BS |
64 | ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16, |
65 | NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx); | |
6ee73861 BS |
66 | if (ret) |
67 | return ret; | |
6ee73861 BS |
68 | |
69 | /* Initialise default context values */ | |
ec91db26 BS |
70 | ctx.dev = chan->dev; |
71 | ctx.mode = NOUVEAU_GRCTX_VALS; | |
a8eaebc6 | 72 | ctx.data = chan->ramin_grctx; |
ec91db26 | 73 | nv40_grctx_init(&ctx); |
6ee73861 | 74 | |
5125bfd8 | 75 | nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst); |
6ee73861 BS |
76 | return 0; |
77 | } | |
78 | ||
79 | void | |
80 | nv40_graph_destroy_context(struct nouveau_channel *chan) | |
81 | { | |
3945e475 FJ |
82 | struct drm_device *dev = chan->dev; |
83 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
84 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | |
85 | unsigned long flags; | |
86 | ||
87 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); | |
88 | pgraph->fifo_access(dev, false); | |
89 | ||
90 | /* Unload the context if it's the currently active one */ | |
91 | if (pgraph->channel(dev) == chan) | |
92 | pgraph->unload_context(dev); | |
93 | ||
94 | pgraph->fifo_access(dev, true); | |
95 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); | |
96 | ||
97 | /* Free the context resources */ | |
a8eaebc6 | 98 | nouveau_gpuobj_ref(NULL, &chan->ramin_grctx); |
6ee73861 BS |
99 | } |
100 | ||
101 | static int | |
102 | nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save) | |
103 | { | |
104 | uint32_t old_cp, tv = 1000, tmp; | |
105 | int i; | |
106 | ||
107 | old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER); | |
108 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); | |
109 | ||
110 | tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310); | |
111 | tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE : | |
112 | NV40_PGRAPH_CTXCTL_0310_XFER_LOAD; | |
113 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp); | |
114 | ||
115 | tmp = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304); | |
116 | tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX; | |
117 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp); | |
118 | ||
119 | nouveau_wait_for_idle(dev); | |
120 | ||
121 | for (i = 0; i < tv; i++) { | |
122 | if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0) | |
123 | break; | |
124 | } | |
125 | ||
126 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp); | |
127 | ||
128 | if (i == tv) { | |
129 | uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT); | |
130 | NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save); | |
131 | NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n", | |
132 | ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT, | |
133 | ucstat & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK); | |
134 | NV_ERROR(dev, "0x40030C = 0x%08x\n", | |
135 | nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C)); | |
136 | return -EBUSY; | |
137 | } | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
142 | /* Restore the context for a specific channel into PGRAPH */ | |
143 | int | |
144 | nv40_graph_load_context(struct nouveau_channel *chan) | |
145 | { | |
146 | struct drm_device *dev = chan->dev; | |
147 | uint32_t inst; | |
148 | int ret; | |
149 | ||
150 | if (!chan->ramin_grctx) | |
151 | return -EINVAL; | |
a8eaebc6 | 152 | inst = chan->ramin_grctx->pinst >> 4; |
6ee73861 BS |
153 | |
154 | ret = nv40_graph_transfer_context(dev, inst, 0); | |
155 | if (ret) | |
156 | return ret; | |
157 | ||
158 | /* 0x40032C, no idea of it's exact function. Could simply be a | |
159 | * record of the currently active PGRAPH context. It's currently | |
160 | * unknown as to what bit 24 does. The nv ddx has it set, so we will | |
161 | * set it here too. | |
162 | */ | |
163 | nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst); | |
164 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, | |
165 | (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) | | |
166 | NV40_PGRAPH_CTXCTL_CUR_LOADED); | |
167 | /* 0x32E0 records the instance address of the active FIFO's PGRAPH | |
168 | * context. If at any time this doesn't match 0x40032C, you will | |
169 | * recieve PGRAPH_INTR_CONTEXT_SWITCH | |
170 | */ | |
171 | nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst); | |
172 | return 0; | |
173 | } | |
174 | ||
175 | int | |
176 | nv40_graph_unload_context(struct drm_device *dev) | |
177 | { | |
178 | uint32_t inst; | |
179 | int ret; | |
180 | ||
181 | inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR); | |
182 | if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED)) | |
183 | return 0; | |
184 | inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE; | |
185 | ||
186 | ret = nv40_graph_transfer_context(dev, inst, 1); | |
187 | ||
188 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst); | |
189 | return ret; | |
190 | } | |
191 | ||
0d87c100 FJ |
192 | void |
193 | nv40_graph_set_region_tiling(struct drm_device *dev, int i, uint32_t addr, | |
194 | uint32_t size, uint32_t pitch) | |
195 | { | |
196 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
197 | uint32_t limit = max(1u, addr + size) - 1; | |
198 | ||
199 | if (pitch) | |
200 | addr |= 1; | |
201 | ||
202 | switch (dev_priv->chipset) { | |
203 | case 0x44: | |
204 | case 0x4a: | |
205 | case 0x4e: | |
206 | nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch); | |
207 | nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit); | |
208 | nv_wr32(dev, NV20_PGRAPH_TILE(i), addr); | |
209 | break; | |
210 | ||
211 | case 0x46: | |
212 | case 0x47: | |
213 | case 0x49: | |
214 | case 0x4b: | |
215 | nv_wr32(dev, NV47_PGRAPH_TSIZE(i), pitch); | |
216 | nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), limit); | |
217 | nv_wr32(dev, NV47_PGRAPH_TILE(i), addr); | |
218 | nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch); | |
219 | nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit); | |
220 | nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr); | |
221 | break; | |
222 | ||
223 | default: | |
224 | nv_wr32(dev, NV20_PGRAPH_TSIZE(i), pitch); | |
225 | nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), limit); | |
226 | nv_wr32(dev, NV20_PGRAPH_TILE(i), addr); | |
227 | nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), pitch); | |
228 | nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), limit); | |
229 | nv_wr32(dev, NV40_PGRAPH_TILE1(i), addr); | |
230 | break; | |
231 | } | |
232 | } | |
233 | ||
6ee73861 BS |
234 | /* |
235 | * G70 0x47 | |
236 | * G71 0x49 | |
237 | * NV45 0x48 | |
238 | * G72[M] 0x46 | |
239 | * G73 0x4b | |
240 | * C51_G7X 0x4c | |
241 | * C51 0x4e | |
242 | */ | |
243 | int | |
244 | nv40_graph_init(struct drm_device *dev) | |
245 | { | |
246 | struct drm_nouveau_private *dev_priv = | |
247 | (struct drm_nouveau_private *)dev->dev_private; | |
0d87c100 | 248 | struct nouveau_fb_engine *pfb = &dev_priv->engine.fb; |
ec91db26 BS |
249 | struct nouveau_grctx ctx = {}; |
250 | uint32_t vramsz, *cp; | |
6ee73861 BS |
251 | int i, j; |
252 | ||
253 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & | |
254 | ~NV_PMC_ENABLE_PGRAPH); | |
255 | nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | | |
256 | NV_PMC_ENABLE_PGRAPH); | |
257 | ||
ec91db26 BS |
258 | cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL); |
259 | if (!cp) | |
260 | return -ENOMEM; | |
054b93e4 | 261 | |
ec91db26 BS |
262 | ctx.dev = dev; |
263 | ctx.mode = NOUVEAU_GRCTX_PROG; | |
264 | ctx.data = cp; | |
265 | ctx.ctxprog_max = 256; | |
266 | nv40_grctx_init(&ctx); | |
267 | dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4; | |
054b93e4 | 268 | |
ec91db26 BS |
269 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0); |
270 | for (i = 0; i < ctx.ctxprog_len; i++) | |
271 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]); | |
f49d273d | 272 | |
ec91db26 | 273 | kfree(cp); |
6ee73861 BS |
274 | |
275 | /* No context present currently */ | |
276 | nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000); | |
277 | ||
278 | nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF); | |
279 | nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF); | |
280 | ||
281 | nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF); | |
282 | nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000); | |
283 | nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0); | |
284 | nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055); | |
285 | nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000); | |
286 | nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f); | |
287 | ||
288 | nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100); | |
289 | nv_wr32(dev, NV10_PGRAPH_STATE , 0xFFFFFFFF); | |
290 | ||
291 | j = nv_rd32(dev, 0x1540) & 0xff; | |
292 | if (j) { | |
293 | for (i = 0; !(j & 1); j >>= 1, i++) | |
294 | ; | |
295 | nv_wr32(dev, 0x405000, i); | |
296 | } | |
297 | ||
298 | if (dev_priv->chipset == 0x40) { | |
299 | nv_wr32(dev, 0x4009b0, 0x83280fff); | |
300 | nv_wr32(dev, 0x4009b4, 0x000000a0); | |
301 | } else { | |
302 | nv_wr32(dev, 0x400820, 0x83280eff); | |
303 | nv_wr32(dev, 0x400824, 0x000000a0); | |
304 | } | |
305 | ||
306 | switch (dev_priv->chipset) { | |
307 | case 0x40: | |
308 | case 0x45: | |
309 | nv_wr32(dev, 0x4009b8, 0x0078e366); | |
310 | nv_wr32(dev, 0x4009bc, 0x0000014c); | |
311 | break; | |
312 | case 0x41: | |
313 | case 0x42: /* pciid also 0x00Cx */ | |
314 | /* case 0x0120: XXX (pciid) */ | |
315 | nv_wr32(dev, 0x400828, 0x007596ff); | |
316 | nv_wr32(dev, 0x40082c, 0x00000108); | |
317 | break; | |
318 | case 0x43: | |
319 | nv_wr32(dev, 0x400828, 0x0072cb77); | |
320 | nv_wr32(dev, 0x40082c, 0x00000108); | |
321 | break; | |
322 | case 0x44: | |
323 | case 0x46: /* G72 */ | |
324 | case 0x4a: | |
325 | case 0x4c: /* G7x-based C51 */ | |
326 | case 0x4e: | |
327 | nv_wr32(dev, 0x400860, 0); | |
328 | nv_wr32(dev, 0x400864, 0); | |
329 | break; | |
330 | case 0x47: /* G70 */ | |
331 | case 0x49: /* G71 */ | |
332 | case 0x4b: /* G73 */ | |
333 | nv_wr32(dev, 0x400828, 0x07830610); | |
334 | nv_wr32(dev, 0x40082c, 0x0000016A); | |
335 | break; | |
336 | default: | |
337 | break; | |
338 | } | |
339 | ||
340 | nv_wr32(dev, 0x400b38, 0x2ffff800); | |
341 | nv_wr32(dev, 0x400b3c, 0x00006000); | |
342 | ||
2295e17a FJ |
343 | /* Tiling related stuff. */ |
344 | switch (dev_priv->chipset) { | |
345 | case 0x44: | |
346 | case 0x4a: | |
347 | nv_wr32(dev, 0x400bc4, 0x1003d888); | |
348 | nv_wr32(dev, 0x400bbc, 0xb7a7b500); | |
349 | break; | |
350 | case 0x46: | |
351 | nv_wr32(dev, 0x400bc4, 0x0000e024); | |
352 | nv_wr32(dev, 0x400bbc, 0xb7a7b520); | |
353 | break; | |
354 | case 0x4c: | |
355 | case 0x4e: | |
356 | case 0x67: | |
357 | nv_wr32(dev, 0x400bc4, 0x1003d888); | |
358 | nv_wr32(dev, 0x400bbc, 0xb7a7b540); | |
359 | break; | |
360 | default: | |
361 | break; | |
362 | } | |
363 | ||
0d87c100 FJ |
364 | /* Turn all the tiling regions off. */ |
365 | for (i = 0; i < pfb->num_tiles; i++) | |
366 | nv40_graph_set_region_tiling(dev, i, 0, 0, 0); | |
6ee73861 BS |
367 | |
368 | /* begin RAM config */ | |
01d73a69 | 369 | vramsz = pci_resource_len(dev->pdev, 0) - 1; |
6ee73861 BS |
370 | switch (dev_priv->chipset) { |
371 | case 0x40: | |
372 | nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0)); | |
373 | nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1)); | |
374 | nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0)); | |
375 | nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1)); | |
376 | nv_wr32(dev, 0x400820, 0); | |
377 | nv_wr32(dev, 0x400824, 0); | |
378 | nv_wr32(dev, 0x400864, vramsz); | |
379 | nv_wr32(dev, 0x400868, vramsz); | |
380 | break; | |
381 | default: | |
382 | switch (dev_priv->chipset) { | |
383 | case 0x46: | |
384 | case 0x47: | |
385 | case 0x49: | |
386 | case 0x4b: | |
387 | nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0)); | |
388 | nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1)); | |
389 | break; | |
390 | default: | |
391 | nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0)); | |
392 | nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1)); | |
393 | break; | |
394 | } | |
395 | nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0)); | |
396 | nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1)); | |
397 | nv_wr32(dev, 0x400840, 0); | |
398 | nv_wr32(dev, 0x400844, 0); | |
399 | nv_wr32(dev, 0x4008A0, vramsz); | |
400 | nv_wr32(dev, 0x4008A4, vramsz); | |
401 | break; | |
402 | } | |
403 | ||
404 | return 0; | |
405 | } | |
406 | ||
407 | void nv40_graph_takedown(struct drm_device *dev) | |
408 | { | |
409 | } | |
410 | ||
411 | struct nouveau_pgraph_object_class nv40_graph_grclass[] = { | |
412 | { 0x0030, false, NULL }, /* null */ | |
413 | { 0x0039, false, NULL }, /* m2mf */ | |
414 | { 0x004a, false, NULL }, /* gdirect */ | |
415 | { 0x009f, false, NULL }, /* imageblit (nv12) */ | |
416 | { 0x008a, false, NULL }, /* ifc */ | |
417 | { 0x0089, false, NULL }, /* sifm */ | |
418 | { 0x3089, false, NULL }, /* sifm (nv40) */ | |
419 | { 0x0062, false, NULL }, /* surf2d */ | |
420 | { 0x3062, false, NULL }, /* surf2d (nv40) */ | |
421 | { 0x0043, false, NULL }, /* rop */ | |
422 | { 0x0012, false, NULL }, /* beta1 */ | |
423 | { 0x0072, false, NULL }, /* beta4 */ | |
424 | { 0x0019, false, NULL }, /* cliprect */ | |
425 | { 0x0044, false, NULL }, /* pattern */ | |
426 | { 0x309e, false, NULL }, /* swzsurf */ | |
427 | { 0x4097, false, NULL }, /* curie (nv40) */ | |
428 | { 0x4497, false, NULL }, /* curie (nv44) */ | |
429 | {} | |
430 | }; | |
431 |