Commit | Line | Data |
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e225f446 | 1 | /* |
26f6d88b BS |
2 | * Copyright 2011 Red Hat Inc. |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
51beb428 | 25 | #include <linux/dma-mapping.h> |
83fc083c | 26 | |
760285e7 DH |
27 | #include <drm/drmP.h> |
28 | #include <drm/drm_crtc_helper.h> | |
26f6d88b | 29 | |
77145f1c BS |
30 | #include "nouveau_drm.h" |
31 | #include "nouveau_dma.h" | |
32 | #include "nouveau_gem.h" | |
26f6d88b BS |
33 | #include "nouveau_connector.h" |
34 | #include "nouveau_encoder.h" | |
35 | #include "nouveau_crtc.h" | |
f589be88 | 36 | #include "nouveau_fence.h" |
3a89cd02 | 37 | #include "nv50_display.h" |
26f6d88b | 38 | |
b5a794b0 | 39 | #include <core/client.h> |
77145f1c | 40 | #include <core/gpuobj.h> |
b5a794b0 | 41 | #include <core/class.h> |
77145f1c BS |
42 | |
43 | #include <subdev/timer.h> | |
44 | #include <subdev/bar.h> | |
45 | #include <subdev/fb.h> | |
5ed50209 | 46 | #include <subdev/i2c.h> |
77145f1c | 47 | |
8a46438a BS |
48 | #define EVO_DMA_NR 9 |
49 | ||
bdb8c212 | 50 | #define EVO_MASTER (0x00) |
a63a97eb | 51 | #define EVO_FLIP(c) (0x01 + (c)) |
8a46438a BS |
52 | #define EVO_OVLY(c) (0x05 + (c)) |
53 | #define EVO_OIMM(c) (0x09 + (c)) | |
bdb8c212 BS |
54 | #define EVO_CURS(c) (0x0d + (c)) |
55 | ||
816af2f2 BS |
56 | /* offsets in shared sync bo of various structures */ |
57 | #define EVO_SYNC(c, o) ((c) * 0x0100 + (o)) | |
9f9bdaaf BS |
58 | #define EVO_MAST_NTFY EVO_SYNC( 0, 0x00) |
59 | #define EVO_FLIP_SEM0(c) EVO_SYNC((c) + 1, 0x00) | |
60 | #define EVO_FLIP_SEM1(c) EVO_SYNC((c) + 1, 0x10) | |
816af2f2 | 61 | |
b5a794b0 BS |
62 | #define EVO_CORE_HANDLE (0xd1500000) |
63 | #define EVO_CHAN_HANDLE(t,i) (0xd15c0000 | (((t) & 0x00ff) << 8) | (i)) | |
64 | #define EVO_CHAN_OCLASS(t,c) ((nv_hclass(c) & 0xff00) | ((t) & 0x00ff)) | |
65 | #define EVO_PUSH_HANDLE(t,i) (0xd15b0000 | (i) | \ | |
66 | (((NV50_DISP_##t##_CLASS) & 0x00ff) << 8)) | |
67 | ||
68 | /****************************************************************************** | |
69 | * EVO channel | |
70 | *****************************************************************************/ | |
71 | ||
e225f446 | 72 | struct nv50_chan { |
b5a794b0 BS |
73 | struct nouveau_object *user; |
74 | u32 handle; | |
75 | }; | |
76 | ||
77 | static int | |
e225f446 BS |
78 | nv50_chan_create(struct nouveau_object *core, u32 bclass, u8 head, |
79 | void *data, u32 size, struct nv50_chan *chan) | |
b5a794b0 BS |
80 | { |
81 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
82 | const u32 oclass = EVO_CHAN_OCLASS(bclass, core); | |
83 | const u32 handle = EVO_CHAN_HANDLE(bclass, head); | |
84 | int ret; | |
85 | ||
86 | ret = nouveau_object_new(client, EVO_CORE_HANDLE, handle, | |
87 | oclass, data, size, &chan->user); | |
88 | if (ret) | |
89 | return ret; | |
90 | ||
91 | chan->handle = handle; | |
92 | return 0; | |
93 | } | |
94 | ||
95 | static void | |
e225f446 | 96 | nv50_chan_destroy(struct nouveau_object *core, struct nv50_chan *chan) |
b5a794b0 BS |
97 | { |
98 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
99 | if (chan->handle) | |
100 | nouveau_object_del(client, EVO_CORE_HANDLE, chan->handle); | |
101 | } | |
102 | ||
103 | /****************************************************************************** | |
104 | * PIO EVO channel | |
105 | *****************************************************************************/ | |
106 | ||
e225f446 BS |
107 | struct nv50_pioc { |
108 | struct nv50_chan base; | |
b5a794b0 BS |
109 | }; |
110 | ||
111 | static void | |
e225f446 | 112 | nv50_pioc_destroy(struct nouveau_object *core, struct nv50_pioc *pioc) |
b5a794b0 | 113 | { |
e225f446 | 114 | nv50_chan_destroy(core, &pioc->base); |
b5a794b0 BS |
115 | } |
116 | ||
117 | static int | |
e225f446 BS |
118 | nv50_pioc_create(struct nouveau_object *core, u32 bclass, u8 head, |
119 | void *data, u32 size, struct nv50_pioc *pioc) | |
b5a794b0 | 120 | { |
e225f446 | 121 | return nv50_chan_create(core, bclass, head, data, size, &pioc->base); |
b5a794b0 BS |
122 | } |
123 | ||
124 | /****************************************************************************** | |
125 | * DMA EVO channel | |
126 | *****************************************************************************/ | |
127 | ||
e225f446 BS |
128 | struct nv50_dmac { |
129 | struct nv50_chan base; | |
3376ee37 BS |
130 | dma_addr_t handle; |
131 | u32 *ptr; | |
59ad1465 DV |
132 | |
133 | /* Protects against concurrent pushbuf access to this channel, lock is | |
134 | * grabbed by evo_wait (if the pushbuf reservation is successful) and | |
135 | * dropped again by evo_kick. */ | |
136 | struct mutex lock; | |
b5a794b0 BS |
137 | }; |
138 | ||
139 | static void | |
e225f446 | 140 | nv50_dmac_destroy(struct nouveau_object *core, struct nv50_dmac *dmac) |
b5a794b0 BS |
141 | { |
142 | if (dmac->ptr) { | |
143 | struct pci_dev *pdev = nv_device(core)->pdev; | |
144 | pci_free_consistent(pdev, PAGE_SIZE, dmac->ptr, dmac->handle); | |
145 | } | |
146 | ||
e225f446 | 147 | nv50_chan_destroy(core, &dmac->base); |
b5a794b0 BS |
148 | } |
149 | ||
150 | static int | |
47057302 | 151 | nv50_dmac_create_fbdma(struct nouveau_object *core, u32 parent) |
b5a794b0 BS |
152 | { |
153 | struct nouveau_fb *pfb = nouveau_fb(core); | |
154 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
155 | struct nouveau_object *object; | |
47057302 BS |
156 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, |
157 | NV_DMA_IN_MEMORY_CLASS, | |
158 | &(struct nv_dma_class) { | |
159 | .flags = NV_DMA_TARGET_VRAM | | |
160 | NV_DMA_ACCESS_RDWR, | |
161 | .start = 0, | |
dceef5d8 | 162 | .limit = pfb->ram->size - 1, |
47057302 BS |
163 | .conf0 = NV50_DMA_CONF0_ENABLE | |
164 | NV50_DMA_CONF0_PART_256, | |
165 | }, sizeof(struct nv_dma_class), &object); | |
166 | if (ret) | |
167 | return ret; | |
b5a794b0 | 168 | |
47057302 BS |
169 | ret = nouveau_object_new(client, parent, NvEvoFB16, |
170 | NV_DMA_IN_MEMORY_CLASS, | |
b5a794b0 | 171 | &(struct nv_dma_class) { |
47057302 BS |
172 | .flags = NV_DMA_TARGET_VRAM | |
173 | NV_DMA_ACCESS_RDWR, | |
174 | .start = 0, | |
dceef5d8 | 175 | .limit = pfb->ram->size - 1, |
47057302 BS |
176 | .conf0 = NV50_DMA_CONF0_ENABLE | 0x70 | |
177 | NV50_DMA_CONF0_PART_256, | |
b5a794b0 BS |
178 | }, sizeof(struct nv_dma_class), &object); |
179 | if (ret) | |
180 | return ret; | |
181 | ||
47057302 BS |
182 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
183 | NV_DMA_IN_MEMORY_CLASS, | |
184 | &(struct nv_dma_class) { | |
185 | .flags = NV_DMA_TARGET_VRAM | | |
186 | NV_DMA_ACCESS_RDWR, | |
187 | .start = 0, | |
dceef5d8 | 188 | .limit = pfb->ram->size - 1, |
47057302 BS |
189 | .conf0 = NV50_DMA_CONF0_ENABLE | 0x7a | |
190 | NV50_DMA_CONF0_PART_256, | |
191 | }, sizeof(struct nv_dma_class), &object); | |
192 | return ret; | |
193 | } | |
194 | ||
195 | static int | |
196 | nvc0_dmac_create_fbdma(struct nouveau_object *core, u32 parent) | |
197 | { | |
198 | struct nouveau_fb *pfb = nouveau_fb(core); | |
199 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
200 | struct nouveau_object *object; | |
201 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, | |
202 | NV_DMA_IN_MEMORY_CLASS, | |
203 | &(struct nv_dma_class) { | |
204 | .flags = NV_DMA_TARGET_VRAM | | |
205 | NV_DMA_ACCESS_RDWR, | |
206 | .start = 0, | |
dceef5d8 | 207 | .limit = pfb->ram->size - 1, |
47057302 BS |
208 | .conf0 = NVC0_DMA_CONF0_ENABLE, |
209 | }, sizeof(struct nv_dma_class), &object); | |
b5a794b0 BS |
210 | if (ret) |
211 | return ret; | |
212 | ||
47057302 | 213 | ret = nouveau_object_new(client, parent, NvEvoFB16, |
b5a794b0 BS |
214 | NV_DMA_IN_MEMORY_CLASS, |
215 | &(struct nv_dma_class) { | |
216 | .flags = NV_DMA_TARGET_VRAM | | |
217 | NV_DMA_ACCESS_RDWR, | |
47057302 | 218 | .start = 0, |
dceef5d8 | 219 | .limit = pfb->ram->size - 1, |
47057302 | 220 | .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe, |
b5a794b0 BS |
221 | }, sizeof(struct nv_dma_class), &object); |
222 | if (ret) | |
47057302 | 223 | return ret; |
b5a794b0 | 224 | |
47057302 | 225 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
b5a794b0 BS |
226 | NV_DMA_IN_MEMORY_CLASS, |
227 | &(struct nv_dma_class) { | |
228 | .flags = NV_DMA_TARGET_VRAM | | |
229 | NV_DMA_ACCESS_RDWR, | |
230 | .start = 0, | |
dceef5d8 | 231 | .limit = pfb->ram->size - 1, |
47057302 | 232 | .conf0 = NVC0_DMA_CONF0_ENABLE | 0xfe, |
b5a794b0 | 233 | }, sizeof(struct nv_dma_class), &object); |
47057302 BS |
234 | return ret; |
235 | } | |
236 | ||
237 | static int | |
238 | nvd0_dmac_create_fbdma(struct nouveau_object *core, u32 parent) | |
239 | { | |
240 | struct nouveau_fb *pfb = nouveau_fb(core); | |
241 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
242 | struct nouveau_object *object; | |
243 | int ret = nouveau_object_new(client, parent, NvEvoVRAM_LP, | |
244 | NV_DMA_IN_MEMORY_CLASS, | |
245 | &(struct nv_dma_class) { | |
246 | .flags = NV_DMA_TARGET_VRAM | | |
247 | NV_DMA_ACCESS_RDWR, | |
248 | .start = 0, | |
dceef5d8 | 249 | .limit = pfb->ram->size - 1, |
47057302 BS |
250 | .conf0 = NVD0_DMA_CONF0_ENABLE | |
251 | NVD0_DMA_CONF0_PAGE_LP, | |
252 | }, sizeof(struct nv_dma_class), &object); | |
b5a794b0 | 253 | if (ret) |
47057302 | 254 | return ret; |
b5a794b0 | 255 | |
47057302 | 256 | ret = nouveau_object_new(client, parent, NvEvoFB32, |
b5a794b0 BS |
257 | NV_DMA_IN_MEMORY_CLASS, |
258 | &(struct nv_dma_class) { | |
259 | .flags = NV_DMA_TARGET_VRAM | | |
260 | NV_DMA_ACCESS_RDWR, | |
261 | .start = 0, | |
dceef5d8 | 262 | .limit = pfb->ram->size - 1, |
47057302 | 263 | .conf0 = NVD0_DMA_CONF0_ENABLE | 0xfe | |
b5a794b0 BS |
264 | NVD0_DMA_CONF0_PAGE_LP, |
265 | }, sizeof(struct nv_dma_class), &object); | |
47057302 BS |
266 | return ret; |
267 | } | |
268 | ||
269 | static int | |
e225f446 | 270 | nv50_dmac_create(struct nouveau_object *core, u32 bclass, u8 head, |
47057302 | 271 | void *data, u32 size, u64 syncbuf, |
e225f446 | 272 | struct nv50_dmac *dmac) |
47057302 BS |
273 | { |
274 | struct nouveau_fb *pfb = nouveau_fb(core); | |
275 | struct nouveau_object *client = nv_pclass(core, NV_CLIENT_CLASS); | |
276 | struct nouveau_object *object; | |
277 | u32 pushbuf = *(u32 *)data; | |
278 | int ret; | |
279 | ||
59ad1465 DV |
280 | mutex_init(&dmac->lock); |
281 | ||
47057302 BS |
282 | dmac->ptr = pci_alloc_consistent(nv_device(core)->pdev, PAGE_SIZE, |
283 | &dmac->handle); | |
284 | if (!dmac->ptr) | |
285 | return -ENOMEM; | |
286 | ||
287 | ret = nouveau_object_new(client, NVDRM_DEVICE, pushbuf, | |
288 | NV_DMA_FROM_MEMORY_CLASS, | |
289 | &(struct nv_dma_class) { | |
290 | .flags = NV_DMA_TARGET_PCI_US | | |
291 | NV_DMA_ACCESS_RD, | |
292 | .start = dmac->handle + 0x0000, | |
293 | .limit = dmac->handle + 0x0fff, | |
294 | }, sizeof(struct nv_dma_class), &object); | |
b5a794b0 | 295 | if (ret) |
47057302 | 296 | return ret; |
b5a794b0 | 297 | |
e225f446 | 298 | ret = nv50_chan_create(core, bclass, head, data, size, &dmac->base); |
47057302 BS |
299 | if (ret) |
300 | return ret; | |
301 | ||
302 | ret = nouveau_object_new(client, dmac->base.handle, NvEvoSync, | |
303 | NV_DMA_IN_MEMORY_CLASS, | |
304 | &(struct nv_dma_class) { | |
305 | .flags = NV_DMA_TARGET_VRAM | | |
306 | NV_DMA_ACCESS_RDWR, | |
307 | .start = syncbuf + 0x0000, | |
308 | .limit = syncbuf + 0x0fff, | |
309 | }, sizeof(struct nv_dma_class), &object); | |
310 | if (ret) | |
311 | return ret; | |
312 | ||
313 | ret = nouveau_object_new(client, dmac->base.handle, NvEvoVRAM, | |
b5a794b0 BS |
314 | NV_DMA_IN_MEMORY_CLASS, |
315 | &(struct nv_dma_class) { | |
316 | .flags = NV_DMA_TARGET_VRAM | | |
317 | NV_DMA_ACCESS_RDWR, | |
318 | .start = 0, | |
dceef5d8 | 319 | .limit = pfb->ram->size - 1, |
b5a794b0 | 320 | }, sizeof(struct nv_dma_class), &object); |
b5a794b0 | 321 | if (ret) |
47057302 BS |
322 | return ret; |
323 | ||
324 | if (nv_device(core)->card_type < NV_C0) | |
325 | ret = nv50_dmac_create_fbdma(core, dmac->base.handle); | |
326 | else | |
327 | if (nv_device(core)->card_type < NV_D0) | |
328 | ret = nvc0_dmac_create_fbdma(core, dmac->base.handle); | |
329 | else | |
330 | ret = nvd0_dmac_create_fbdma(core, dmac->base.handle); | |
b5a794b0 BS |
331 | return ret; |
332 | } | |
333 | ||
e225f446 BS |
334 | struct nv50_mast { |
335 | struct nv50_dmac base; | |
b5a794b0 BS |
336 | }; |
337 | ||
e225f446 BS |
338 | struct nv50_curs { |
339 | struct nv50_pioc base; | |
b5a794b0 BS |
340 | }; |
341 | ||
e225f446 BS |
342 | struct nv50_sync { |
343 | struct nv50_dmac base; | |
9f9bdaaf BS |
344 | u32 addr; |
345 | u32 data; | |
3376ee37 BS |
346 | }; |
347 | ||
e225f446 BS |
348 | struct nv50_ovly { |
349 | struct nv50_dmac base; | |
b5a794b0 | 350 | }; |
f20ce962 | 351 | |
e225f446 BS |
352 | struct nv50_oimm { |
353 | struct nv50_pioc base; | |
26f6d88b BS |
354 | }; |
355 | ||
e225f446 | 356 | struct nv50_head { |
dd0e3d53 | 357 | struct nouveau_crtc base; |
8dda53fc | 358 | struct nouveau_bo *image; |
e225f446 BS |
359 | struct nv50_curs curs; |
360 | struct nv50_sync sync; | |
361 | struct nv50_ovly ovly; | |
362 | struct nv50_oimm oimm; | |
b5a794b0 BS |
363 | }; |
364 | ||
e225f446 BS |
365 | #define nv50_head(c) ((struct nv50_head *)nouveau_crtc(c)) |
366 | #define nv50_curs(c) (&nv50_head(c)->curs) | |
367 | #define nv50_sync(c) (&nv50_head(c)->sync) | |
368 | #define nv50_ovly(c) (&nv50_head(c)->ovly) | |
369 | #define nv50_oimm(c) (&nv50_head(c)->oimm) | |
370 | #define nv50_chan(c) (&(c)->base.base) | |
371 | #define nv50_vers(c) nv_mclass(nv50_chan(c)->user) | |
b5a794b0 | 372 | |
e225f446 | 373 | struct nv50_disp { |
b5a794b0 | 374 | struct nouveau_object *core; |
e225f446 | 375 | struct nv50_mast mast; |
b5a794b0 | 376 | |
b5a794b0 BS |
377 | u32 modeset; |
378 | ||
379 | struct nouveau_bo *sync; | |
dd0e3d53 BS |
380 | }; |
381 | ||
e225f446 BS |
382 | static struct nv50_disp * |
383 | nv50_disp(struct drm_device *dev) | |
26f6d88b | 384 | { |
77145f1c | 385 | return nouveau_display(dev)->priv; |
26f6d88b BS |
386 | } |
387 | ||
e225f446 | 388 | #define nv50_mast(d) (&nv50_disp(d)->mast) |
b5a794b0 | 389 | |
bdb8c212 | 390 | static struct drm_crtc * |
e225f446 | 391 | nv50_display_crtc_get(struct drm_encoder *encoder) |
bdb8c212 BS |
392 | { |
393 | return nouveau_encoder(encoder)->crtc; | |
394 | } | |
395 | ||
396 | /****************************************************************************** | |
397 | * EVO channel helpers | |
398 | *****************************************************************************/ | |
51beb428 | 399 | static u32 * |
b5a794b0 | 400 | evo_wait(void *evoc, int nr) |
51beb428 | 401 | { |
e225f446 | 402 | struct nv50_dmac *dmac = evoc; |
b5a794b0 | 403 | u32 put = nv_ro32(dmac->base.user, 0x0000) / 4; |
51beb428 | 404 | |
59ad1465 | 405 | mutex_lock(&dmac->lock); |
de8268c5 | 406 | if (put + nr >= (PAGE_SIZE / 4) - 8) { |
b5a794b0 | 407 | dmac->ptr[put] = 0x20000000; |
51beb428 | 408 | |
b5a794b0 BS |
409 | nv_wo32(dmac->base.user, 0x0000, 0x00000000); |
410 | if (!nv_wait(dmac->base.user, 0x0004, ~0, 0x00000000)) { | |
59ad1465 | 411 | mutex_unlock(&dmac->lock); |
b5a794b0 | 412 | NV_ERROR(dmac->base.user, "channel stalled\n"); |
51beb428 BS |
413 | return NULL; |
414 | } | |
415 | ||
416 | put = 0; | |
417 | } | |
418 | ||
b5a794b0 | 419 | return dmac->ptr + put; |
51beb428 BS |
420 | } |
421 | ||
422 | static void | |
b5a794b0 | 423 | evo_kick(u32 *push, void *evoc) |
51beb428 | 424 | { |
e225f446 | 425 | struct nv50_dmac *dmac = evoc; |
b5a794b0 | 426 | nv_wo32(dmac->base.user, 0x0000, (push - dmac->ptr) << 2); |
59ad1465 | 427 | mutex_unlock(&dmac->lock); |
51beb428 BS |
428 | } |
429 | ||
430 | #define evo_mthd(p,m,s) *((p)++) = (((s) << 18) | (m)) | |
431 | #define evo_data(p,d) *((p)++) = (d) | |
432 | ||
3376ee37 BS |
433 | static bool |
434 | evo_sync_wait(void *data) | |
435 | { | |
5cc027f6 BS |
436 | if (nouveau_bo_rd32(data, EVO_MAST_NTFY) != 0x00000000) |
437 | return true; | |
438 | usleep_range(1, 2); | |
439 | return false; | |
3376ee37 BS |
440 | } |
441 | ||
442 | static int | |
b5a794b0 | 443 | evo_sync(struct drm_device *dev) |
3376ee37 | 444 | { |
77145f1c | 445 | struct nouveau_device *device = nouveau_dev(dev); |
e225f446 BS |
446 | struct nv50_disp *disp = nv50_disp(dev); |
447 | struct nv50_mast *mast = nv50_mast(dev); | |
b5a794b0 | 448 | u32 *push = evo_wait(mast, 8); |
3376ee37 | 449 | if (push) { |
816af2f2 | 450 | nouveau_bo_wr32(disp->sync, EVO_MAST_NTFY, 0x00000000); |
3376ee37 | 451 | evo_mthd(push, 0x0084, 1); |
816af2f2 | 452 | evo_data(push, 0x80000000 | EVO_MAST_NTFY); |
3376ee37 BS |
453 | evo_mthd(push, 0x0080, 2); |
454 | evo_data(push, 0x00000000); | |
455 | evo_data(push, 0x00000000); | |
b5a794b0 | 456 | evo_kick(push, mast); |
77145f1c | 457 | if (nv_wait_cb(device, evo_sync_wait, disp->sync)) |
3376ee37 BS |
458 | return 0; |
459 | } | |
460 | ||
461 | return -EBUSY; | |
462 | } | |
463 | ||
464 | /****************************************************************************** | |
a63a97eb | 465 | * Page flipping channel |
3376ee37 BS |
466 | *****************************************************************************/ |
467 | struct nouveau_bo * | |
e225f446 | 468 | nv50_display_crtc_sema(struct drm_device *dev, int crtc) |
3376ee37 | 469 | { |
e225f446 | 470 | return nv50_disp(dev)->sync; |
3376ee37 BS |
471 | } |
472 | ||
9f9bdaaf BS |
473 | struct nv50_display_flip { |
474 | struct nv50_disp *disp; | |
475 | struct nv50_sync *chan; | |
476 | }; | |
477 | ||
478 | static bool | |
479 | nv50_display_flip_wait(void *data) | |
480 | { | |
481 | struct nv50_display_flip *flip = data; | |
482 | if (nouveau_bo_rd32(flip->disp->sync, flip->chan->addr / 4) == | |
b1ea3e6e | 483 | flip->chan->data) |
9f9bdaaf BS |
484 | return true; |
485 | usleep_range(1, 2); | |
486 | return false; | |
487 | } | |
488 | ||
3376ee37 | 489 | void |
e225f446 | 490 | nv50_display_flip_stop(struct drm_crtc *crtc) |
3376ee37 | 491 | { |
9f9bdaaf BS |
492 | struct nouveau_device *device = nouveau_dev(crtc->dev); |
493 | struct nv50_display_flip flip = { | |
494 | .disp = nv50_disp(crtc->dev), | |
495 | .chan = nv50_sync(crtc), | |
496 | }; | |
3376ee37 BS |
497 | u32 *push; |
498 | ||
9f9bdaaf | 499 | push = evo_wait(flip.chan, 8); |
3376ee37 BS |
500 | if (push) { |
501 | evo_mthd(push, 0x0084, 1); | |
502 | evo_data(push, 0x00000000); | |
503 | evo_mthd(push, 0x0094, 1); | |
504 | evo_data(push, 0x00000000); | |
505 | evo_mthd(push, 0x00c0, 1); | |
506 | evo_data(push, 0x00000000); | |
507 | evo_mthd(push, 0x0080, 1); | |
508 | evo_data(push, 0x00000000); | |
9f9bdaaf | 509 | evo_kick(push, flip.chan); |
3376ee37 | 510 | } |
9f9bdaaf BS |
511 | |
512 | nv_wait_cb(device, nv50_display_flip_wait, &flip); | |
3376ee37 BS |
513 | } |
514 | ||
515 | int | |
e225f446 | 516 | nv50_display_flip_next(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
3376ee37 BS |
517 | struct nouveau_channel *chan, u32 swap_interval) |
518 | { | |
519 | struct nouveau_framebuffer *nv_fb = nouveau_framebuffer(fb); | |
3376ee37 | 520 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
8dda53fc | 521 | struct nv50_head *head = nv50_head(crtc); |
e225f446 | 522 | struct nv50_sync *sync = nv50_sync(crtc); |
3376ee37 | 523 | u32 *push; |
8dda53fc | 524 | int ret; |
3376ee37 BS |
525 | |
526 | swap_interval <<= 4; | |
527 | if (swap_interval == 0) | |
528 | swap_interval |= 0x100; | |
f60b6e7a BS |
529 | if (chan == NULL) |
530 | evo_sync(crtc->dev); | |
3376ee37 | 531 | |
b5a794b0 | 532 | push = evo_wait(sync, 128); |
3376ee37 BS |
533 | if (unlikely(push == NULL)) |
534 | return -EBUSY; | |
535 | ||
9f9bdaaf BS |
536 | if (chan && nv_mclass(chan->object) < NV84_CHANNEL_IND_CLASS) { |
537 | ret = RING_SPACE(chan, 8); | |
538 | if (ret) | |
539 | return ret; | |
540 | ||
541 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 2); | |
8dda53fc | 542 | OUT_RING (chan, NvEvoSema0 + nv_crtc->index); |
9f9bdaaf BS |
543 | OUT_RING (chan, sync->addr ^ 0x10); |
544 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_RELEASE, 1); | |
545 | OUT_RING (chan, sync->data + 1); | |
546 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_SEMAPHORE_OFFSET, 2); | |
547 | OUT_RING (chan, sync->addr); | |
548 | OUT_RING (chan, sync->data); | |
549 | } else | |
550 | if (chan && nv_mclass(chan->object) < NVC0_CHANNEL_IND_CLASS) { | |
8dda53fc | 551 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
9f9bdaaf BS |
552 | ret = RING_SPACE(chan, 12); |
553 | if (ret) | |
554 | return ret; | |
555 | ||
556 | BEGIN_NV04(chan, 0, NV11_SUBCHAN_DMA_SEMAPHORE, 1); | |
557 | OUT_RING (chan, chan->vram); | |
558 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
559 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
560 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
561 | OUT_RING (chan, sync->data + 1); | |
562 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG); | |
563 | BEGIN_NV04(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
564 | OUT_RING (chan, upper_32_bits(addr)); | |
565 | OUT_RING (chan, lower_32_bits(addr)); | |
566 | OUT_RING (chan, sync->data); | |
567 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL); | |
568 | } else | |
569 | if (chan) { | |
8dda53fc | 570 | u64 addr = nv84_fence_crtc(chan, nv_crtc->index) + sync->addr; |
9f9bdaaf BS |
571 | ret = RING_SPACE(chan, 10); |
572 | if (ret) | |
573 | return ret; | |
574 | ||
575 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
576 | OUT_RING (chan, upper_32_bits(addr ^ 0x10)); | |
577 | OUT_RING (chan, lower_32_bits(addr ^ 0x10)); | |
578 | OUT_RING (chan, sync->data + 1); | |
579 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG | | |
580 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
581 | BEGIN_NVC0(chan, 0, NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH, 4); | |
582 | OUT_RING (chan, upper_32_bits(addr)); | |
583 | OUT_RING (chan, lower_32_bits(addr)); | |
584 | OUT_RING (chan, sync->data); | |
585 | OUT_RING (chan, NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL | | |
586 | NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD); | |
587 | } | |
35bcf5d5 | 588 | |
9f9bdaaf BS |
589 | if (chan) { |
590 | sync->addr ^= 0x10; | |
591 | sync->data++; | |
3376ee37 | 592 | FIRE_RING (chan); |
3376ee37 BS |
593 | } |
594 | ||
595 | /* queue the flip */ | |
596 | evo_mthd(push, 0x0100, 1); | |
597 | evo_data(push, 0xfffe0000); | |
598 | evo_mthd(push, 0x0084, 1); | |
599 | evo_data(push, swap_interval); | |
600 | if (!(swap_interval & 0x00000100)) { | |
601 | evo_mthd(push, 0x00e0, 1); | |
602 | evo_data(push, 0x40000000); | |
603 | } | |
604 | evo_mthd(push, 0x0088, 4); | |
9f9bdaaf BS |
605 | evo_data(push, sync->addr); |
606 | evo_data(push, sync->data++); | |
607 | evo_data(push, sync->data); | |
3376ee37 BS |
608 | evo_data(push, NvEvoSync); |
609 | evo_mthd(push, 0x00a0, 2); | |
610 | evo_data(push, 0x00000000); | |
611 | evo_data(push, 0x00000000); | |
612 | evo_mthd(push, 0x00c0, 1); | |
613 | evo_data(push, nv_fb->r_dma); | |
614 | evo_mthd(push, 0x0110, 2); | |
615 | evo_data(push, 0x00000000); | |
616 | evo_data(push, 0x00000000); | |
e225f446 | 617 | if (nv50_vers(sync) < NVD0_DISP_SYNC_CLASS) { |
ed5085a5 BS |
618 | evo_mthd(push, 0x0800, 5); |
619 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
620 | evo_data(push, 0); | |
621 | evo_data(push, (fb->height << 16) | fb->width); | |
622 | evo_data(push, nv_fb->r_pitch); | |
623 | evo_data(push, nv_fb->r_format); | |
624 | } else { | |
625 | evo_mthd(push, 0x0400, 5); | |
626 | evo_data(push, nv_fb->nvbo->bo.offset >> 8); | |
627 | evo_data(push, 0); | |
628 | evo_data(push, (fb->height << 16) | fb->width); | |
629 | evo_data(push, nv_fb->r_pitch); | |
630 | evo_data(push, nv_fb->r_format); | |
631 | } | |
3376ee37 BS |
632 | evo_mthd(push, 0x0080, 1); |
633 | evo_data(push, 0x00000000); | |
b5a794b0 | 634 | evo_kick(push, sync); |
8dda53fc BS |
635 | |
636 | nouveau_bo_ref(nv_fb->nvbo, &head->image); | |
3376ee37 BS |
637 | return 0; |
638 | } | |
639 | ||
438d99e3 BS |
640 | /****************************************************************************** |
641 | * CRTC | |
642 | *****************************************************************************/ | |
643 | static int | |
e225f446 | 644 | nv50_crtc_set_dither(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 645 | { |
e225f446 | 646 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de691855 BS |
647 | struct nouveau_connector *nv_connector; |
648 | struct drm_connector *connector; | |
649 | u32 *push, mode = 0x00; | |
438d99e3 | 650 | |
488ff207 | 651 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
de691855 BS |
652 | connector = &nv_connector->base; |
653 | if (nv_connector->dithering_mode == DITHERING_MODE_AUTO) { | |
654 | if (nv_crtc->base.fb->depth > connector->display_info.bpc * 3) | |
655 | mode = DITHERING_MODE_DYNAMIC2X2; | |
656 | } else { | |
657 | mode = nv_connector->dithering_mode; | |
658 | } | |
659 | ||
660 | if (nv_connector->dithering_depth == DITHERING_DEPTH_AUTO) { | |
661 | if (connector->display_info.bpc >= 8) | |
662 | mode |= DITHERING_DEPTH_8BPC; | |
663 | } else { | |
664 | mode |= nv_connector->dithering_depth; | |
438d99e3 BS |
665 | } |
666 | ||
de8268c5 | 667 | push = evo_wait(mast, 4); |
438d99e3 | 668 | if (push) { |
e225f446 | 669 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
670 | evo_mthd(push, 0x08a0 + (nv_crtc->index * 0x0400), 1); |
671 | evo_data(push, mode); | |
672 | } else | |
e225f446 | 673 | if (nv50_vers(mast) < NVE0_DISP_MAST_CLASS) { |
de8268c5 BS |
674 | evo_mthd(push, 0x0490 + (nv_crtc->index * 0x0300), 1); |
675 | evo_data(push, mode); | |
676 | } else { | |
677 | evo_mthd(push, 0x04a0 + (nv_crtc->index * 0x0300), 1); | |
678 | evo_data(push, mode); | |
679 | } | |
680 | ||
438d99e3 BS |
681 | if (update) { |
682 | evo_mthd(push, 0x0080, 1); | |
683 | evo_data(push, 0x00000000); | |
684 | } | |
de8268c5 | 685 | evo_kick(push, mast); |
438d99e3 BS |
686 | } |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | static int | |
e225f446 | 692 | nv50_crtc_set_scale(struct nouveau_crtc *nv_crtc, bool update) |
438d99e3 | 693 | { |
e225f446 | 694 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
92854622 | 695 | struct drm_display_mode *omode, *umode = &nv_crtc->base.mode; |
3376ee37 | 696 | struct drm_crtc *crtc = &nv_crtc->base; |
f3fdc52d | 697 | struct nouveau_connector *nv_connector; |
92854622 BS |
698 | int mode = DRM_MODE_SCALE_NONE; |
699 | u32 oX, oY, *push; | |
f3fdc52d | 700 | |
92854622 BS |
701 | /* start off at the resolution we programmed the crtc for, this |
702 | * effectively handles NONE/FULL scaling | |
703 | */ | |
f3fdc52d | 704 | nv_connector = nouveau_crtc_connector_get(nv_crtc); |
92854622 BS |
705 | if (nv_connector && nv_connector->native_mode) |
706 | mode = nv_connector->scaling_mode; | |
707 | ||
708 | if (mode != DRM_MODE_SCALE_NONE) | |
709 | omode = nv_connector->native_mode; | |
710 | else | |
711 | omode = umode; | |
712 | ||
713 | oX = omode->hdisplay; | |
714 | oY = omode->vdisplay; | |
715 | if (omode->flags & DRM_MODE_FLAG_DBLSCAN) | |
716 | oY *= 2; | |
717 | ||
718 | /* add overscan compensation if necessary, will keep the aspect | |
719 | * ratio the same as the backend mode unless overridden by the | |
720 | * user setting both hborder and vborder properties. | |
721 | */ | |
722 | if (nv_connector && ( nv_connector->underscan == UNDERSCAN_ON || | |
723 | (nv_connector->underscan == UNDERSCAN_AUTO && | |
724 | nv_connector->edid && | |
725 | drm_detect_hdmi_monitor(nv_connector->edid)))) { | |
726 | u32 bX = nv_connector->underscan_hborder; | |
727 | u32 bY = nv_connector->underscan_vborder; | |
728 | u32 aspect = (oY << 19) / oX; | |
729 | ||
730 | if (bX) { | |
731 | oX -= (bX * 2); | |
732 | if (bY) oY -= (bY * 2); | |
733 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
734 | } else { | |
735 | oX -= (oX >> 4) + 32; | |
736 | if (bY) oY -= (bY * 2); | |
737 | else oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
738 | } | |
739 | } | |
740 | ||
741 | /* handle CENTER/ASPECT scaling, taking into account the areas | |
742 | * removed already for overscan compensation | |
743 | */ | |
744 | switch (mode) { | |
745 | case DRM_MODE_SCALE_CENTER: | |
746 | oX = min((u32)umode->hdisplay, oX); | |
747 | oY = min((u32)umode->vdisplay, oY); | |
748 | /* fall-through */ | |
749 | case DRM_MODE_SCALE_ASPECT: | |
750 | if (oY < oX) { | |
751 | u32 aspect = (umode->hdisplay << 19) / umode->vdisplay; | |
752 | oX = ((oY * aspect) + (aspect / 2)) >> 19; | |
753 | } else { | |
754 | u32 aspect = (umode->vdisplay << 19) / umode->hdisplay; | |
755 | oY = ((oX * aspect) + (aspect / 2)) >> 19; | |
f3fdc52d | 756 | } |
92854622 BS |
757 | break; |
758 | default: | |
759 | break; | |
f3fdc52d | 760 | } |
438d99e3 | 761 | |
de8268c5 | 762 | push = evo_wait(mast, 8); |
438d99e3 | 763 | if (push) { |
e225f446 | 764 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
765 | /*XXX: SCALE_CTRL_ACTIVE??? */ |
766 | evo_mthd(push, 0x08d8 + (nv_crtc->index * 0x400), 2); | |
767 | evo_data(push, (oY << 16) | oX); | |
768 | evo_data(push, (oY << 16) | oX); | |
769 | evo_mthd(push, 0x08a4 + (nv_crtc->index * 0x400), 1); | |
770 | evo_data(push, 0x00000000); | |
771 | evo_mthd(push, 0x08c8 + (nv_crtc->index * 0x400), 1); | |
772 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
773 | } else { | |
774 | evo_mthd(push, 0x04c0 + (nv_crtc->index * 0x300), 3); | |
775 | evo_data(push, (oY << 16) | oX); | |
776 | evo_data(push, (oY << 16) | oX); | |
777 | evo_data(push, (oY << 16) | oX); | |
778 | evo_mthd(push, 0x0494 + (nv_crtc->index * 0x300), 1); | |
779 | evo_data(push, 0x00000000); | |
780 | evo_mthd(push, 0x04b8 + (nv_crtc->index * 0x300), 1); | |
781 | evo_data(push, umode->vdisplay << 16 | umode->hdisplay); | |
782 | } | |
783 | ||
784 | evo_kick(push, mast); | |
785 | ||
438d99e3 | 786 | if (update) { |
e225f446 BS |
787 | nv50_display_flip_stop(crtc); |
788 | nv50_display_flip_next(crtc, crtc->fb, NULL, 1); | |
438d99e3 | 789 | } |
438d99e3 BS |
790 | } |
791 | ||
792 | return 0; | |
793 | } | |
794 | ||
f9887d09 | 795 | static int |
e225f446 | 796 | nv50_crtc_set_color_vibrance(struct nouveau_crtc *nv_crtc, bool update) |
f9887d09 | 797 | { |
e225f446 | 798 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
f9887d09 BS |
799 | u32 *push, hue, vib; |
800 | int adj; | |
801 | ||
802 | adj = (nv_crtc->color_vibrance > 0) ? 50 : 0; | |
803 | vib = ((nv_crtc->color_vibrance * 2047 + adj) / 100) & 0xfff; | |
804 | hue = ((nv_crtc->vibrant_hue * 2047) / 100) & 0xfff; | |
805 | ||
806 | push = evo_wait(mast, 16); | |
807 | if (push) { | |
e225f446 | 808 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
f9887d09 BS |
809 | evo_mthd(push, 0x08a8 + (nv_crtc->index * 0x400), 1); |
810 | evo_data(push, (hue << 20) | (vib << 8)); | |
811 | } else { | |
812 | evo_mthd(push, 0x0498 + (nv_crtc->index * 0x300), 1); | |
813 | evo_data(push, (hue << 20) | (vib << 8)); | |
814 | } | |
815 | ||
816 | if (update) { | |
817 | evo_mthd(push, 0x0080, 1); | |
818 | evo_data(push, 0x00000000); | |
819 | } | |
820 | evo_kick(push, mast); | |
821 | } | |
822 | ||
823 | return 0; | |
824 | } | |
825 | ||
438d99e3 | 826 | static int |
e225f446 | 827 | nv50_crtc_set_image(struct nouveau_crtc *nv_crtc, struct drm_framebuffer *fb, |
438d99e3 BS |
828 | int x, int y, bool update) |
829 | { | |
830 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(fb); | |
e225f446 | 831 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
438d99e3 BS |
832 | u32 *push; |
833 | ||
de8268c5 | 834 | push = evo_wait(mast, 16); |
438d99e3 | 835 | if (push) { |
e225f446 | 836 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
837 | evo_mthd(push, 0x0860 + (nv_crtc->index * 0x400), 1); |
838 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
839 | evo_mthd(push, 0x0868 + (nv_crtc->index * 0x400), 3); | |
840 | evo_data(push, (fb->height << 16) | fb->width); | |
841 | evo_data(push, nvfb->r_pitch); | |
842 | evo_data(push, nvfb->r_format); | |
843 | evo_mthd(push, 0x08c0 + (nv_crtc->index * 0x400), 1); | |
844 | evo_data(push, (y << 16) | x); | |
e225f446 | 845 | if (nv50_vers(mast) > NV50_DISP_MAST_CLASS) { |
de8268c5 BS |
846 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
847 | evo_data(push, nvfb->r_dma); | |
848 | } | |
849 | } else { | |
850 | evo_mthd(push, 0x0460 + (nv_crtc->index * 0x300), 1); | |
851 | evo_data(push, nvfb->nvbo->bo.offset >> 8); | |
852 | evo_mthd(push, 0x0468 + (nv_crtc->index * 0x300), 4); | |
853 | evo_data(push, (fb->height << 16) | fb->width); | |
854 | evo_data(push, nvfb->r_pitch); | |
855 | evo_data(push, nvfb->r_format); | |
856 | evo_data(push, nvfb->r_dma); | |
857 | evo_mthd(push, 0x04b0 + (nv_crtc->index * 0x300), 1); | |
858 | evo_data(push, (y << 16) | x); | |
859 | } | |
860 | ||
a46232ee BS |
861 | if (update) { |
862 | evo_mthd(push, 0x0080, 1); | |
863 | evo_data(push, 0x00000000); | |
864 | } | |
de8268c5 | 865 | evo_kick(push, mast); |
438d99e3 BS |
866 | } |
867 | ||
c0cc92a1 | 868 | nv_crtc->fb.tile_flags = nvfb->r_dma; |
438d99e3 BS |
869 | return 0; |
870 | } | |
871 | ||
872 | static void | |
e225f446 | 873 | nv50_crtc_cursor_show(struct nouveau_crtc *nv_crtc) |
438d99e3 | 874 | { |
e225f446 | 875 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 | 876 | u32 *push = evo_wait(mast, 16); |
438d99e3 | 877 | if (push) { |
e225f446 | 878 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
de8268c5 BS |
879 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
880 | evo_data(push, 0x85000000); | |
881 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
882 | } else | |
e225f446 | 883 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
884 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 2); |
885 | evo_data(push, 0x85000000); | |
886 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
887 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); | |
888 | evo_data(push, NvEvoVRAM); | |
889 | } else { | |
438d99e3 BS |
890 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 2); |
891 | evo_data(push, 0x85000000); | |
892 | evo_data(push, nv_crtc->cursor.nvbo->bo.offset >> 8); | |
893 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
37b034a6 | 894 | evo_data(push, NvEvoVRAM); |
de8268c5 BS |
895 | } |
896 | evo_kick(push, mast); | |
897 | } | |
898 | } | |
899 | ||
900 | static void | |
e225f446 | 901 | nv50_crtc_cursor_hide(struct nouveau_crtc *nv_crtc) |
de8268c5 | 902 | { |
e225f446 | 903 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 BS |
904 | u32 *push = evo_wait(mast, 16); |
905 | if (push) { | |
e225f446 | 906 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
de8268c5 BS |
907 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
908 | evo_data(push, 0x05000000); | |
909 | } else | |
e225f446 | 910 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
911 | evo_mthd(push, 0x0880 + (nv_crtc->index * 0x400), 1); |
912 | evo_data(push, 0x05000000); | |
913 | evo_mthd(push, 0x089c + (nv_crtc->index * 0x400), 1); | |
914 | evo_data(push, 0x00000000); | |
438d99e3 BS |
915 | } else { |
916 | evo_mthd(push, 0x0480 + (nv_crtc->index * 0x300), 1); | |
917 | evo_data(push, 0x05000000); | |
918 | evo_mthd(push, 0x048c + (nv_crtc->index * 0x300), 1); | |
919 | evo_data(push, 0x00000000); | |
920 | } | |
de8268c5 BS |
921 | evo_kick(push, mast); |
922 | } | |
923 | } | |
438d99e3 | 924 | |
de8268c5 | 925 | static void |
e225f446 | 926 | nv50_crtc_cursor_show_hide(struct nouveau_crtc *nv_crtc, bool show, bool update) |
de8268c5 | 927 | { |
e225f446 | 928 | struct nv50_mast *mast = nv50_mast(nv_crtc->base.dev); |
de8268c5 BS |
929 | |
930 | if (show) | |
e225f446 | 931 | nv50_crtc_cursor_show(nv_crtc); |
de8268c5 | 932 | else |
e225f446 | 933 | nv50_crtc_cursor_hide(nv_crtc); |
de8268c5 BS |
934 | |
935 | if (update) { | |
936 | u32 *push = evo_wait(mast, 2); | |
937 | if (push) { | |
438d99e3 BS |
938 | evo_mthd(push, 0x0080, 1); |
939 | evo_data(push, 0x00000000); | |
de8268c5 | 940 | evo_kick(push, mast); |
438d99e3 | 941 | } |
438d99e3 BS |
942 | } |
943 | } | |
944 | ||
945 | static void | |
e225f446 | 946 | nv50_crtc_dpms(struct drm_crtc *crtc, int mode) |
438d99e3 BS |
947 | { |
948 | } | |
949 | ||
950 | static void | |
e225f446 | 951 | nv50_crtc_prepare(struct drm_crtc *crtc) |
438d99e3 BS |
952 | { |
953 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 954 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
955 | u32 *push; |
956 | ||
e225f446 | 957 | nv50_display_flip_stop(crtc); |
3376ee37 | 958 | |
de8268c5 | 959 | push = evo_wait(mast, 2); |
438d99e3 | 960 | if (push) { |
e225f446 | 961 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
de8268c5 BS |
962 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
963 | evo_data(push, 0x00000000); | |
964 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
965 | evo_data(push, 0x40000000); | |
966 | } else | |
e225f446 | 967 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
968 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
969 | evo_data(push, 0x00000000); | |
970 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 1); | |
971 | evo_data(push, 0x40000000); | |
972 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
973 | evo_data(push, 0x00000000); | |
974 | } else { | |
975 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
976 | evo_data(push, 0x00000000); | |
977 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 1); | |
978 | evo_data(push, 0x03000000); | |
979 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
980 | evo_data(push, 0x00000000); | |
981 | } | |
982 | ||
983 | evo_kick(push, mast); | |
438d99e3 BS |
984 | } |
985 | ||
e225f446 | 986 | nv50_crtc_cursor_show_hide(nv_crtc, false, false); |
438d99e3 BS |
987 | } |
988 | ||
989 | static void | |
e225f446 | 990 | nv50_crtc_commit(struct drm_crtc *crtc) |
438d99e3 BS |
991 | { |
992 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 | 993 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
994 | u32 *push; |
995 | ||
de8268c5 | 996 | push = evo_wait(mast, 32); |
438d99e3 | 997 | if (push) { |
e225f446 | 998 | if (nv50_vers(mast) < NV84_DISP_MAST_CLASS) { |
de8268c5 BS |
999 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1000 | evo_data(push, NvEvoVRAM_LP); | |
1001 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); | |
1002 | evo_data(push, 0xc0000000); | |
1003 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1004 | } else | |
e225f446 | 1005 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
1006 | evo_mthd(push, 0x0874 + (nv_crtc->index * 0x400), 1); |
1007 | evo_data(push, nv_crtc->fb.tile_flags); | |
1008 | evo_mthd(push, 0x0840 + (nv_crtc->index * 0x400), 2); | |
1009 | evo_data(push, 0xc0000000); | |
1010 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1011 | evo_mthd(push, 0x085c + (nv_crtc->index * 0x400), 1); | |
1012 | evo_data(push, NvEvoVRAM); | |
1013 | } else { | |
1014 | evo_mthd(push, 0x0474 + (nv_crtc->index * 0x300), 1); | |
1015 | evo_data(push, nv_crtc->fb.tile_flags); | |
1016 | evo_mthd(push, 0x0440 + (nv_crtc->index * 0x300), 4); | |
1017 | evo_data(push, 0x83000000); | |
1018 | evo_data(push, nv_crtc->lut.nvbo->bo.offset >> 8); | |
1019 | evo_data(push, 0x00000000); | |
1020 | evo_data(push, 0x00000000); | |
1021 | evo_mthd(push, 0x045c + (nv_crtc->index * 0x300), 1); | |
1022 | evo_data(push, NvEvoVRAM); | |
1023 | evo_mthd(push, 0x0430 + (nv_crtc->index * 0x300), 1); | |
1024 | evo_data(push, 0xffffff00); | |
1025 | } | |
1026 | ||
1027 | evo_kick(push, mast); | |
438d99e3 BS |
1028 | } |
1029 | ||
e225f446 BS |
1030 | nv50_crtc_cursor_show_hide(nv_crtc, nv_crtc->cursor.visible, true); |
1031 | nv50_display_flip_next(crtc, crtc->fb, NULL, 1); | |
438d99e3 BS |
1032 | } |
1033 | ||
1034 | static bool | |
e225f446 | 1035 | nv50_crtc_mode_fixup(struct drm_crtc *crtc, const struct drm_display_mode *mode, |
438d99e3 BS |
1036 | struct drm_display_mode *adjusted_mode) |
1037 | { | |
eb2e9686 | 1038 | drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V); |
438d99e3 BS |
1039 | return true; |
1040 | } | |
1041 | ||
1042 | static int | |
e225f446 | 1043 | nv50_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) |
438d99e3 BS |
1044 | { |
1045 | struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->fb); | |
8dda53fc | 1046 | struct nv50_head *head = nv50_head(crtc); |
438d99e3 BS |
1047 | int ret; |
1048 | ||
1049 | ret = nouveau_bo_pin(nvfb->nvbo, TTM_PL_FLAG_VRAM); | |
8dda53fc BS |
1050 | if (ret == 0) { |
1051 | if (head->image) | |
1052 | nouveau_bo_unpin(head->image); | |
1053 | nouveau_bo_ref(nvfb->nvbo, &head->image); | |
438d99e3 BS |
1054 | } |
1055 | ||
8dda53fc | 1056 | return ret; |
438d99e3 BS |
1057 | } |
1058 | ||
1059 | static int | |
e225f446 | 1060 | nv50_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *umode, |
438d99e3 BS |
1061 | struct drm_display_mode *mode, int x, int y, |
1062 | struct drm_framebuffer *old_fb) | |
1063 | { | |
e225f446 | 1064 | struct nv50_mast *mast = nv50_mast(crtc->dev); |
438d99e3 BS |
1065 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1066 | struct nouveau_connector *nv_connector; | |
2d1d898b BS |
1067 | u32 ilace = (mode->flags & DRM_MODE_FLAG_INTERLACE) ? 2 : 1; |
1068 | u32 vscan = (mode->flags & DRM_MODE_FLAG_DBLSCAN) ? 2 : 1; | |
1069 | u32 hactive, hsynce, hbackp, hfrontp, hblanke, hblanks; | |
1070 | u32 vactive, vsynce, vbackp, vfrontp, vblanke, vblanks; | |
1071 | u32 vblan2e = 0, vblan2s = 1; | |
3488c57b | 1072 | u32 *push; |
438d99e3 BS |
1073 | int ret; |
1074 | ||
2d1d898b BS |
1075 | hactive = mode->htotal; |
1076 | hsynce = mode->hsync_end - mode->hsync_start - 1; | |
1077 | hbackp = mode->htotal - mode->hsync_end; | |
1078 | hblanke = hsynce + hbackp; | |
1079 | hfrontp = mode->hsync_start - mode->hdisplay; | |
1080 | hblanks = mode->htotal - hfrontp - 1; | |
1081 | ||
1082 | vactive = mode->vtotal * vscan / ilace; | |
1083 | vsynce = ((mode->vsync_end - mode->vsync_start) * vscan / ilace) - 1; | |
1084 | vbackp = (mode->vtotal - mode->vsync_end) * vscan / ilace; | |
1085 | vblanke = vsynce + vbackp; | |
1086 | vfrontp = (mode->vsync_start - mode->vdisplay) * vscan / ilace; | |
1087 | vblanks = vactive - vfrontp - 1; | |
1088 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
1089 | vblan2e = vactive + vsynce + vbackp; | |
1090 | vblan2s = vblan2e + (mode->vdisplay * vscan / ilace); | |
1091 | vactive = (vactive * 2) + 1; | |
2d1d898b BS |
1092 | } |
1093 | ||
e225f446 | 1094 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1095 | if (ret) |
1096 | return ret; | |
1097 | ||
de8268c5 | 1098 | push = evo_wait(mast, 64); |
438d99e3 | 1099 | if (push) { |
e225f446 | 1100 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
de8268c5 BS |
1101 | evo_mthd(push, 0x0804 + (nv_crtc->index * 0x400), 2); |
1102 | evo_data(push, 0x00800000 | mode->clock); | |
1103 | evo_data(push, (ilace == 2) ? 2 : 0); | |
1104 | evo_mthd(push, 0x0810 + (nv_crtc->index * 0x400), 6); | |
1105 | evo_data(push, 0x00000000); | |
1106 | evo_data(push, (vactive << 16) | hactive); | |
1107 | evo_data(push, ( vsynce << 16) | hsynce); | |
1108 | evo_data(push, (vblanke << 16) | hblanke); | |
1109 | evo_data(push, (vblanks << 16) | hblanks); | |
1110 | evo_data(push, (vblan2e << 16) | vblan2s); | |
1111 | evo_mthd(push, 0x082c + (nv_crtc->index * 0x400), 1); | |
1112 | evo_data(push, 0x00000000); | |
1113 | evo_mthd(push, 0x0900 + (nv_crtc->index * 0x400), 2); | |
1114 | evo_data(push, 0x00000311); | |
1115 | evo_data(push, 0x00000100); | |
1116 | } else { | |
1117 | evo_mthd(push, 0x0410 + (nv_crtc->index * 0x300), 6); | |
1118 | evo_data(push, 0x00000000); | |
1119 | evo_data(push, (vactive << 16) | hactive); | |
1120 | evo_data(push, ( vsynce << 16) | hsynce); | |
1121 | evo_data(push, (vblanke << 16) | hblanke); | |
1122 | evo_data(push, (vblanks << 16) | hblanks); | |
1123 | evo_data(push, (vblan2e << 16) | vblan2s); | |
1124 | evo_mthd(push, 0x042c + (nv_crtc->index * 0x300), 1); | |
1125 | evo_data(push, 0x00000000); /* ??? */ | |
1126 | evo_mthd(push, 0x0450 + (nv_crtc->index * 0x300), 3); | |
1127 | evo_data(push, mode->clock * 1000); | |
1128 | evo_data(push, 0x00200000); /* ??? */ | |
1129 | evo_data(push, mode->clock * 1000); | |
1130 | evo_mthd(push, 0x04d0 + (nv_crtc->index * 0x300), 2); | |
1131 | evo_data(push, 0x00000311); | |
1132 | evo_data(push, 0x00000100); | |
1133 | } | |
1134 | ||
1135 | evo_kick(push, mast); | |
438d99e3 BS |
1136 | } |
1137 | ||
1138 | nv_connector = nouveau_crtc_connector_get(nv_crtc); | |
e225f446 BS |
1139 | nv50_crtc_set_dither(nv_crtc, false); |
1140 | nv50_crtc_set_scale(nv_crtc, false); | |
1141 | nv50_crtc_set_color_vibrance(nv_crtc, false); | |
1142 | nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, false); | |
438d99e3 BS |
1143 | return 0; |
1144 | } | |
1145 | ||
1146 | static int | |
e225f446 | 1147 | nv50_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, |
438d99e3 BS |
1148 | struct drm_framebuffer *old_fb) |
1149 | { | |
77145f1c | 1150 | struct nouveau_drm *drm = nouveau_drm(crtc->dev); |
438d99e3 BS |
1151 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1152 | int ret; | |
1153 | ||
84e2ad8b | 1154 | if (!crtc->fb) { |
77145f1c | 1155 | NV_DEBUG(drm, "No FB bound\n"); |
84e2ad8b BS |
1156 | return 0; |
1157 | } | |
1158 | ||
e225f446 | 1159 | ret = nv50_crtc_swap_fbs(crtc, old_fb); |
438d99e3 BS |
1160 | if (ret) |
1161 | return ret; | |
1162 | ||
e225f446 BS |
1163 | nv50_display_flip_stop(crtc); |
1164 | nv50_crtc_set_image(nv_crtc, crtc->fb, x, y, true); | |
1165 | nv50_display_flip_next(crtc, crtc->fb, NULL, 1); | |
438d99e3 BS |
1166 | return 0; |
1167 | } | |
1168 | ||
1169 | static int | |
e225f446 | 1170 | nv50_crtc_mode_set_base_atomic(struct drm_crtc *crtc, |
438d99e3 BS |
1171 | struct drm_framebuffer *fb, int x, int y, |
1172 | enum mode_set_atomic state) | |
1173 | { | |
1174 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1175 | nv50_display_flip_stop(crtc); |
1176 | nv50_crtc_set_image(nv_crtc, fb, x, y, true); | |
438d99e3 BS |
1177 | return 0; |
1178 | } | |
1179 | ||
1180 | static void | |
e225f446 | 1181 | nv50_crtc_lut_load(struct drm_crtc *crtc) |
438d99e3 | 1182 | { |
e225f446 | 1183 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
438d99e3 BS |
1184 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); |
1185 | void __iomem *lut = nvbo_kmap_obj_iovirtual(nv_crtc->lut.nvbo); | |
1186 | int i; | |
1187 | ||
1188 | for (i = 0; i < 256; i++) { | |
de8268c5 BS |
1189 | u16 r = nv_crtc->lut.r[i] >> 2; |
1190 | u16 g = nv_crtc->lut.g[i] >> 2; | |
1191 | u16 b = nv_crtc->lut.b[i] >> 2; | |
1192 | ||
1193 | if (nv_mclass(disp->core) < NVD0_DISP_CLASS) { | |
1194 | writew(r + 0x0000, lut + (i * 0x08) + 0); | |
1195 | writew(g + 0x0000, lut + (i * 0x08) + 2); | |
1196 | writew(b + 0x0000, lut + (i * 0x08) + 4); | |
1197 | } else { | |
1198 | writew(r + 0x6000, lut + (i * 0x20) + 0); | |
1199 | writew(g + 0x6000, lut + (i * 0x20) + 2); | |
1200 | writew(b + 0x6000, lut + (i * 0x20) + 4); | |
1201 | } | |
438d99e3 BS |
1202 | } |
1203 | } | |
1204 | ||
8dda53fc BS |
1205 | static void |
1206 | nv50_crtc_disable(struct drm_crtc *crtc) | |
1207 | { | |
1208 | struct nv50_head *head = nv50_head(crtc); | |
1209 | if (head->image) | |
1210 | nouveau_bo_unpin(head->image); | |
1211 | nouveau_bo_ref(NULL, &head->image); | |
1212 | } | |
1213 | ||
438d99e3 | 1214 | static int |
e225f446 | 1215 | nv50_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, |
438d99e3 BS |
1216 | uint32_t handle, uint32_t width, uint32_t height) |
1217 | { | |
1218 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
1219 | struct drm_device *dev = crtc->dev; | |
1220 | struct drm_gem_object *gem; | |
1221 | struct nouveau_bo *nvbo; | |
1222 | bool visible = (handle != 0); | |
1223 | int i, ret = 0; | |
1224 | ||
1225 | if (visible) { | |
1226 | if (width != 64 || height != 64) | |
1227 | return -EINVAL; | |
1228 | ||
1229 | gem = drm_gem_object_lookup(dev, file_priv, handle); | |
1230 | if (unlikely(!gem)) | |
1231 | return -ENOENT; | |
1232 | nvbo = nouveau_gem_object(gem); | |
1233 | ||
1234 | ret = nouveau_bo_map(nvbo); | |
1235 | if (ret == 0) { | |
1236 | for (i = 0; i < 64 * 64; i++) { | |
1237 | u32 v = nouveau_bo_rd32(nvbo, i); | |
1238 | nouveau_bo_wr32(nv_crtc->cursor.nvbo, i, v); | |
1239 | } | |
1240 | nouveau_bo_unmap(nvbo); | |
1241 | } | |
1242 | ||
1243 | drm_gem_object_unreference_unlocked(gem); | |
1244 | } | |
1245 | ||
1246 | if (visible != nv_crtc->cursor.visible) { | |
e225f446 | 1247 | nv50_crtc_cursor_show_hide(nv_crtc, visible, true); |
438d99e3 BS |
1248 | nv_crtc->cursor.visible = visible; |
1249 | } | |
1250 | ||
1251 | return ret; | |
1252 | } | |
1253 | ||
1254 | static int | |
e225f446 | 1255 | nv50_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) |
438d99e3 | 1256 | { |
e225f446 BS |
1257 | struct nv50_curs *curs = nv50_curs(crtc); |
1258 | struct nv50_chan *chan = nv50_chan(curs); | |
b5a794b0 BS |
1259 | nv_wo32(chan->user, 0x0084, (y << 16) | (x & 0xffff)); |
1260 | nv_wo32(chan->user, 0x0080, 0x00000000); | |
438d99e3 BS |
1261 | return 0; |
1262 | } | |
1263 | ||
1264 | static void | |
e225f446 | 1265 | nv50_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, |
438d99e3 BS |
1266 | uint32_t start, uint32_t size) |
1267 | { | |
1268 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
bdefc8cb | 1269 | u32 end = min_t(u32, start + size, 256); |
438d99e3 BS |
1270 | u32 i; |
1271 | ||
1272 | for (i = start; i < end; i++) { | |
1273 | nv_crtc->lut.r[i] = r[i]; | |
1274 | nv_crtc->lut.g[i] = g[i]; | |
1275 | nv_crtc->lut.b[i] = b[i]; | |
1276 | } | |
1277 | ||
e225f446 | 1278 | nv50_crtc_lut_load(crtc); |
438d99e3 BS |
1279 | } |
1280 | ||
1281 | static void | |
e225f446 | 1282 | nv50_crtc_destroy(struct drm_crtc *crtc) |
438d99e3 BS |
1283 | { |
1284 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
e225f446 BS |
1285 | struct nv50_disp *disp = nv50_disp(crtc->dev); |
1286 | struct nv50_head *head = nv50_head(crtc); | |
8dda53fc | 1287 | |
e225f446 BS |
1288 | nv50_dmac_destroy(disp->core, &head->ovly.base); |
1289 | nv50_pioc_destroy(disp->core, &head->oimm.base); | |
1290 | nv50_dmac_destroy(disp->core, &head->sync.base); | |
1291 | nv50_pioc_destroy(disp->core, &head->curs.base); | |
8dda53fc BS |
1292 | |
1293 | /*XXX: this shouldn't be necessary, but the core doesn't call | |
1294 | * disconnect() during the cleanup paths | |
1295 | */ | |
1296 | if (head->image) | |
1297 | nouveau_bo_unpin(head->image); | |
1298 | nouveau_bo_ref(NULL, &head->image); | |
1299 | ||
438d99e3 | 1300 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); |
04c8c210 MS |
1301 | if (nv_crtc->cursor.nvbo) |
1302 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); | |
438d99e3 | 1303 | nouveau_bo_ref(NULL, &nv_crtc->cursor.nvbo); |
8dda53fc | 1304 | |
438d99e3 | 1305 | nouveau_bo_unmap(nv_crtc->lut.nvbo); |
04c8c210 MS |
1306 | if (nv_crtc->lut.nvbo) |
1307 | nouveau_bo_unpin(nv_crtc->lut.nvbo); | |
438d99e3 | 1308 | nouveau_bo_ref(NULL, &nv_crtc->lut.nvbo); |
8dda53fc | 1309 | |
438d99e3 BS |
1310 | drm_crtc_cleanup(crtc); |
1311 | kfree(crtc); | |
1312 | } | |
1313 | ||
e225f446 BS |
1314 | static const struct drm_crtc_helper_funcs nv50_crtc_hfunc = { |
1315 | .dpms = nv50_crtc_dpms, | |
1316 | .prepare = nv50_crtc_prepare, | |
1317 | .commit = nv50_crtc_commit, | |
1318 | .mode_fixup = nv50_crtc_mode_fixup, | |
1319 | .mode_set = nv50_crtc_mode_set, | |
1320 | .mode_set_base = nv50_crtc_mode_set_base, | |
1321 | .mode_set_base_atomic = nv50_crtc_mode_set_base_atomic, | |
1322 | .load_lut = nv50_crtc_lut_load, | |
8dda53fc | 1323 | .disable = nv50_crtc_disable, |
438d99e3 BS |
1324 | }; |
1325 | ||
e225f446 BS |
1326 | static const struct drm_crtc_funcs nv50_crtc_func = { |
1327 | .cursor_set = nv50_crtc_cursor_set, | |
1328 | .cursor_move = nv50_crtc_cursor_move, | |
1329 | .gamma_set = nv50_crtc_gamma_set, | |
5addcf0a | 1330 | .set_config = nouveau_crtc_set_config, |
e225f446 | 1331 | .destroy = nv50_crtc_destroy, |
3376ee37 | 1332 | .page_flip = nouveau_crtc_page_flip, |
438d99e3 BS |
1333 | }; |
1334 | ||
c20ab3e1 | 1335 | static void |
e225f446 | 1336 | nv50_cursor_set_pos(struct nouveau_crtc *nv_crtc, int x, int y) |
c20ab3e1 BS |
1337 | { |
1338 | } | |
1339 | ||
1340 | static void | |
e225f446 | 1341 | nv50_cursor_set_offset(struct nouveau_crtc *nv_crtc, uint32_t offset) |
c20ab3e1 BS |
1342 | { |
1343 | } | |
1344 | ||
438d99e3 | 1345 | static int |
e225f446 | 1346 | nv50_crtc_create(struct drm_device *dev, struct nouveau_object *core, int index) |
438d99e3 | 1347 | { |
e225f446 BS |
1348 | struct nv50_disp *disp = nv50_disp(dev); |
1349 | struct nv50_head *head; | |
438d99e3 BS |
1350 | struct drm_crtc *crtc; |
1351 | int ret, i; | |
1352 | ||
dd0e3d53 BS |
1353 | head = kzalloc(sizeof(*head), GFP_KERNEL); |
1354 | if (!head) | |
438d99e3 BS |
1355 | return -ENOMEM; |
1356 | ||
dd0e3d53 | 1357 | head->base.index = index; |
e225f446 BS |
1358 | head->base.set_dither = nv50_crtc_set_dither; |
1359 | head->base.set_scale = nv50_crtc_set_scale; | |
1360 | head->base.set_color_vibrance = nv50_crtc_set_color_vibrance; | |
f9887d09 BS |
1361 | head->base.color_vibrance = 50; |
1362 | head->base.vibrant_hue = 0; | |
e225f446 BS |
1363 | head->base.cursor.set_offset = nv50_cursor_set_offset; |
1364 | head->base.cursor.set_pos = nv50_cursor_set_pos; | |
438d99e3 | 1365 | for (i = 0; i < 256; i++) { |
dd0e3d53 BS |
1366 | head->base.lut.r[i] = i << 8; |
1367 | head->base.lut.g[i] = i << 8; | |
1368 | head->base.lut.b[i] = i << 8; | |
438d99e3 BS |
1369 | } |
1370 | ||
dd0e3d53 | 1371 | crtc = &head->base.base; |
e225f446 BS |
1372 | drm_crtc_init(dev, crtc, &nv50_crtc_func); |
1373 | drm_crtc_helper_add(crtc, &nv50_crtc_hfunc); | |
438d99e3 BS |
1374 | drm_mode_crtc_set_gamma_size(crtc, 256); |
1375 | ||
b5a794b0 BS |
1376 | ret = nouveau_bo_new(dev, 8192, 0x100, TTM_PL_FLAG_VRAM, |
1377 | 0, 0x0000, NULL, &head->base.lut.nvbo); | |
1378 | if (!ret) { | |
1379 | ret = nouveau_bo_pin(head->base.lut.nvbo, TTM_PL_FLAG_VRAM); | |
04c8c210 | 1380 | if (!ret) { |
b5a794b0 | 1381 | ret = nouveau_bo_map(head->base.lut.nvbo); |
04c8c210 MS |
1382 | if (ret) |
1383 | nouveau_bo_unpin(head->base.lut.nvbo); | |
1384 | } | |
b5a794b0 BS |
1385 | if (ret) |
1386 | nouveau_bo_ref(NULL, &head->base.lut.nvbo); | |
1387 | } | |
1388 | ||
1389 | if (ret) | |
1390 | goto out; | |
1391 | ||
e225f446 | 1392 | nv50_crtc_lut_load(crtc); |
b5a794b0 BS |
1393 | |
1394 | /* allocate cursor resources */ | |
e225f446 | 1395 | ret = nv50_pioc_create(disp->core, NV50_DISP_CURS_CLASS, index, |
b5a794b0 BS |
1396 | &(struct nv50_display_curs_class) { |
1397 | .head = index, | |
1398 | }, sizeof(struct nv50_display_curs_class), | |
1399 | &head->curs.base); | |
1400 | if (ret) | |
1401 | goto out; | |
1402 | ||
438d99e3 | 1403 | ret = nouveau_bo_new(dev, 64 * 64 * 4, 0x100, TTM_PL_FLAG_VRAM, |
dd0e3d53 | 1404 | 0, 0x0000, NULL, &head->base.cursor.nvbo); |
438d99e3 | 1405 | if (!ret) { |
dd0e3d53 | 1406 | ret = nouveau_bo_pin(head->base.cursor.nvbo, TTM_PL_FLAG_VRAM); |
04c8c210 | 1407 | if (!ret) { |
dd0e3d53 | 1408 | ret = nouveau_bo_map(head->base.cursor.nvbo); |
04c8c210 MS |
1409 | if (ret) |
1410 | nouveau_bo_unpin(head->base.lut.nvbo); | |
1411 | } | |
438d99e3 | 1412 | if (ret) |
dd0e3d53 | 1413 | nouveau_bo_ref(NULL, &head->base.cursor.nvbo); |
438d99e3 BS |
1414 | } |
1415 | ||
1416 | if (ret) | |
1417 | goto out; | |
1418 | ||
b5a794b0 | 1419 | /* allocate page flip / sync resources */ |
e225f446 | 1420 | ret = nv50_dmac_create(disp->core, NV50_DISP_SYNC_CLASS, index, |
b5a794b0 BS |
1421 | &(struct nv50_display_sync_class) { |
1422 | .pushbuf = EVO_PUSH_HANDLE(SYNC, index), | |
1423 | .head = index, | |
1424 | }, sizeof(struct nv50_display_sync_class), | |
1425 | disp->sync->bo.offset, &head->sync.base); | |
1426 | if (ret) | |
1427 | goto out; | |
1428 | ||
9f9bdaaf BS |
1429 | head->sync.addr = EVO_FLIP_SEM0(index); |
1430 | head->sync.data = 0x00000000; | |
438d99e3 | 1431 | |
b5a794b0 | 1432 | /* allocate overlay resources */ |
e225f446 | 1433 | ret = nv50_pioc_create(disp->core, NV50_DISP_OIMM_CLASS, index, |
b5a794b0 BS |
1434 | &(struct nv50_display_oimm_class) { |
1435 | .head = index, | |
1436 | }, sizeof(struct nv50_display_oimm_class), | |
1437 | &head->oimm.base); | |
438d99e3 BS |
1438 | if (ret) |
1439 | goto out; | |
1440 | ||
e225f446 | 1441 | ret = nv50_dmac_create(disp->core, NV50_DISP_OVLY_CLASS, index, |
b5a794b0 BS |
1442 | &(struct nv50_display_ovly_class) { |
1443 | .pushbuf = EVO_PUSH_HANDLE(OVLY, index), | |
1444 | .head = index, | |
1445 | }, sizeof(struct nv50_display_ovly_class), | |
1446 | disp->sync->bo.offset, &head->ovly.base); | |
1447 | if (ret) | |
1448 | goto out; | |
438d99e3 BS |
1449 | |
1450 | out: | |
1451 | if (ret) | |
e225f446 | 1452 | nv50_crtc_destroy(crtc); |
438d99e3 BS |
1453 | return ret; |
1454 | } | |
1455 | ||
26f6d88b BS |
1456 | /****************************************************************************** |
1457 | * DAC | |
1458 | *****************************************************************************/ | |
8eaa9669 | 1459 | static void |
e225f446 | 1460 | nv50_dac_dpms(struct drm_encoder *encoder, int mode) |
8eaa9669 BS |
1461 | { |
1462 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1463 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
8eaa9669 BS |
1464 | int or = nv_encoder->or; |
1465 | u32 dpms_ctrl; | |
1466 | ||
35b21d39 | 1467 | dpms_ctrl = 0x00000000; |
8eaa9669 BS |
1468 | if (mode == DRM_MODE_DPMS_STANDBY || mode == DRM_MODE_DPMS_OFF) |
1469 | dpms_ctrl |= 0x00000001; | |
1470 | if (mode == DRM_MODE_DPMS_SUSPEND || mode == DRM_MODE_DPMS_OFF) | |
1471 | dpms_ctrl |= 0x00000004; | |
1472 | ||
35b21d39 | 1473 | nv_call(disp->core, NV50_DISP_DAC_PWR + or, dpms_ctrl); |
8eaa9669 BS |
1474 | } |
1475 | ||
1476 | static bool | |
e225f446 | 1477 | nv50_dac_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 1478 | const struct drm_display_mode *mode, |
8eaa9669 BS |
1479 | struct drm_display_mode *adjusted_mode) |
1480 | { | |
1481 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1482 | struct nouveau_connector *nv_connector; | |
1483 | ||
1484 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1485 | if (nv_connector && nv_connector->native_mode) { | |
1486 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
1487 | int id = adjusted_mode->base.id; | |
1488 | *adjusted_mode = *nv_connector->native_mode; | |
1489 | adjusted_mode->base.id = id; | |
1490 | } | |
1491 | } | |
1492 | ||
1493 | return true; | |
1494 | } | |
1495 | ||
8eaa9669 | 1496 | static void |
e225f446 | 1497 | nv50_dac_commit(struct drm_encoder *encoder) |
8eaa9669 BS |
1498 | { |
1499 | } | |
1500 | ||
1501 | static void | |
e225f446 | 1502 | nv50_dac_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
8eaa9669 BS |
1503 | struct drm_display_mode *adjusted_mode) |
1504 | { | |
e225f446 | 1505 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
8eaa9669 BS |
1506 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1507 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
97b19b5c | 1508 | u32 *push; |
8eaa9669 | 1509 | |
e225f446 | 1510 | nv50_dac_dpms(encoder, DRM_MODE_DPMS_ON); |
8eaa9669 | 1511 | |
97b19b5c | 1512 | push = evo_wait(mast, 8); |
8eaa9669 | 1513 | if (push) { |
e225f446 | 1514 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
97b19b5c BS |
1515 | u32 syncs = 0x00000000; |
1516 | ||
1517 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1518 | syncs |= 0x00000001; | |
1519 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1520 | syncs |= 0x00000002; | |
1521 | ||
1522 | evo_mthd(push, 0x0400 + (nv_encoder->or * 0x080), 2); | |
1523 | evo_data(push, 1 << nv_crtc->index); | |
1524 | evo_data(push, syncs); | |
1525 | } else { | |
1526 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); | |
1527 | u32 syncs = 0x00000001; | |
1528 | ||
1529 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1530 | syncs |= 0x00000008; | |
1531 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1532 | syncs |= 0x00000010; | |
1533 | ||
1534 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1535 | magic |= 0x00000001; | |
1536 | ||
1537 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
1538 | evo_data(push, syncs); | |
1539 | evo_data(push, magic); | |
1540 | evo_mthd(push, 0x0180 + (nv_encoder->or * 0x020), 1); | |
1541 | evo_data(push, 1 << nv_crtc->index); | |
1542 | } | |
1543 | ||
1544 | evo_kick(push, mast); | |
8eaa9669 BS |
1545 | } |
1546 | ||
1547 | nv_encoder->crtc = encoder->crtc; | |
1548 | } | |
1549 | ||
1550 | static void | |
e225f446 | 1551 | nv50_dac_disconnect(struct drm_encoder *encoder) |
8eaa9669 BS |
1552 | { |
1553 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1554 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
97b19b5c | 1555 | const int or = nv_encoder->or; |
8eaa9669 BS |
1556 | u32 *push; |
1557 | ||
1558 | if (nv_encoder->crtc) { | |
e225f446 | 1559 | nv50_crtc_prepare(nv_encoder->crtc); |
8eaa9669 | 1560 | |
97b19b5c | 1561 | push = evo_wait(mast, 4); |
8eaa9669 | 1562 | if (push) { |
e225f446 | 1563 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
97b19b5c BS |
1564 | evo_mthd(push, 0x0400 + (or * 0x080), 1); |
1565 | evo_data(push, 0x00000000); | |
1566 | } else { | |
1567 | evo_mthd(push, 0x0180 + (or * 0x020), 1); | |
1568 | evo_data(push, 0x00000000); | |
1569 | } | |
97b19b5c | 1570 | evo_kick(push, mast); |
8eaa9669 | 1571 | } |
8eaa9669 | 1572 | } |
97b19b5c BS |
1573 | |
1574 | nv_encoder->crtc = NULL; | |
8eaa9669 BS |
1575 | } |
1576 | ||
b6d8e7ec | 1577 | static enum drm_connector_status |
e225f446 | 1578 | nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector) |
b6d8e7ec | 1579 | { |
e225f446 | 1580 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
35b21d39 | 1581 | int ret, or = nouveau_encoder(encoder)->or; |
d40ee48a BS |
1582 | u32 load = nouveau_drm(encoder->dev)->vbios.dactestval; |
1583 | if (load == 0) | |
1584 | load = 340; | |
b681993f | 1585 | |
35b21d39 | 1586 | ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load)); |
4b31ebcf | 1587 | if (ret || !load) |
35b21d39 | 1588 | return connector_status_disconnected; |
b681993f | 1589 | |
35b21d39 | 1590 | return connector_status_connected; |
b6d8e7ec BS |
1591 | } |
1592 | ||
8eaa9669 | 1593 | static void |
e225f446 | 1594 | nv50_dac_destroy(struct drm_encoder *encoder) |
8eaa9669 BS |
1595 | { |
1596 | drm_encoder_cleanup(encoder); | |
1597 | kfree(encoder); | |
1598 | } | |
1599 | ||
e225f446 BS |
1600 | static const struct drm_encoder_helper_funcs nv50_dac_hfunc = { |
1601 | .dpms = nv50_dac_dpms, | |
1602 | .mode_fixup = nv50_dac_mode_fixup, | |
1603 | .prepare = nv50_dac_disconnect, | |
1604 | .commit = nv50_dac_commit, | |
1605 | .mode_set = nv50_dac_mode_set, | |
1606 | .disable = nv50_dac_disconnect, | |
1607 | .get_crtc = nv50_display_crtc_get, | |
1608 | .detect = nv50_dac_detect | |
8eaa9669 BS |
1609 | }; |
1610 | ||
e225f446 BS |
1611 | static const struct drm_encoder_funcs nv50_dac_func = { |
1612 | .destroy = nv50_dac_destroy, | |
8eaa9669 BS |
1613 | }; |
1614 | ||
1615 | static int | |
e225f446 | 1616 | nv50_dac_create(struct drm_connector *connector, struct dcb_output *dcbe) |
8eaa9669 | 1617 | { |
5ed50209 BS |
1618 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
1619 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); | |
8eaa9669 BS |
1620 | struct nouveau_encoder *nv_encoder; |
1621 | struct drm_encoder *encoder; | |
5ed50209 | 1622 | int type = DRM_MODE_ENCODER_DAC; |
8eaa9669 BS |
1623 | |
1624 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
1625 | if (!nv_encoder) | |
1626 | return -ENOMEM; | |
1627 | nv_encoder->dcb = dcbe; | |
1628 | nv_encoder->or = ffs(dcbe->or) - 1; | |
5ed50209 | 1629 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
8eaa9669 BS |
1630 | |
1631 | encoder = to_drm_encoder(nv_encoder); | |
1632 | encoder->possible_crtcs = dcbe->heads; | |
1633 | encoder->possible_clones = 0; | |
5ed50209 | 1634 | drm_encoder_init(connector->dev, encoder, &nv50_dac_func, type); |
e225f446 | 1635 | drm_encoder_helper_add(encoder, &nv50_dac_hfunc); |
8eaa9669 BS |
1636 | |
1637 | drm_mode_connector_attach_encoder(connector, encoder); | |
1638 | return 0; | |
1639 | } | |
26f6d88b | 1640 | |
78951d22 BS |
1641 | /****************************************************************************** |
1642 | * Audio | |
1643 | *****************************************************************************/ | |
1644 | static void | |
e225f446 | 1645 | nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 BS |
1646 | { |
1647 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1648 | struct nouveau_connector *nv_connector; | |
e225f446 | 1649 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
78951d22 BS |
1650 | |
1651 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1652 | if (!drm_detect_monitor_audio(nv_connector->edid)) | |
1653 | return; | |
1654 | ||
78951d22 | 1655 | drm_edid_to_eld(&nv_connector->base, nv_connector->edid); |
78951d22 | 1656 | |
0a9e2b95 BS |
1657 | nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, |
1658 | nv_connector->base.eld, | |
1659 | nv_connector->base.eld[2] * 4); | |
78951d22 BS |
1660 | } |
1661 | ||
1662 | static void | |
e225f446 | 1663 | nv50_audio_disconnect(struct drm_encoder *encoder) |
78951d22 BS |
1664 | { |
1665 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1666 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
78951d22 | 1667 | |
0a9e2b95 | 1668 | nv_exec(disp->core, NVA3_DISP_SOR_HDA_ELD + nv_encoder->or, NULL, 0); |
78951d22 BS |
1669 | } |
1670 | ||
1671 | /****************************************************************************** | |
1672 | * HDMI | |
1673 | *****************************************************************************/ | |
1674 | static void | |
e225f446 | 1675 | nv50_hdmi_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) |
78951d22 | 1676 | { |
64d9cc04 BS |
1677 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1678 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
1679 | struct nouveau_connector *nv_connector; | |
e225f446 | 1680 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1c30cd09 | 1681 | const u32 moff = (nv_crtc->index << 3) | nv_encoder->or; |
64d9cc04 BS |
1682 | u32 rekey = 56; /* binary driver, and tegra constant */ |
1683 | u32 max_ac_packet; | |
1684 | ||
1685 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1686 | if (!drm_detect_hdmi_monitor(nv_connector->edid)) | |
1687 | return; | |
1688 | ||
1689 | max_ac_packet = mode->htotal - mode->hdisplay; | |
1690 | max_ac_packet -= rekey; | |
1691 | max_ac_packet -= 18; /* constant from tegra */ | |
1692 | max_ac_packet /= 32; | |
1693 | ||
1c30cd09 BS |
1694 | nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, |
1695 | NV84_DISP_SOR_HDMI_PWR_STATE_ON | | |
1696 | (max_ac_packet << 16) | rekey); | |
091e40cd | 1697 | |
e225f446 | 1698 | nv50_audio_mode_set(encoder, mode); |
78951d22 BS |
1699 | } |
1700 | ||
1701 | static void | |
e225f446 | 1702 | nv50_hdmi_disconnect(struct drm_encoder *encoder) |
78951d22 | 1703 | { |
64d9cc04 BS |
1704 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1705 | struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc); | |
e225f446 | 1706 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1c30cd09 | 1707 | const u32 moff = (nv_crtc->index << 3) | nv_encoder->or; |
64d9cc04 | 1708 | |
e225f446 | 1709 | nv50_audio_disconnect(encoder); |
64d9cc04 | 1710 | |
1c30cd09 | 1711 | nv_call(disp->core, NV84_DISP_SOR_HDMI_PWR + moff, 0x00000000); |
78951d22 BS |
1712 | } |
1713 | ||
26f6d88b BS |
1714 | /****************************************************************************** |
1715 | * SOR | |
1716 | *****************************************************************************/ | |
83fc083c | 1717 | static void |
e225f446 | 1718 | nv50_sor_dpms(struct drm_encoder *encoder, int mode) |
83fc083c BS |
1719 | { |
1720 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1721 | struct drm_device *dev = encoder->dev; | |
e225f446 | 1722 | struct nv50_disp *disp = nv50_disp(dev); |
83fc083c BS |
1723 | struct drm_encoder *partner; |
1724 | int or = nv_encoder->or; | |
83fc083c BS |
1725 | |
1726 | nv_encoder->last_dpms = mode; | |
1727 | ||
1728 | list_for_each_entry(partner, &dev->mode_config.encoder_list, head) { | |
1729 | struct nouveau_encoder *nv_partner = nouveau_encoder(partner); | |
1730 | ||
1731 | if (partner->encoder_type != DRM_MODE_ENCODER_TMDS) | |
1732 | continue; | |
1733 | ||
1734 | if (nv_partner != nv_encoder && | |
26cfa813 | 1735 | nv_partner->dcb->or == nv_encoder->dcb->or) { |
83fc083c BS |
1736 | if (nv_partner->last_dpms == DRM_MODE_DPMS_ON) |
1737 | return; | |
1738 | break; | |
1739 | } | |
1740 | } | |
1741 | ||
74b66850 | 1742 | nv_call(disp->core, NV50_DISP_SOR_PWR + or, (mode == DRM_MODE_DPMS_ON)); |
83fc083c BS |
1743 | } |
1744 | ||
1745 | static bool | |
e225f446 | 1746 | nv50_sor_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 1747 | const struct drm_display_mode *mode, |
83fc083c BS |
1748 | struct drm_display_mode *adjusted_mode) |
1749 | { | |
1750 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1751 | struct nouveau_connector *nv_connector; | |
1752 | ||
1753 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
1754 | if (nv_connector && nv_connector->native_mode) { | |
1755 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
1756 | int id = adjusted_mode->base.id; | |
1757 | *adjusted_mode = *nv_connector->native_mode; | |
1758 | adjusted_mode->base.id = id; | |
1759 | } | |
1760 | } | |
1761 | ||
1762 | return true; | |
1763 | } | |
1764 | ||
4cbb0f8d | 1765 | static void |
e225f446 | 1766 | nv50_sor_disconnect(struct drm_encoder *encoder) |
4cbb0f8d BS |
1767 | { |
1768 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
e225f446 | 1769 | struct nv50_mast *mast = nv50_mast(encoder->dev); |
419e8dc0 | 1770 | const int or = nv_encoder->or; |
4cbb0f8d BS |
1771 | u32 *push; |
1772 | ||
1773 | if (nv_encoder->crtc) { | |
e225f446 | 1774 | nv50_crtc_prepare(nv_encoder->crtc); |
4cbb0f8d | 1775 | |
419e8dc0 | 1776 | push = evo_wait(mast, 4); |
4cbb0f8d | 1777 | if (push) { |
e225f446 | 1778 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { |
419e8dc0 BS |
1779 | evo_mthd(push, 0x0600 + (or * 0x40), 1); |
1780 | evo_data(push, 0x00000000); | |
1781 | } else { | |
1782 | evo_mthd(push, 0x0200 + (or * 0x20), 1); | |
1783 | evo_data(push, 0x00000000); | |
1784 | } | |
419e8dc0 | 1785 | evo_kick(push, mast); |
4cbb0f8d BS |
1786 | } |
1787 | ||
e225f446 | 1788 | nv50_hdmi_disconnect(encoder); |
4cbb0f8d | 1789 | } |
419e8dc0 BS |
1790 | |
1791 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; | |
1792 | nv_encoder->crtc = NULL; | |
4cbb0f8d BS |
1793 | } |
1794 | ||
83fc083c | 1795 | static void |
e225f446 | 1796 | nv50_sor_commit(struct drm_encoder *encoder) |
83fc083c BS |
1797 | { |
1798 | } | |
1799 | ||
1800 | static void | |
e225f446 | 1801 | nv50_sor_mode_set(struct drm_encoder *encoder, struct drm_display_mode *umode, |
3b6d83d1 | 1802 | struct drm_display_mode *mode) |
83fc083c | 1803 | { |
e225f446 BS |
1804 | struct nv50_disp *disp = nv50_disp(encoder->dev); |
1805 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
78951d22 | 1806 | struct drm_device *dev = encoder->dev; |
77145f1c | 1807 | struct nouveau_drm *drm = nouveau_drm(dev); |
83fc083c BS |
1808 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); |
1809 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
3b6d83d1 | 1810 | struct nouveau_connector *nv_connector; |
77145f1c | 1811 | struct nvbios *bios = &drm->vbios; |
419e8dc0 BS |
1812 | u32 *push, lvds = 0; |
1813 | u8 owner = 1 << nv_crtc->index; | |
1814 | u8 proto = 0xf; | |
1815 | u8 depth = 0x0; | |
83fc083c | 1816 | |
3b6d83d1 BS |
1817 | nv_connector = nouveau_encoder_connector_get(nv_encoder); |
1818 | switch (nv_encoder->dcb->type) { | |
cb75d97e | 1819 | case DCB_OUTPUT_TMDS: |
3b6d83d1 BS |
1820 | if (nv_encoder->dcb->sorconf.link & 1) { |
1821 | if (mode->clock < 165000) | |
419e8dc0 | 1822 | proto = 0x1; |
3b6d83d1 | 1823 | else |
419e8dc0 | 1824 | proto = 0x5; |
3b6d83d1 | 1825 | } else { |
419e8dc0 | 1826 | proto = 0x2; |
3b6d83d1 BS |
1827 | } |
1828 | ||
e225f446 | 1829 | nv50_hdmi_mode_set(encoder, mode); |
3b6d83d1 | 1830 | break; |
cb75d97e | 1831 | case DCB_OUTPUT_LVDS: |
419e8dc0 BS |
1832 | proto = 0x0; |
1833 | ||
3b6d83d1 BS |
1834 | if (bios->fp_no_ddc) { |
1835 | if (bios->fp.dual_link) | |
419e8dc0 | 1836 | lvds |= 0x0100; |
3b6d83d1 | 1837 | if (bios->fp.if_is_24bit) |
419e8dc0 | 1838 | lvds |= 0x0200; |
3b6d83d1 | 1839 | } else { |
befb51e9 | 1840 | if (nv_connector->type == DCB_CONNECTOR_LVDS_SPWG) { |
3b6d83d1 | 1841 | if (((u8 *)nv_connector->edid)[121] == 2) |
419e8dc0 | 1842 | lvds |= 0x0100; |
3b6d83d1 BS |
1843 | } else |
1844 | if (mode->clock >= bios->fp.duallink_transition_clk) { | |
419e8dc0 | 1845 | lvds |= 0x0100; |
3b6d83d1 | 1846 | } |
83fc083c | 1847 | |
419e8dc0 | 1848 | if (lvds & 0x0100) { |
3b6d83d1 | 1849 | if (bios->fp.strapless_is_24bit & 2) |
419e8dc0 | 1850 | lvds |= 0x0200; |
3b6d83d1 BS |
1851 | } else { |
1852 | if (bios->fp.strapless_is_24bit & 1) | |
419e8dc0 | 1853 | lvds |= 0x0200; |
3b6d83d1 BS |
1854 | } |
1855 | ||
1856 | if (nv_connector->base.display_info.bpc == 8) | |
419e8dc0 | 1857 | lvds |= 0x0200; |
3b6d83d1 | 1858 | } |
4a230fa6 | 1859 | |
419e8dc0 | 1860 | nv_call(disp->core, NV50_DISP_SOR_LVDS_SCRIPT + nv_encoder->or, lvds); |
3b6d83d1 | 1861 | break; |
cb75d97e | 1862 | case DCB_OUTPUT_DP: |
3488c57b | 1863 | if (nv_connector->base.display_info.bpc == 6) { |
6e83fda2 | 1864 | nv_encoder->dp.datarate = mode->clock * 18 / 8; |
419e8dc0 | 1865 | depth = 0x2; |
bf2c886a BS |
1866 | } else |
1867 | if (nv_connector->base.display_info.bpc == 8) { | |
6e83fda2 | 1868 | nv_encoder->dp.datarate = mode->clock * 24 / 8; |
419e8dc0 | 1869 | depth = 0x5; |
bf2c886a BS |
1870 | } else { |
1871 | nv_encoder->dp.datarate = mode->clock * 30 / 8; | |
1872 | depth = 0x6; | |
3488c57b | 1873 | } |
6e83fda2 BS |
1874 | |
1875 | if (nv_encoder->dcb->sorconf.link & 1) | |
419e8dc0 | 1876 | proto = 0x8; |
6e83fda2 | 1877 | else |
419e8dc0 | 1878 | proto = 0x9; |
6e83fda2 | 1879 | break; |
3b6d83d1 BS |
1880 | default: |
1881 | BUG_ON(1); | |
1882 | break; | |
1883 | } | |
ff8ff503 | 1884 | |
e225f446 | 1885 | nv50_sor_dpms(encoder, DRM_MODE_DPMS_ON); |
83fc083c | 1886 | |
e225f446 | 1887 | push = evo_wait(nv50_mast(dev), 8); |
83fc083c | 1888 | if (push) { |
e225f446 | 1889 | if (nv50_vers(mast) < NVD0_DISP_CLASS) { |
e2de1794 BS |
1890 | u32 ctrl = (depth << 16) | (proto << 8) | owner; |
1891 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1892 | ctrl |= 0x00001000; | |
1893 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1894 | ctrl |= 0x00002000; | |
419e8dc0 | 1895 | evo_mthd(push, 0x0600 + (nv_encoder->or * 0x040), 1); |
e2de1794 | 1896 | evo_data(push, ctrl); |
419e8dc0 BS |
1897 | } else { |
1898 | u32 magic = 0x31ec6000 | (nv_crtc->index << 25); | |
1899 | u32 syncs = 0x00000001; | |
1900 | ||
1901 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
1902 | syncs |= 0x00000008; | |
1903 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
1904 | syncs |= 0x00000010; | |
1905 | ||
1906 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
1907 | magic |= 0x00000001; | |
1908 | ||
1909 | evo_mthd(push, 0x0404 + (nv_crtc->index * 0x300), 2); | |
1910 | evo_data(push, syncs | (depth << 6)); | |
1911 | evo_data(push, magic); | |
1912 | evo_mthd(push, 0x0200 + (nv_encoder->or * 0x020), 1); | |
1913 | evo_data(push, owner | (proto << 8)); | |
1914 | } | |
1915 | ||
1916 | evo_kick(push, mast); | |
83fc083c BS |
1917 | } |
1918 | ||
1919 | nv_encoder->crtc = encoder->crtc; | |
1920 | } | |
1921 | ||
83fc083c | 1922 | static void |
e225f446 | 1923 | nv50_sor_destroy(struct drm_encoder *encoder) |
83fc083c BS |
1924 | { |
1925 | drm_encoder_cleanup(encoder); | |
1926 | kfree(encoder); | |
1927 | } | |
1928 | ||
e225f446 BS |
1929 | static const struct drm_encoder_helper_funcs nv50_sor_hfunc = { |
1930 | .dpms = nv50_sor_dpms, | |
1931 | .mode_fixup = nv50_sor_mode_fixup, | |
5a885f0b | 1932 | .prepare = nv50_sor_disconnect, |
e225f446 BS |
1933 | .commit = nv50_sor_commit, |
1934 | .mode_set = nv50_sor_mode_set, | |
1935 | .disable = nv50_sor_disconnect, | |
1936 | .get_crtc = nv50_display_crtc_get, | |
83fc083c BS |
1937 | }; |
1938 | ||
e225f446 BS |
1939 | static const struct drm_encoder_funcs nv50_sor_func = { |
1940 | .destroy = nv50_sor_destroy, | |
83fc083c BS |
1941 | }; |
1942 | ||
1943 | static int | |
e225f446 | 1944 | nv50_sor_create(struct drm_connector *connector, struct dcb_output *dcbe) |
83fc083c | 1945 | { |
5ed50209 BS |
1946 | struct nouveau_drm *drm = nouveau_drm(connector->dev); |
1947 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); | |
83fc083c BS |
1948 | struct nouveau_encoder *nv_encoder; |
1949 | struct drm_encoder *encoder; | |
5ed50209 BS |
1950 | int type; |
1951 | ||
1952 | switch (dcbe->type) { | |
1953 | case DCB_OUTPUT_LVDS: type = DRM_MODE_ENCODER_LVDS; break; | |
1954 | case DCB_OUTPUT_TMDS: | |
1955 | case DCB_OUTPUT_DP: | |
1956 | default: | |
1957 | type = DRM_MODE_ENCODER_TMDS; | |
1958 | break; | |
1959 | } | |
83fc083c BS |
1960 | |
1961 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
1962 | if (!nv_encoder) | |
1963 | return -ENOMEM; | |
1964 | nv_encoder->dcb = dcbe; | |
1965 | nv_encoder->or = ffs(dcbe->or) - 1; | |
5ed50209 | 1966 | nv_encoder->i2c = i2c->find(i2c, dcbe->i2c_index); |
83fc083c BS |
1967 | nv_encoder->last_dpms = DRM_MODE_DPMS_OFF; |
1968 | ||
1969 | encoder = to_drm_encoder(nv_encoder); | |
1970 | encoder->possible_crtcs = dcbe->heads; | |
1971 | encoder->possible_clones = 0; | |
5ed50209 | 1972 | drm_encoder_init(connector->dev, encoder, &nv50_sor_func, type); |
e225f446 | 1973 | drm_encoder_helper_add(encoder, &nv50_sor_hfunc); |
83fc083c BS |
1974 | |
1975 | drm_mode_connector_attach_encoder(connector, encoder); | |
1976 | return 0; | |
1977 | } | |
26f6d88b | 1978 | |
eb6313ad BS |
1979 | /****************************************************************************** |
1980 | * PIOR | |
1981 | *****************************************************************************/ | |
1982 | ||
1983 | static void | |
1984 | nv50_pior_dpms(struct drm_encoder *encoder, int mode) | |
1985 | { | |
1986 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1987 | struct nv50_disp *disp = nv50_disp(encoder->dev); | |
1988 | u32 mthd = (nv_encoder->dcb->type << 12) | nv_encoder->or; | |
1989 | u32 ctrl = (mode == DRM_MODE_DPMS_ON); | |
1990 | nv_call(disp->core, NV50_DISP_PIOR_PWR + mthd, ctrl); | |
1991 | } | |
1992 | ||
1993 | static bool | |
1994 | nv50_pior_mode_fixup(struct drm_encoder *encoder, | |
1995 | const struct drm_display_mode *mode, | |
1996 | struct drm_display_mode *adjusted_mode) | |
1997 | { | |
1998 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
1999 | struct nouveau_connector *nv_connector; | |
2000 | ||
2001 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2002 | if (nv_connector && nv_connector->native_mode) { | |
2003 | if (nv_connector->scaling_mode != DRM_MODE_SCALE_NONE) { | |
2004 | int id = adjusted_mode->base.id; | |
2005 | *adjusted_mode = *nv_connector->native_mode; | |
2006 | adjusted_mode->base.id = id; | |
2007 | } | |
2008 | } | |
2009 | ||
2010 | adjusted_mode->clock *= 2; | |
2011 | return true; | |
2012 | } | |
2013 | ||
2014 | static void | |
2015 | nv50_pior_commit(struct drm_encoder *encoder) | |
2016 | { | |
2017 | } | |
2018 | ||
2019 | static void | |
2020 | nv50_pior_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, | |
2021 | struct drm_display_mode *adjusted_mode) | |
2022 | { | |
2023 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2024 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2025 | struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc); | |
2026 | struct nouveau_connector *nv_connector; | |
2027 | u8 owner = 1 << nv_crtc->index; | |
2028 | u8 proto, depth; | |
2029 | u32 *push; | |
2030 | ||
2031 | nv_connector = nouveau_encoder_connector_get(nv_encoder); | |
2032 | switch (nv_connector->base.display_info.bpc) { | |
2033 | case 10: depth = 0x6; break; | |
2034 | case 8: depth = 0x5; break; | |
2035 | case 6: depth = 0x2; break; | |
2036 | default: depth = 0x0; break; | |
2037 | } | |
2038 | ||
2039 | switch (nv_encoder->dcb->type) { | |
2040 | case DCB_OUTPUT_TMDS: | |
2041 | case DCB_OUTPUT_DP: | |
2042 | proto = 0x0; | |
2043 | break; | |
2044 | default: | |
2045 | BUG_ON(1); | |
2046 | break; | |
2047 | } | |
2048 | ||
2049 | nv50_pior_dpms(encoder, DRM_MODE_DPMS_ON); | |
2050 | ||
2051 | push = evo_wait(mast, 8); | |
2052 | if (push) { | |
2053 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { | |
2054 | u32 ctrl = (depth << 16) | (proto << 8) | owner; | |
2055 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
2056 | ctrl |= 0x00001000; | |
2057 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
2058 | ctrl |= 0x00002000; | |
2059 | evo_mthd(push, 0x0700 + (nv_encoder->or * 0x040), 1); | |
2060 | evo_data(push, ctrl); | |
2061 | } | |
2062 | ||
2063 | evo_kick(push, mast); | |
2064 | } | |
2065 | ||
2066 | nv_encoder->crtc = encoder->crtc; | |
2067 | } | |
2068 | ||
2069 | static void | |
2070 | nv50_pior_disconnect(struct drm_encoder *encoder) | |
2071 | { | |
2072 | struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder); | |
2073 | struct nv50_mast *mast = nv50_mast(encoder->dev); | |
2074 | const int or = nv_encoder->or; | |
2075 | u32 *push; | |
2076 | ||
2077 | if (nv_encoder->crtc) { | |
2078 | nv50_crtc_prepare(nv_encoder->crtc); | |
2079 | ||
2080 | push = evo_wait(mast, 4); | |
2081 | if (push) { | |
2082 | if (nv50_vers(mast) < NVD0_DISP_MAST_CLASS) { | |
2083 | evo_mthd(push, 0x0700 + (or * 0x040), 1); | |
2084 | evo_data(push, 0x00000000); | |
2085 | } | |
eb6313ad BS |
2086 | evo_kick(push, mast); |
2087 | } | |
2088 | } | |
2089 | ||
2090 | nv_encoder->crtc = NULL; | |
2091 | } | |
2092 | ||
2093 | static void | |
2094 | nv50_pior_destroy(struct drm_encoder *encoder) | |
2095 | { | |
2096 | drm_encoder_cleanup(encoder); | |
2097 | kfree(encoder); | |
2098 | } | |
2099 | ||
2100 | static const struct drm_encoder_helper_funcs nv50_pior_hfunc = { | |
2101 | .dpms = nv50_pior_dpms, | |
2102 | .mode_fixup = nv50_pior_mode_fixup, | |
2103 | .prepare = nv50_pior_disconnect, | |
2104 | .commit = nv50_pior_commit, | |
2105 | .mode_set = nv50_pior_mode_set, | |
2106 | .disable = nv50_pior_disconnect, | |
2107 | .get_crtc = nv50_display_crtc_get, | |
2108 | }; | |
2109 | ||
2110 | static const struct drm_encoder_funcs nv50_pior_func = { | |
2111 | .destroy = nv50_pior_destroy, | |
2112 | }; | |
2113 | ||
2114 | static int | |
2115 | nv50_pior_create(struct drm_connector *connector, struct dcb_output *dcbe) | |
2116 | { | |
2117 | struct nouveau_drm *drm = nouveau_drm(connector->dev); | |
2118 | struct nouveau_i2c *i2c = nouveau_i2c(drm->device); | |
2119 | struct nouveau_i2c_port *ddc = NULL; | |
2120 | struct nouveau_encoder *nv_encoder; | |
2121 | struct drm_encoder *encoder; | |
2122 | int type; | |
2123 | ||
2124 | switch (dcbe->type) { | |
2125 | case DCB_OUTPUT_TMDS: | |
2126 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTDDC(dcbe->extdev)); | |
2127 | type = DRM_MODE_ENCODER_TMDS; | |
2128 | break; | |
2129 | case DCB_OUTPUT_DP: | |
2130 | ddc = i2c->find_type(i2c, NV_I2C_TYPE_EXTAUX(dcbe->extdev)); | |
2131 | type = DRM_MODE_ENCODER_TMDS; | |
2132 | break; | |
2133 | default: | |
2134 | return -ENODEV; | |
2135 | } | |
2136 | ||
2137 | nv_encoder = kzalloc(sizeof(*nv_encoder), GFP_KERNEL); | |
2138 | if (!nv_encoder) | |
2139 | return -ENOMEM; | |
2140 | nv_encoder->dcb = dcbe; | |
2141 | nv_encoder->or = ffs(dcbe->or) - 1; | |
2142 | nv_encoder->i2c = ddc; | |
2143 | ||
2144 | encoder = to_drm_encoder(nv_encoder); | |
2145 | encoder->possible_crtcs = dcbe->heads; | |
2146 | encoder->possible_clones = 0; | |
2147 | drm_encoder_init(connector->dev, encoder, &nv50_pior_func, type); | |
2148 | drm_encoder_helper_add(encoder, &nv50_pior_hfunc); | |
2149 | ||
2150 | drm_mode_connector_attach_encoder(connector, encoder); | |
2151 | return 0; | |
2152 | } | |
2153 | ||
26f6d88b BS |
2154 | /****************************************************************************** |
2155 | * Init | |
2156 | *****************************************************************************/ | |
2a44e499 | 2157 | void |
e225f446 | 2158 | nv50_display_fini(struct drm_device *dev) |
26f6d88b | 2159 | { |
26f6d88b BS |
2160 | } |
2161 | ||
2162 | int | |
e225f446 | 2163 | nv50_display_init(struct drm_device *dev) |
26f6d88b | 2164 | { |
9f9bdaaf BS |
2165 | struct nv50_disp *disp = nv50_disp(dev); |
2166 | struct drm_crtc *crtc; | |
2167 | u32 *push; | |
2168 | ||
2169 | push = evo_wait(nv50_mast(dev), 32); | |
2170 | if (!push) | |
2171 | return -EBUSY; | |
2172 | ||
2173 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
2174 | struct nv50_sync *sync = nv50_sync(crtc); | |
2175 | nouveau_bo_wr32(disp->sync, sync->addr / 4, sync->data); | |
bdb8c212 | 2176 | } |
efd272a7 | 2177 | |
9f9bdaaf BS |
2178 | evo_mthd(push, 0x0088, 1); |
2179 | evo_data(push, NvEvoSync); | |
2180 | evo_kick(push, nv50_mast(dev)); | |
2181 | return 0; | |
26f6d88b BS |
2182 | } |
2183 | ||
2184 | void | |
e225f446 | 2185 | nv50_display_destroy(struct drm_device *dev) |
26f6d88b | 2186 | { |
e225f446 | 2187 | struct nv50_disp *disp = nv50_disp(dev); |
bdb8c212 | 2188 | |
e225f446 | 2189 | nv50_dmac_destroy(disp->core, &disp->mast.base); |
26f6d88b | 2190 | |
816af2f2 | 2191 | nouveau_bo_unmap(disp->sync); |
04c8c210 MS |
2192 | if (disp->sync) |
2193 | nouveau_bo_unpin(disp->sync); | |
816af2f2 | 2194 | nouveau_bo_ref(NULL, &disp->sync); |
51beb428 | 2195 | |
77145f1c | 2196 | nouveau_display(dev)->priv = NULL; |
26f6d88b BS |
2197 | kfree(disp); |
2198 | } | |
2199 | ||
2200 | int | |
e225f446 | 2201 | nv50_display_create(struct drm_device *dev) |
26f6d88b | 2202 | { |
77145f1c BS |
2203 | struct nouveau_device *device = nouveau_dev(dev); |
2204 | struct nouveau_drm *drm = nouveau_drm(dev); | |
77145f1c | 2205 | struct dcb_table *dcb = &drm->vbios.dcb; |
83fc083c | 2206 | struct drm_connector *connector, *tmp; |
e225f446 | 2207 | struct nv50_disp *disp; |
cb75d97e | 2208 | struct dcb_output *dcbe; |
7c5f6a87 | 2209 | int crtcs, ret, i; |
26f6d88b BS |
2210 | |
2211 | disp = kzalloc(sizeof(*disp), GFP_KERNEL); | |
2212 | if (!disp) | |
2213 | return -ENOMEM; | |
77145f1c BS |
2214 | |
2215 | nouveau_display(dev)->priv = disp; | |
e225f446 BS |
2216 | nouveau_display(dev)->dtor = nv50_display_destroy; |
2217 | nouveau_display(dev)->init = nv50_display_init; | |
2218 | nouveau_display(dev)->fini = nv50_display_fini; | |
2332b311 | 2219 | disp->core = nouveau_display(dev)->core; |
26f6d88b | 2220 | |
b5a794b0 BS |
2221 | /* small shared memory area we use for notifiers and semaphores */ |
2222 | ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, | |
2223 | 0, 0x0000, NULL, &disp->sync); | |
2224 | if (!ret) { | |
2225 | ret = nouveau_bo_pin(disp->sync, TTM_PL_FLAG_VRAM); | |
04c8c210 | 2226 | if (!ret) { |
b5a794b0 | 2227 | ret = nouveau_bo_map(disp->sync); |
04c8c210 MS |
2228 | if (ret) |
2229 | nouveau_bo_unpin(disp->sync); | |
2230 | } | |
b5a794b0 BS |
2231 | if (ret) |
2232 | nouveau_bo_ref(NULL, &disp->sync); | |
2233 | } | |
2234 | ||
b5a794b0 BS |
2235 | if (ret) |
2236 | goto out; | |
2237 | ||
2238 | /* allocate master evo channel */ | |
e225f446 | 2239 | ret = nv50_dmac_create(disp->core, NV50_DISP_MAST_CLASS, 0, |
b5a794b0 BS |
2240 | &(struct nv50_display_mast_class) { |
2241 | .pushbuf = EVO_PUSH_HANDLE(MAST, 0), | |
2242 | }, sizeof(struct nv50_display_mast_class), | |
2243 | disp->sync->bo.offset, &disp->mast.base); | |
2244 | if (ret) | |
2245 | goto out; | |
2246 | ||
438d99e3 | 2247 | /* create crtc objects to represent the hw heads */ |
63718a07 BS |
2248 | if (nv_mclass(disp->core) >= NVD0_DISP_CLASS) |
2249 | crtcs = nv_rd32(device, 0x022448); | |
2250 | else | |
2251 | crtcs = 2; | |
2252 | ||
7c5f6a87 | 2253 | for (i = 0; i < crtcs; i++) { |
e225f446 | 2254 | ret = nv50_crtc_create(dev, disp->core, i); |
438d99e3 BS |
2255 | if (ret) |
2256 | goto out; | |
2257 | } | |
2258 | ||
83fc083c BS |
2259 | /* create encoder/connector objects based on VBIOS DCB table */ |
2260 | for (i = 0, dcbe = &dcb->entry[0]; i < dcb->entries; i++, dcbe++) { | |
2261 | connector = nouveau_connector_create(dev, dcbe->connector); | |
2262 | if (IS_ERR(connector)) | |
2263 | continue; | |
2264 | ||
eb6313ad BS |
2265 | if (dcbe->location == DCB_LOC_ON_CHIP) { |
2266 | switch (dcbe->type) { | |
2267 | case DCB_OUTPUT_TMDS: | |
2268 | case DCB_OUTPUT_LVDS: | |
2269 | case DCB_OUTPUT_DP: | |
2270 | ret = nv50_sor_create(connector, dcbe); | |
2271 | break; | |
2272 | case DCB_OUTPUT_ANALOG: | |
2273 | ret = nv50_dac_create(connector, dcbe); | |
2274 | break; | |
2275 | default: | |
2276 | ret = -ENODEV; | |
2277 | break; | |
2278 | } | |
2279 | } else { | |
2280 | ret = nv50_pior_create(connector, dcbe); | |
83fc083c BS |
2281 | } |
2282 | ||
eb6313ad BS |
2283 | if (ret) { |
2284 | NV_WARN(drm, "failed to create encoder %d/%d/%d: %d\n", | |
2285 | dcbe->location, dcbe->type, | |
2286 | ffs(dcbe->or) - 1, ret); | |
94f54f53 | 2287 | ret = 0; |
83fc083c BS |
2288 | } |
2289 | } | |
2290 | ||
2291 | /* cull any connectors we created that don't have an encoder */ | |
2292 | list_for_each_entry_safe(connector, tmp, &dev->mode_config.connector_list, head) { | |
2293 | if (connector->encoder_ids[0]) | |
2294 | continue; | |
2295 | ||
77145f1c | 2296 | NV_WARN(drm, "%s has no encoders, removing\n", |
83fc083c BS |
2297 | drm_get_connector_name(connector)); |
2298 | connector->funcs->destroy(connector); | |
2299 | } | |
2300 | ||
26f6d88b BS |
2301 | out: |
2302 | if (ret) | |
e225f446 | 2303 | nv50_display_destroy(dev); |
26f6d88b BS |
2304 | return ret; |
2305 | } |