drm/nouveau: port all engines to new engine module format
[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv50_display.h
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1/*
2 * Copyright (C) 2008 Maarten Maathuis.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sublicense, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial
15 * portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef __NV50_DISPLAY_H__
28#define __NV50_DISPLAY_H__
29
30#include "drmP.h"
31#include "drm.h"
32#include "nouveau_drv.h"
33#include "nouveau_dma.h"
34#include "nouveau_reg.h"
35#include "nouveau_crtc.h"
36#include "nv50_evo.h"
37
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38struct nv50_display_crtc {
39 struct nouveau_channel *sync;
40 struct {
41 struct nouveau_bo *bo;
42 u32 offset;
43 u16 value;
44 } sem;
45};
46
ef8389a8 47struct nv50_display {
59c0f578 48 struct nouveau_channel *master;
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49
50 struct nouveau_gpuobj *ramin;
51 u32 dmao;
52 u32 hash;
ef8389a8 53
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54 struct nv50_display_crtc crtc[2];
55
f13e435c 56 struct tasklet_struct tasklet;
ef8389a8 57 struct {
cb75d97e 58 struct dcb_output *dcb;
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59 u16 script;
60 u32 pclk;
61 } irq;
62};
63
64static inline struct nv50_display *
65nv50_display(struct drm_device *dev)
66{
67 struct drm_nouveau_private *dev_priv = dev->dev_private;
68 return dev_priv->engine.display.priv;
69}
70
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71int nv50_display_early_init(struct drm_device *dev);
72void nv50_display_late_takedown(struct drm_device *dev);
6ee73861 73int nv50_display_create(struct drm_device *dev);
c88c2e06 74int nv50_display_init(struct drm_device *dev);
2a44e499 75void nv50_display_fini(struct drm_device *dev);
c88c2e06 76void nv50_display_destroy(struct drm_device *dev);
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77int nv50_crtc_blank(struct nouveau_crtc *, bool blank);
78int nv50_crtc_set_clock(struct drm_device *, int head, int pclk);
79
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80u32 nv50_display_active_crtcs(struct drm_device *);
81
e6e039d1 82int nv50_display_sync(struct drm_device *);
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83int nv50_display_flip_next(struct drm_crtc *, struct drm_framebuffer *,
84 struct nouveau_channel *chan);
85void nv50_display_flip_stop(struct drm_crtc *);
86
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87int nv50_evo_create(struct drm_device *dev);
88void nv50_evo_destroy(struct drm_device *dev);
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89int nv50_evo_init(struct drm_device *dev);
90void nv50_evo_fini(struct drm_device *dev);
91void nv50_evo_dmaobj_init(struct nouveau_gpuobj *, u32 memtype, u64 base,
92 u64 size);
93int nv50_evo_dmaobj_new(struct nouveau_channel *, u32 handle, u32 memtype,
94 u64 base, u64 size, struct nouveau_gpuobj **);
95
6ee73861 96#endif /* __NV50_DISPLAY_H__ */
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