[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv50_evo.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"

#include "nouveau_drv.h"
#include "nouveau_dma.h"
#include "nouveau_ramht.h"
#include "nv50_display.h"

static void
nv50_evo_channel_del(struct nouveau_channel **pevo)
{
	struct nouveau_channel *evo = *pevo;

	if (!evo)
		return;
	*pevo = NULL;

	nouveau_ramht_ref(NULL, &evo->ramht, evo);
	nouveau_gpuobj_channel_takedown(evo);
	nouveau_bo_unmap(evo->pushbuf_bo);
	nouveau_bo_ref(NULL, &evo->pushbuf_bo);

	if (evo->user)
		iounmap(evo->user);

	kfree(evo);
}

void
nv50_evo_dmaobj_init(struct nouveau_gpuobj *obj, u32 memtype, u64 base, u64 size)
{
	struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
	u32 flags5;

	if (dev_priv->chipset < 0xc0) {
		/* not supported on 0x50, specified in format mthd */
		if (dev_priv->chipset == 0x50)
			memtype = 0;
		flags5 = 0x00010000;
	} else {
		if (memtype & 0x80000000)
			flags5 = 0x00000000; /* large pages */
		else
			flags5 = 0x00020000;
	}

	nv50_gpuobj_dma_init(obj, 0, 0x3d, base, size, NV_MEM_TARGET_VRAM,
			     NV_MEM_ACCESS_RW, (memtype >> 8) & 0xff, 0);
	nv_wo32(obj, 0x14, flags5);
	dev_priv->engine.instmem.flush(obj->dev);
}

int
nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype,
		    u64 base, u64 size, struct nouveau_gpuobj **pobj)
{
	struct nv50_display *disp = nv50_display(evo->dev);
	struct nouveau_gpuobj *obj = NULL;
	int ret;

	ret = nouveau_gpuobj_new(evo->dev, disp->master, 6*4, 32, 0, &obj);
	if (ret)
		return ret;
	obj->engine = NVOBJ_ENGINE_DISPLAY;

	nv50_evo_dmaobj_init(obj, memtype, base, size);

	ret = nouveau_ramht_insert(evo, handle, obj);
	if (ret)
		goto out;

	if (pobj)
		nouveau_gpuobj_ref(obj, pobj);
out:
	nouveau_gpuobj_ref(NULL, &obj);
	return ret;
}

static int
nv50_evo_channel_new(struct drm_device *dev, int chid,
		     struct nouveau_channel **pevo)
{
	struct nv50_display *disp = nv50_display(dev);
	struct nouveau_channel *evo;
	int ret;

	evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
	if (!evo)
		return -ENOMEM;
	*pevo = evo;

	evo->id = chid;
	evo->dev = dev;
	evo->user_get = 4;
	evo->user_put = 0;

	ret = nouveau_bo_new(dev, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0, NULL,
			     &evo->pushbuf_bo);
	if (ret == 0)
		ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
	if (ret) {
		NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
		nv50_evo_channel_del(pevo);
		return ret;
	}

	ret = nouveau_bo_map(evo->pushbuf_bo);
	if (ret) {
		NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
		nv50_evo_channel_del(pevo);
		return ret;
	}

	evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
			    NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
	if (!evo->user) {
		NV_ERROR(dev, "Error mapping EVO control regs.\n");
		nv50_evo_channel_del(pevo);
		return -ENOMEM;
	}

	/* bind primary evo channel's ramht to the channel */
	if (disp->master && evo != disp->master)
		nouveau_ramht_ref(disp->master->ramht, &evo->ramht, NULL);

	return 0;
}

static int
nv50_evo_channel_init(struct nouveau_channel *evo)
{
	struct drm_device *dev = evo->dev;
	int id = evo->id, ret, i;
	u64 pushbuf = evo->pushbuf_bo->bo.offset;
	u32 tmp;

	tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
	if ((tmp & 0x009f0000) == 0x00020000)
		nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00800000);

	tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
	if ((tmp & 0x003f0000) == 0x00030000)
		nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp | 0x00600000);

	/* initialise fifo */
	nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 |
		     NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM |
		     NV50_PDISPLAY_EVO_DMA_CB_VALID);
	nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
	nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
	nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
		     NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);

	nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 |
		     NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
		NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id,
			 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
		return -EBUSY;
	}

	/* enable error reporting on the channel */
	nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);

	evo->dma.max = (4096/4) - 2;
	evo->dma.max &= ~7;
	evo->dma.put = 0;
	evo->dma.cur = evo->dma.put;
	evo->dma.free = evo->dma.max - evo->dma.cur;

	ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
	if (ret)
		return ret;

	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
		OUT_RING(evo, 0);

	return 0;
}

static void
nv50_evo_channel_fini(struct nouveau_channel *evo)
{
	struct drm_device *dev = evo->dev;
	int id = evo->id;

	nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000);
	nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
	nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id));
	nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
		NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id,
			 nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
	}
}

void
nv50_evo_destroy(struct drm_device *dev)
{
	struct nv50_display *disp = nv50_display(dev);
	int i;

	for (i = 0; i < 2; i++) {
		if (disp->crtc[i].sem.bo) {
			nouveau_bo_unmap(disp->crtc[i].sem.bo);
			nouveau_bo_ref(NULL, &disp->crtc[i].sem.bo);
		}
		nv50_evo_channel_del(&disp->crtc[i].sync);
	}
	nouveau_gpuobj_ref(NULL, &disp->ntfy);
	nv50_evo_channel_del(&disp->master);
}

int
nv50_evo_create(struct drm_device *dev)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;
	struct nv50_display *disp = nv50_display(dev);
	struct nouveau_gpuobj *ramht = NULL;
	struct nouveau_channel *evo;
	int ret, i, j;

	/* create primary evo channel, the one we use for modesetting
	 * purporses
	 */
	ret = nv50_evo_channel_new(dev, 0, &disp->master);
	if (ret)
		return ret;
	evo = disp->master;

	/* setup object management on it, any other evo channel will
	 * use this also as there's no per-channel support on the
	 * hardware
	 */
	ret = nouveau_gpuobj_new(dev, NULL, 32768, 65536,
				 NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
	if (ret) {
		NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
		goto err;
	}

	ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
	if (ret) {
		NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
		goto err;
	}

	ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
	if (ret) {
		NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
		goto err;
	}

	ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
	nouveau_gpuobj_ref(NULL, &ramht);
	if (ret)
		goto err;

	/* not sure exactly what this is..
	 *
	 * the first dword of the structure is used by nvidia to wait on
	 * full completion of an EVO "update" command.
	 *
	 * method 0x8c on the master evo channel will fill a lot more of
	 * this structure with some undefined info
	 */
	ret = nouveau_gpuobj_new(dev, disp->master, 0x1000, 0,
				 NVOBJ_FLAG_ZERO_ALLOC, &disp->ntfy);
	if (ret)
		goto err;

	ret = nv50_evo_dmaobj_new(disp->master, NvEvoSync, 0x0000,
				  disp->ntfy->vinst, disp->ntfy->size, NULL);
	if (ret)
		goto err;

	/* create some default objects for the scanout memtypes we support */
	ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000,
				  0, dev_priv->vram_size, NULL);
	if (ret)
		goto err;

	ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000,
				  0, dev_priv->vram_size, NULL);
	if (ret)
		goto err;

	ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 |
				  (dev_priv->chipset < 0xc0 ? 0x7a00 : 0xfe00),
				  0, dev_priv->vram_size, NULL);
	if (ret)
		goto err;

	ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 |
				  (dev_priv->chipset < 0xc0 ? 0x7000 : 0xfe00),
				  0, dev_priv->vram_size, NULL);
	if (ret)
		goto err;

	/* create "display sync" channels and other structures we need
	 * to implement page flipping
	 */
	for (i = 0; i < 2; i++) {
		struct nv50_display_crtc *dispc = &disp->crtc[i];
		u64 offset;

		ret = nv50_evo_channel_new(dev, 1 + i, &dispc->sync);
		if (ret)
			goto err;

		ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
				     0, 0x0000, NULL, &dispc->sem.bo);
		if (!ret) {
			ret = nouveau_bo_pin(dispc->sem.bo, TTM_PL_FLAG_VRAM);
			if (!ret)
				ret = nouveau_bo_map(dispc->sem.bo);
			if (ret)
				nouveau_bo_ref(NULL, &dispc->sem.bo);
			offset = dispc->sem.bo->bo.offset;
		}

		if (ret)
			goto err;

		ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoSync, 0x0000,
					  offset, 4096, NULL);
		if (ret)
			goto err;

		ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000,
					  0, dev_priv->vram_size, NULL);
		if (ret)
			goto err;

		ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 |
					  (dev_priv->chipset < 0xc0 ?
					  0x7a00 : 0xfe00),
					  0, dev_priv->vram_size, NULL);
		if (ret)
			goto err;

		ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 |
					  (dev_priv->chipset < 0xc0 ?
					  0x7000 : 0xfe00),
					  0, dev_priv->vram_size, NULL);
		if (ret)
			goto err;

		for (j = 0; j < 4096; j += 4)
			nouveau_bo_wr32(dispc->sem.bo, j / 4, 0x74b1e000);
		dispc->sem.offset = 0;
	}

	return 0;

err:
	nv50_evo_destroy(dev);
	return ret;
}

int
nv50_evo_init(struct drm_device *dev)
{
	struct nv50_display *disp = nv50_display(dev);
	int ret, i;

	ret = nv50_evo_channel_init(disp->master);
	if (ret)
		return ret;

	for (i = 0; i < 2; i++) {
		ret = nv50_evo_channel_init(disp->crtc[i].sync);
		if (ret)
			return ret;
	}

	return 0;
}

void
nv50_evo_fini(struct drm_device *dev)
{
	struct nv50_display *disp = nv50_display(dev);
	int i;

	for (i = 0; i < 2; i++) {
		if (disp->crtc[i].sync)
			nv50_evo_channel_fini(disp->crtc[i].sync);
	}

	if (disp->master)
		nv50_evo_channel_fini(disp->master);
}
Commit	Line	Data
b7bc613a BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
	26
	27	#include "nouveau_drv.h"
	28	#include "nouveau_dma.h"
	29	#include "nouveau_ramht.h"
ef8389a8	30	#include "nv50_display.h"
b7bc613a BS	31
b7bc613a BS	32	static void
1e96268a	33	nv50_evo_channel_del(struct nouveau_channel **pevo)
b7bc613a	34	{
1e96268a	35	struct nouveau_channel evo = pevo;
b7bc613a	36
1e96268a	37	if (!evo)
b7bc613a	38	return;
1e96268a	39	*pevo = NULL;
b7bc613a	40
b7cb6c01	41	nouveau_ramht_ref(NULL, &evo->ramht, evo);
1e96268a BS	42	nouveau_gpuobj_channel_takedown(evo);
	43	nouveau_bo_unmap(evo->pushbuf_bo);
	44	nouveau_bo_ref(NULL, &evo->pushbuf_bo);
b7bc613a	45
1e96268a BS	46	if (evo->user)
	47	iounmap(evo->user);
	48
	49	kfree(evo);
b7bc613a BS	50	}
b7bc613a BS	51
292deb7a BS	52	void
	53	nv50_evo_dmaobj_init(struct nouveau_gpuobj *obj, u32 memtype, u64 base, u64 size)
	54	{
	55	struct drm_nouveau_private *dev_priv = obj->dev->dev_private;
	56	u32 flags5;
	57
	58	if (dev_priv->chipset < 0xc0) {
	59	/* not supported on 0x50, specified in format mthd */
	60	if (dev_priv->chipset == 0x50)
	61	memtype = 0;
	62	flags5 = 0x00010000;
	63	} else {
	64	if (memtype & 0x80000000)
	65	flags5 = 0x00000000; /* large pages */
	66	else
	67	flags5 = 0x00020000;
	68	}
	69
	70	nv50_gpuobj_dma_init(obj, 0, 0x3d, base, size, NV_MEM_TARGET_VRAM,
	71	NV_MEM_ACCESS_RW, (memtype >> 8) & 0xff, 0);
	72	nv_wo32(obj, 0x14, flags5);
	73	dev_priv->engine.instmem.flush(obj->dev);
	74	}
	75
b7bc613a	76	int
292deb7a BS	77	nv50_evo_dmaobj_new(struct nouveau_channel *evo, u32 handle, u32 memtype,
292deb7a BS	78	u64 base, u64 size, struct nouveau_gpuobj **pobj)
b7bc613a	79	{
ef8389a8	80	struct nv50_display *disp = nv50_display(evo->dev);
b7bc613a BS	81	struct nouveau_gpuobj *obj = NULL;
	82	int ret;
	83
59c0f578	84	ret = nouveau_gpuobj_new(evo->dev, disp->master, 6*4, 32, 0, &obj);
b7bc613a BS	85	if (ret)
	86	return ret;
	87	obj->engine = NVOBJ_ENGINE_DISPLAY;
	88
292deb7a	89	nv50_evo_dmaobj_init(obj, memtype, base, size);
b7bc613a	90
292deb7a BS	91	ret = nouveau_ramht_insert(evo, handle, obj);
	92	if (ret)
	93	goto out;
b7bc613a	94
292deb7a BS	95	if (pobj)
	96	nouveau_gpuobj_ref(obj, pobj);
	97	out:
	98	nouveau_gpuobj_ref(NULL, &obj);
	99	return ret;
b7bc613a BS	100	}
	101
	102	static int
30d81817 BS	103	nv50_evo_channel_new(struct drm_device *dev, int chid,
30d81817 BS	104	struct nouveau_channel **pevo)
b7bc613a	105	{
ef8389a8	106	struct nv50_display *disp = nv50_display(dev);
1e96268a	107	struct nouveau_channel *evo;
b7bc613a BS	108	int ret;
b7bc613a BS	109
1e96268a BS	110	evo = kzalloc(sizeof(struct nouveau_channel), GFP_KERNEL);
1e96268a BS	111	if (!evo)
b7bc613a	112	return -ENOMEM;
1e96268a	113	*pevo = evo;
b7bc613a	114
30d81817	115	evo->id = chid;
1e96268a BS	116	evo->dev = dev;
	117	evo->user_get = 4;
	118	evo->user_put = 0;
b7bc613a	119
22b33e8e	120	ret = nouveau_bo_new(dev, 4096, 0, TTM_PL_FLAG_VRAM, 0, 0, NULL,
d550c41e	121	&evo->pushbuf_bo);
b7bc613a	122	if (ret == 0)
1e96268a	123	ret = nouveau_bo_pin(evo->pushbuf_bo, TTM_PL_FLAG_VRAM);
b7bc613a BS	124	if (ret) {
b7bc613a BS	125	NV_ERROR(dev, "Error creating EVO DMA push buffer: %d\n", ret);
1e96268a	126	nv50_evo_channel_del(pevo);
b7bc613a BS	127	return ret;
	128	}
	129
1e96268a	130	ret = nouveau_bo_map(evo->pushbuf_bo);
b7bc613a BS	131	if (ret) {
b7bc613a BS	132	NV_ERROR(dev, "Error mapping EVO DMA push buffer: %d\n", ret);
1e96268a	133	nv50_evo_channel_del(pevo);
b7bc613a BS	134	return ret;
	135	}
	136
1e96268a BS	137	evo->user = ioremap(pci_resource_start(dev->pdev, 0) +
	138	NV50_PDISPLAY_USER(evo->id), PAGE_SIZE);
	139	if (!evo->user) {
b7bc613a	140	NV_ERROR(dev, "Error mapping EVO control regs.\n");
1e96268a	141	nv50_evo_channel_del(pevo);
b7bc613a BS	142	return -ENOMEM;
	143	}
	144
1e96268a	145	/* bind primary evo channel's ramht to the channel */
59c0f578 BS	146	if (disp->master && evo != disp->master)
59c0f578 BS	147	nouveau_ramht_ref(disp->master->ramht, &evo->ramht, NULL);
1e96268a	148
b7bc613a BS	149	return 0;
	150	}
	151
	152	static int
	153	nv50_evo_channel_init(struct nouveau_channel *evo)
	154	{
b7bc613a	155	struct drm_device *dev = evo->dev;
1e96268a	156	int id = evo->id, ret, i;
180cc306	157	u64 pushbuf = evo->pushbuf_bo->bo.offset;
b7bc613a BS	158	u32 tmp;
b7bc613a BS	159
43ce028f BS	160	tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
	161	if ((tmp & 0x009f0000) == 0x00020000)
	162	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp \| 0x00800000);
b7bc613a	163
43ce028f BS	164	tmp = nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id));
	165	if ((tmp & 0x003f0000) == 0x00030000)
	166	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), tmp \| 0x00600000);
b7bc613a BS	167
b7bc613a BS	168	/* initialise fifo */
43ce028f BS	169	nv_wr32(dev, NV50_PDISPLAY_EVO_DMA_CB(id), pushbuf >> 8 \|
	170	NV50_PDISPLAY_EVO_DMA_CB_LOCATION_VRAM \|
	171	NV50_PDISPLAY_EVO_DMA_CB_VALID);
1e96268a BS	172	nv_wr32(dev, NV50_PDISPLAY_EVO_UNK2(id), 0x00010000);
1e96268a BS	173	nv_wr32(dev, NV50_PDISPLAY_EVO_HASH_TAG(id), id);
43ce028f BS	174	nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), NV50_PDISPLAY_EVO_CTRL_DMA,
	175	NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
	176
	177	nv_wr32(dev, NV50_PDISPLAY_USER_PUT(id), 0x00000000);
	178	nv_wr32(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x01000003 \|
	179	NV50_PDISPLAY_EVO_CTRL_DMA_ENABLED);
1e96268a	180	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x80000000, 0x00000000)) {
43ce028f	181	NV_ERROR(dev, "EvoCh %d init timeout: 0x%08x\n", id,
1e96268a	182	nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
b7bc613a BS	183	return -EBUSY;
b7bc613a BS	184	}
b7bc613a BS	185
b7bc613a BS	186	/* enable error reporting on the channel */
1e96268a	187	nv_mask(dev, 0x610028, 0x00000000, 0x00010001 << id);
b7bc613a BS	188
b7bc613a BS	189	evo->dma.max = (4096/4) - 2;
59197c02	190	evo->dma.max &= ~7;
b7bc613a BS	191	evo->dma.put = 0;
	192	evo->dma.cur = evo->dma.put;
	193	evo->dma.free = evo->dma.max - evo->dma.cur;
	194
	195	ret = RING_SPACE(evo, NOUVEAU_DMA_SKIPS);
	196	if (ret)
	197	return ret;
	198
	199	for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
	200	OUT_RING(evo, 0);
	201
	202	return 0;
	203	}
	204
	205	static void
	206	nv50_evo_channel_fini(struct nouveau_channel *evo)
	207	{
	208	struct drm_device *dev = evo->dev;
43ce028f BS	209	int id = evo->id;
	210
	211	nv_mask(dev, 0x610028, 0x00010001 << id, 0x00000000);
	212	nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00001010, 0x00001000);
	213	nv_wr32(dev, NV50_PDISPLAY_INTR_0, (1 << id));
	214	nv_mask(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x00000003, 0x00000000);
	215	if (!nv_wait(dev, NV50_PDISPLAY_EVO_CTRL(id), 0x001e0000, 0x00000000)) {
	216	NV_ERROR(dev, "EvoCh %d takedown timeout: 0x%08x\n", id,
	217	nv_rd32(dev, NV50_PDISPLAY_EVO_CTRL(id)));
1e96268a BS	218	}
	219	}
	220
1772fcc6	221	void
33f409df BS	222	nv50_evo_destroy(struct drm_device *dev)
	223	{
	224	struct nv50_display *disp = nv50_display(dev);
cdccc70e BS	225	int i;
	226
	227	for (i = 0; i < 2; i++) {
	228	if (disp->crtc[i].sem.bo) {
	229	nouveau_bo_unmap(disp->crtc[i].sem.bo);
	230	nouveau_bo_ref(NULL, &disp->crtc[i].sem.bo);
	231	}
	232	nv50_evo_channel_del(&disp->crtc[i].sync);
	233	}
60f60bf1	234	nouveau_gpuobj_ref(NULL, &disp->ntfy);
33f409df BS	235	nv50_evo_channel_del(&disp->master);
	236	}
	237
1772fcc6	238	int
1e96268a BS	239	nv50_evo_create(struct drm_device *dev)
	240	{
	241	struct drm_nouveau_private *dev_priv = dev->dev_private;
ef8389a8	242	struct nv50_display *disp = nv50_display(dev);
1e96268a BS	243	struct nouveau_gpuobj *ramht = NULL;
1e96268a BS	244	struct nouveau_channel *evo;
cdccc70e	245	int ret, i, j;
1e96268a BS	246
	247	/* create primary evo channel, the one we use for modesetting
	248	* purporses
	249	*/
30d81817	250	ret = nv50_evo_channel_new(dev, 0, &disp->master);
1e96268a BS	251	if (ret)
1e96268a BS	252	return ret;
59c0f578	253	evo = disp->master;
1e96268a BS	254
	255	/* setup object management on it, any other evo channel will
	256	* use this also as there's no per-channel support on the
	257	* hardware
	258	*/
8888cb18	259	ret = nouveau_gpuobj_new(dev, NULL, 32768, 65536,
1e96268a BS	260	NVOBJ_FLAG_ZERO_ALLOC, &evo->ramin);
	261	if (ret) {
	262	NV_ERROR(dev, "Error allocating EVO channel memory: %d\n", ret);
33f409df	263	goto err;
1e96268a BS	264	}
	265
	266	ret = drm_mm_init(&evo->ramin_heap, 0, 32768);
	267	if (ret) {
	268	NV_ERROR(dev, "Error initialising EVO PRAMIN heap: %d\n", ret);
33f409df	269	goto err;
1e96268a BS	270	}
	271
	272	ret = nouveau_gpuobj_new(dev, evo, 4096, 16, 0, &ramht);
	273	if (ret) {
	274	NV_ERROR(dev, "Unable to allocate EVO RAMHT: %d\n", ret);
33f409df	275	goto err;
1e96268a BS	276	}
	277
	278	ret = nouveau_ramht_new(dev, ramht, &evo->ramht);
	279	nouveau_gpuobj_ref(NULL, &ramht);
33f409df BS	280	if (ret)
33f409df BS	281	goto err;
1e96268a	282
60f60bf1 BS	283	/* not sure exactly what this is..
	284	*
	285	* the first dword of the structure is used by nvidia to wait on
	286	* full completion of an EVO "update" command.
	287	*
	288	* method 0x8c on the master evo channel will fill a lot more of
	289	* this structure with some undefined info
	290	*/
	291	ret = nouveau_gpuobj_new(dev, disp->master, 0x1000, 0,
	292	NVOBJ_FLAG_ZERO_ALLOC, &disp->ntfy);
	293	if (ret)
	294	goto err;
	295
292deb7a BS	296	ret = nv50_evo_dmaobj_new(disp->master, NvEvoSync, 0x0000,
292deb7a BS	297	disp->ntfy->vinst, disp->ntfy->size, NULL);
60f60bf1 BS	298	if (ret)
	299	goto err;
	300
1e96268a	301	/* create some default objects for the scanout memtypes we support */
292deb7a BS	302	ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM, 0x0000,
	303	0, dev_priv->vram_size, NULL);
	304	if (ret)
	305	goto err;
1e96268a	306
292deb7a BS	307	ret = nv50_evo_dmaobj_new(disp->master, NvEvoVRAM_LP, 0x80000000,
	308	0, dev_priv->vram_size, NULL);
	309	if (ret)
	310	goto err;
1e96268a	311
292deb7a BS	312	ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB32, 0x80000000 \|
	313	(dev_priv->chipset < 0xc0 ? 0x7a00 : 0xfe00),
	314	0, dev_priv->vram_size, NULL);
	315	if (ret)
	316	goto err;
6d86951a	317
292deb7a BS	318	ret = nv50_evo_dmaobj_new(disp->master, NvEvoFB16, 0x80000000 \|
	319	(dev_priv->chipset < 0xc0 ? 0x7000 : 0xfe00),
	320	0, dev_priv->vram_size, NULL);
	321	if (ret)
	322	goto err;
1e96268a	323
cdccc70e BS	324	/* create "display sync" channels and other structures we need
	325	* to implement page flipping
	326	*/
	327	for (i = 0; i < 2; i++) {
	328	struct nv50_display_crtc *dispc = &disp->crtc[i];
	329	u64 offset;
	330
	331	ret = nv50_evo_channel_new(dev, 1 + i, &dispc->sync);
	332	if (ret)
	333	goto err;
	334
7375c95b	335	ret = nouveau_bo_new(dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
22b33e8e	336	0, 0x0000, NULL, &dispc->sem.bo);
cdccc70e	337	if (!ret) {
cdccc70e BS	338	ret = nouveau_bo_pin(dispc->sem.bo, TTM_PL_FLAG_VRAM);
	339	if (!ret)
	340	ret = nouveau_bo_map(dispc->sem.bo);
	341	if (ret)
	342	nouveau_bo_ref(NULL, &dispc->sem.bo);
180cc306	343	offset = dispc->sem.bo->bo.offset;
cdccc70e BS	344	}
	345
	346	if (ret)
	347	goto err;
	348
	349	ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoSync, 0x0000,
	350	offset, 4096, NULL);
	351	if (ret)
	352	goto err;
	353
	354	ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoVRAM_LP, 0x80000000,
	355	0, dev_priv->vram_size, NULL);
	356	if (ret)
	357	goto err;
	358
	359	ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB32, 0x80000000 \|
	360	(dev_priv->chipset < 0xc0 ?
	361	0x7a00 : 0xfe00),
	362	0, dev_priv->vram_size, NULL);
	363	if (ret)
	364	goto err;
	365
	366	ret = nv50_evo_dmaobj_new(dispc->sync, NvEvoFB16, 0x80000000 \|
	367	(dev_priv->chipset < 0xc0 ?
	368	0x7000 : 0xfe00),
	369	0, dev_priv->vram_size, NULL);
	370	if (ret)
	371	goto err;
	372
	373	for (j = 0; j < 4096; j += 4)
	374	nouveau_bo_wr32(dispc->sem.bo, j / 4, 0x74b1e000);
	375	dispc->sem.offset = 0;
	376	}
	377
1e96268a	378	return 0;
33f409df BS	379
	380	err:
	381	nv50_evo_destroy(dev);
	382	return ret;
b7bc613a BS	383	}
	384
	385	int
	386	nv50_evo_init(struct drm_device *dev)
	387	{
ef8389a8	388	struct nv50_display *disp = nv50_display(dev);
cdccc70e	389	int ret, i;
b7bc613a	390
cdccc70e BS	391	ret = nv50_evo_channel_init(disp->master);
	392	if (ret)
	393	return ret;
	394
	395	for (i = 0; i < 2; i++) {
	396	ret = nv50_evo_channel_init(disp->crtc[i].sync);
	397	if (ret)
	398	return ret;
	399	}
	400
	401	return 0;
b7bc613a BS	402	}
	403
	404	void
	405	nv50_evo_fini(struct drm_device *dev)
	406	{
ef8389a8	407	struct nv50_display *disp = nv50_display(dev);
cdccc70e BS	408	int i;
	409
	410	for (i = 0; i < 2; i++) {
	411	if (disp->crtc[i].sync)
	412	nv50_evo_channel_fini(disp->crtc[i].sync);
	413	}
b7bc613a	414
33f409df	415	if (disp->master)
59c0f578	416	nv50_evo_channel_fini(disp->master);
b7bc613a	417	}