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f589be88 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs <bskeggs@redhat.com> | |
23 | */ | |
24 | ||
ebb945a9 BS |
25 | #include <core/object.h> |
26 | #include <core/class.h> | |
27 | ||
28 | #include "nouveau_drm.h" | |
f589be88 | 29 | #include "nouveau_dma.h" |
a4cea27b | 30 | #include "nv10_fence.h" |
f589be88 | 31 | |
77145f1c BS |
32 | #include "nv50_display.h" |
33 | ||
f589be88 BS |
34 | static int |
35 | nv50_fence_context_new(struct nouveau_channel *chan) | |
36 | { | |
77145f1c | 37 | struct drm_device *dev = chan->drm->dev; |
a4cea27b MS |
38 | struct nv10_fence_priv *priv = chan->drm->fence; |
39 | struct nv10_fence_chan *fctx; | |
f589be88 | 40 | struct ttm_mem_reg *mem = &priv->bo->bo.mem; |
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41 | struct nouveau_object *object; |
42 | int ret, i; | |
f589be88 BS |
43 | |
44 | fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL); | |
45 | if (!fctx) | |
46 | return -ENOMEM; | |
47 | ||
48 | nouveau_fence_context_new(&fctx->base); | |
827520ce BS |
49 | fctx->base.emit = nv10_fence_emit; |
50 | fctx->base.read = nv10_fence_read; | |
51 | fctx->base.sync = nv17_fence_sync; | |
f589be88 | 52 | |
ebb945a9 BS |
53 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, |
54 | NvSema, 0x0002, | |
55 | &(struct nv_dma_class) { | |
56 | .flags = NV_DMA_TARGET_VRAM | | |
57 | NV_DMA_ACCESS_RDWR, | |
58 | .start = mem->start * PAGE_SIZE, | |
59 | .limit = mem->size - 1, | |
60 | }, sizeof(struct nv_dma_class), | |
61 | &object); | |
f589be88 BS |
62 | |
63 | /* dma objects for display sync channel semaphore blocks */ | |
77145f1c | 64 | for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) { |
e225f446 | 65 | struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i); |
ebb945a9 BS |
66 | |
67 | ret = nouveau_object_new(nv_object(chan->cli), chan->handle, | |
68 | NvEvoSema0 + i, 0x003d, | |
69 | &(struct nv_dma_class) { | |
70 | .flags = NV_DMA_TARGET_VRAM | | |
71 | NV_DMA_ACCESS_RDWR, | |
72 | .start = bo->bo.offset, | |
73 | .limit = bo->bo.offset + 0xfff, | |
74 | }, sizeof(struct nv_dma_class), | |
75 | &object); | |
f589be88 BS |
76 | } |
77 | ||
78 | if (ret) | |
79 | nv10_fence_context_del(chan); | |
80 | return ret; | |
81 | } | |
82 | ||
83 | int | |
ebb945a9 | 84 | nv50_fence_create(struct nouveau_drm *drm) |
f589be88 | 85 | { |
a4cea27b | 86 | struct nv10_fence_priv *priv; |
f589be88 BS |
87 | int ret = 0; |
88 | ||
ebb945a9 | 89 | priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL); |
f589be88 BS |
90 | if (!priv) |
91 | return -ENOMEM; | |
92 | ||
93 | priv->base.dtor = nv10_fence_destroy; | |
827520ce | 94 | priv->base.resume = nv17_fence_resume; |
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95 | priv->base.context_new = nv50_fence_context_new; |
96 | priv->base.context_del = nv10_fence_context_del; | |
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97 | spin_lock_init(&priv->lock); |
98 | ||
ebb945a9 | 99 | ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM, |
f589be88 BS |
100 | 0, 0x0000, NULL, &priv->bo); |
101 | if (!ret) { | |
102 | ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM); | |
04c8c210 | 103 | if (!ret) { |
f589be88 | 104 | ret = nouveau_bo_map(priv->bo); |
04c8c210 MS |
105 | if (ret) |
106 | nouveau_bo_unpin(priv->bo); | |
107 | } | |
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108 | if (ret) |
109 | nouveau_bo_ref(NULL, &priv->bo); | |
110 | } | |
111 | ||
827520ce BS |
112 | if (ret) { |
113 | nv10_fence_destroy(drm); | |
114 | return ret; | |
ebb945a9 BS |
115 | } |
116 | ||
827520ce | 117 | nouveau_bo_wr32(priv->bo, 0x000, 0x00000000); |
f589be88 BS |
118 | return ret; |
119 | } |