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d5f3c90d MK |
1 | /* |
2 | * Copyright 2009 Marcin Kościelnicki | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | */ | |
22 | ||
23 | #define CP_FLAG_CLEAR 0 | |
24 | #define CP_FLAG_SET 1 | |
25 | #define CP_FLAG_SWAP_DIRECTION ((0 * 32) + 0) | |
26 | #define CP_FLAG_SWAP_DIRECTION_LOAD 0 | |
27 | #define CP_FLAG_SWAP_DIRECTION_SAVE 1 | |
28 | #define CP_FLAG_UNK01 ((0 * 32) + 1) | |
29 | #define CP_FLAG_UNK01_CLEAR 0 | |
30 | #define CP_FLAG_UNK01_SET 1 | |
31 | #define CP_FLAG_UNK03 ((0 * 32) + 3) | |
32 | #define CP_FLAG_UNK03_CLEAR 0 | |
33 | #define CP_FLAG_UNK03_SET 1 | |
34 | #define CP_FLAG_USER_SAVE ((0 * 32) + 5) | |
35 | #define CP_FLAG_USER_SAVE_NOT_PENDING 0 | |
36 | #define CP_FLAG_USER_SAVE_PENDING 1 | |
37 | #define CP_FLAG_USER_LOAD ((0 * 32) + 6) | |
38 | #define CP_FLAG_USER_LOAD_NOT_PENDING 0 | |
39 | #define CP_FLAG_USER_LOAD_PENDING 1 | |
40 | #define CP_FLAG_UNK0B ((0 * 32) + 0xb) | |
41 | #define CP_FLAG_UNK0B_CLEAR 0 | |
42 | #define CP_FLAG_UNK0B_SET 1 | |
43 | #define CP_FLAG_UNK1D ((0 * 32) + 0x1d) | |
44 | #define CP_FLAG_UNK1D_CLEAR 0 | |
45 | #define CP_FLAG_UNK1D_SET 1 | |
46 | #define CP_FLAG_UNK20 ((1 * 32) + 0) | |
47 | #define CP_FLAG_UNK20_CLEAR 0 | |
48 | #define CP_FLAG_UNK20_SET 1 | |
49 | #define CP_FLAG_STATUS ((2 * 32) + 0) | |
50 | #define CP_FLAG_STATUS_BUSY 0 | |
51 | #define CP_FLAG_STATUS_IDLE 1 | |
52 | #define CP_FLAG_AUTO_SAVE ((2 * 32) + 4) | |
53 | #define CP_FLAG_AUTO_SAVE_NOT_PENDING 0 | |
54 | #define CP_FLAG_AUTO_SAVE_PENDING 1 | |
55 | #define CP_FLAG_AUTO_LOAD ((2 * 32) + 5) | |
56 | #define CP_FLAG_AUTO_LOAD_NOT_PENDING 0 | |
57 | #define CP_FLAG_AUTO_LOAD_PENDING 1 | |
0dd8c3f0 MK |
58 | #define CP_FLAG_NEWCTX ((2 * 32) + 10) |
59 | #define CP_FLAG_NEWCTX_BUSY 0 | |
60 | #define CP_FLAG_NEWCTX_DONE 1 | |
d5f3c90d MK |
61 | #define CP_FLAG_XFER ((2 * 32) + 11) |
62 | #define CP_FLAG_XFER_IDLE 0 | |
63 | #define CP_FLAG_XFER_BUSY 1 | |
d5f3c90d MK |
64 | #define CP_FLAG_ALWAYS ((2 * 32) + 13) |
65 | #define CP_FLAG_ALWAYS_FALSE 0 | |
66 | #define CP_FLAG_ALWAYS_TRUE 1 | |
3bf777bf MK |
67 | #define CP_FLAG_INTR ((2 * 32) + 15) |
68 | #define CP_FLAG_INTR_NOT_PENDING 0 | |
69 | #define CP_FLAG_INTR_PENDING 1 | |
d5f3c90d MK |
70 | |
71 | #define CP_CTX 0x00100000 | |
72 | #define CP_CTX_COUNT 0x000f0000 | |
73 | #define CP_CTX_COUNT_SHIFT 16 | |
74 | #define CP_CTX_REG 0x00003fff | |
75 | #define CP_LOAD_SR 0x00200000 | |
76 | #define CP_LOAD_SR_VALUE 0x000fffff | |
77 | #define CP_BRA 0x00400000 | |
78 | #define CP_BRA_IP 0x0001ff00 | |
79 | #define CP_BRA_IP_SHIFT 8 | |
80 | #define CP_BRA_IF_CLEAR 0x00000080 | |
81 | #define CP_BRA_FLAG 0x0000007f | |
82 | #define CP_WAIT 0x00500000 | |
83 | #define CP_WAIT_SET 0x00000080 | |
84 | #define CP_WAIT_FLAG 0x0000007f | |
85 | #define CP_SET 0x00700000 | |
86 | #define CP_SET_1 0x00000080 | |
87 | #define CP_SET_FLAG 0x0000007f | |
88 | #define CP_NEWCTX 0x00600004 | |
89 | #define CP_NEXT_TO_SWAP 0x00600005 | |
90 | #define CP_SET_CONTEXT_POINTER 0x00600006 | |
91 | #define CP_SET_XFER_POINTER 0x00600007 | |
92 | #define CP_ENABLE 0x00600009 | |
93 | #define CP_END 0x0060000c | |
94 | #define CP_NEXT_TO_CURRENT 0x0060000d | |
95 | #define CP_DISABLE1 0x0090ffff | |
96 | #define CP_DISABLE2 0x0091ffff | |
97 | #define CP_XFER_1 0x008000ff | |
98 | #define CP_XFER_2 0x008800ff | |
99 | #define CP_SEEK_1 0x00c000ff | |
100 | #define CP_SEEK_2 0x00c800ff | |
101 | ||
102 | #include "drmP.h" | |
103 | #include "nouveau_drv.h" | |
104 | #include "nouveau_grctx.h" | |
105 | ||
106 | /* | |
107 | * This code deals with PGRAPH contexts on NV50 family cards. Like NV40, it's | |
108 | * the GPU itself that does context-switching, but it needs a special | |
109 | * microcode to do it. And it's the driver's task to supply this microcode, | |
110 | * further known as ctxprog, as well as the initial context values, known | |
111 | * as ctxvals. | |
112 | * | |
113 | * Without ctxprog, you cannot switch contexts. Not even in software, since | |
114 | * the majority of context [xfer strands] isn't accessible directly. You're | |
115 | * stuck with a single channel, and you also suffer all the problems resulting | |
116 | * from missing ctxvals, since you cannot load them. | |
117 | * | |
118 | * Without ctxvals, you're stuck with PGRAPH's default context. It's enough to | |
119 | * run 2d operations, but trying to utilise 3d or CUDA will just lock you up, | |
120 | * since you don't have... some sort of needed setup. | |
121 | * | |
122 | * Nouveau will just disable acceleration if not given ctxprog + ctxvals, since | |
123 | * it's too much hassle to handle no-ctxprog as a special case. | |
124 | */ | |
125 | ||
126 | /* | |
127 | * How ctxprogs work. | |
128 | * | |
129 | * The ctxprog is written in its own kind of microcode, with very small and | |
130 | * crappy set of available commands. You upload it to a small [512 insns] | |
131 | * area of memory on PGRAPH, and it'll be run when PFIFO wants PGRAPH to | |
132 | * switch channel. or when the driver explicitely requests it. Stuff visible | |
133 | * to ctxprog consists of: PGRAPH MMIO registers, PGRAPH context strands, | |
134 | * the per-channel context save area in VRAM [known as ctxvals or grctx], | |
135 | * 4 flags registers, a scratch register, two grctx pointers, plus many | |
136 | * random poorly-understood details. | |
137 | * | |
138 | * When ctxprog runs, it's supposed to check what operations are asked of it, | |
139 | * save old context if requested, optionally reset PGRAPH and switch to the | |
140 | * new channel, and load the new context. Context consists of three major | |
141 | * parts: subset of MMIO registers and two "xfer areas". | |
142 | */ | |
143 | ||
144 | /* TODO: | |
145 | * - document unimplemented bits compared to nvidia | |
146 | * - NVAx: make a TP subroutine, use it. | |
147 | * - use 0x4008fc instead of 0x1540? | |
148 | */ | |
149 | ||
150 | enum cp_label { | |
151 | cp_check_load = 1, | |
152 | cp_setup_auto_load, | |
153 | cp_setup_load, | |
154 | cp_setup_save, | |
155 | cp_swap_state, | |
156 | cp_prepare_exit, | |
157 | cp_exit, | |
158 | }; | |
159 | ||
160 | static void nv50_graph_construct_mmio(struct nouveau_grctx *ctx); | |
161 | static void nv50_graph_construct_xfer1(struct nouveau_grctx *ctx); | |
162 | static void nv50_graph_construct_xfer2(struct nouveau_grctx *ctx); | |
163 | ||
164 | /* Main function: construct the ctxprog skeleton, call the other functions. */ | |
165 | ||
166 | int | |
167 | nv50_grctx_init(struct nouveau_grctx *ctx) | |
168 | { | |
169 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
170 | ||
171 | switch (dev_priv->chipset) { | |
172 | case 0x50: | |
173 | case 0x84: | |
174 | case 0x86: | |
175 | case 0x92: | |
176 | case 0x94: | |
177 | case 0x96: | |
178 | case 0x98: | |
179 | case 0xa0: | |
eaeefba1 | 180 | case 0xa3: |
d5f3c90d MK |
181 | case 0xa5: |
182 | case 0xa8: | |
183 | case 0xaa: | |
184 | case 0xac: | |
185 | break; | |
186 | default: | |
187 | NV_ERROR(ctx->dev, "I don't know how to make a ctxprog for " | |
188 | "your NV%x card.\n", dev_priv->chipset); | |
189 | NV_ERROR(ctx->dev, "Disabling acceleration. Please contact " | |
190 | "the devs.\n"); | |
191 | return -ENOSYS; | |
192 | } | |
193 | /* decide whether we're loading/unloading the context */ | |
194 | cp_bra (ctx, AUTO_SAVE, PENDING, cp_setup_save); | |
195 | cp_bra (ctx, USER_SAVE, PENDING, cp_setup_save); | |
196 | ||
197 | cp_name(ctx, cp_check_load); | |
198 | cp_bra (ctx, AUTO_LOAD, PENDING, cp_setup_auto_load); | |
199 | cp_bra (ctx, USER_LOAD, PENDING, cp_setup_load); | |
200 | cp_bra (ctx, ALWAYS, TRUE, cp_exit); | |
201 | ||
202 | /* setup for context load */ | |
203 | cp_name(ctx, cp_setup_auto_load); | |
204 | cp_out (ctx, CP_DISABLE1); | |
205 | cp_out (ctx, CP_DISABLE2); | |
206 | cp_out (ctx, CP_ENABLE); | |
207 | cp_out (ctx, CP_NEXT_TO_SWAP); | |
208 | cp_set (ctx, UNK01, SET); | |
209 | cp_name(ctx, cp_setup_load); | |
210 | cp_out (ctx, CP_NEWCTX); | |
211 | cp_wait(ctx, NEWCTX, BUSY); | |
212 | cp_set (ctx, UNK1D, CLEAR); | |
213 | cp_set (ctx, SWAP_DIRECTION, LOAD); | |
214 | cp_bra (ctx, UNK0B, SET, cp_prepare_exit); | |
215 | cp_bra (ctx, ALWAYS, TRUE, cp_swap_state); | |
216 | ||
217 | /* setup for context save */ | |
218 | cp_name(ctx, cp_setup_save); | |
219 | cp_set (ctx, UNK1D, SET); | |
220 | cp_wait(ctx, STATUS, BUSY); | |
3bf777bf MK |
221 | cp_wait(ctx, INTR, PENDING); |
222 | cp_bra (ctx, STATUS, BUSY, cp_setup_save); | |
d5f3c90d MK |
223 | cp_set (ctx, UNK01, SET); |
224 | cp_set (ctx, SWAP_DIRECTION, SAVE); | |
225 | ||
226 | /* general PGRAPH state */ | |
227 | cp_name(ctx, cp_swap_state); | |
228 | cp_set (ctx, UNK03, SET); | |
229 | cp_pos (ctx, 0x00004/4); | |
230 | cp_ctx (ctx, 0x400828, 1); /* needed. otherwise, flickering happens. */ | |
231 | cp_pos (ctx, 0x00100/4); | |
232 | nv50_graph_construct_mmio(ctx); | |
233 | nv50_graph_construct_xfer1(ctx); | |
234 | nv50_graph_construct_xfer2(ctx); | |
235 | ||
236 | cp_bra (ctx, SWAP_DIRECTION, SAVE, cp_check_load); | |
237 | ||
238 | cp_set (ctx, UNK20, SET); | |
239 | cp_set (ctx, SWAP_DIRECTION, SAVE); /* no idea why this is needed, but fixes at least one lockup. */ | |
240 | cp_lsr (ctx, ctx->ctxvals_base); | |
241 | cp_out (ctx, CP_SET_XFER_POINTER); | |
242 | cp_lsr (ctx, 4); | |
243 | cp_out (ctx, CP_SEEK_1); | |
244 | cp_out (ctx, CP_XFER_1); | |
245 | cp_wait(ctx, XFER, BUSY); | |
246 | ||
247 | /* pre-exit state updates */ | |
248 | cp_name(ctx, cp_prepare_exit); | |
249 | cp_set (ctx, UNK01, CLEAR); | |
250 | cp_set (ctx, UNK03, CLEAR); | |
251 | cp_set (ctx, UNK1D, CLEAR); | |
252 | ||
253 | cp_bra (ctx, USER_SAVE, PENDING, cp_exit); | |
254 | cp_out (ctx, CP_NEXT_TO_CURRENT); | |
255 | ||
256 | cp_name(ctx, cp_exit); | |
257 | cp_set (ctx, USER_SAVE, NOT_PENDING); | |
258 | cp_set (ctx, USER_LOAD, NOT_PENDING); | |
259 | cp_out (ctx, CP_END); | |
260 | ctx->ctxvals_pos += 0x400; /* padding... no idea why you need it */ | |
261 | ||
262 | return 0; | |
263 | } | |
264 | ||
265 | /* | |
266 | * Constructs MMIO part of ctxprog and ctxvals. Just a matter of knowing which | |
267 | * registers to save/restore and the default values for them. | |
268 | */ | |
269 | ||
270 | static void | |
271 | nv50_graph_construct_mmio(struct nouveau_grctx *ctx) | |
272 | { | |
273 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
274 | int i, j; | |
275 | int offset, base; | |
276 | uint32_t units = nv_rd32 (ctx->dev, 0x1540); | |
277 | ||
304424e1 | 278 | /* 0800: DISPATCH */ |
d5f3c90d MK |
279 | cp_ctx(ctx, 0x400808, 7); |
280 | gr_def(ctx, 0x400814, 0x00000030); | |
281 | cp_ctx(ctx, 0x400834, 0x32); | |
282 | if (dev_priv->chipset == 0x50) { | |
283 | gr_def(ctx, 0x400834, 0xff400040); | |
284 | gr_def(ctx, 0x400838, 0xfff00080); | |
285 | gr_def(ctx, 0x40083c, 0xfff70090); | |
286 | gr_def(ctx, 0x400840, 0xffe806a8); | |
287 | } | |
288 | gr_def(ctx, 0x400844, 0x00000002); | |
289 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
290 | gr_def(ctx, 0x400894, 0x00001000); | |
291 | gr_def(ctx, 0x4008e8, 0x00000003); | |
292 | gr_def(ctx, 0x4008ec, 0x00001000); | |
293 | if (dev_priv->chipset == 0x50) | |
294 | cp_ctx(ctx, 0x400908, 0xb); | |
295 | else if (dev_priv->chipset < 0xa0) | |
296 | cp_ctx(ctx, 0x400908, 0xc); | |
297 | else | |
298 | cp_ctx(ctx, 0x400908, 0xe); | |
299 | ||
300 | if (dev_priv->chipset >= 0xa0) | |
301 | cp_ctx(ctx, 0x400b00, 0x1); | |
302 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
303 | cp_ctx(ctx, 0x400b10, 0x1); | |
304 | gr_def(ctx, 0x400b10, 0x0001629d); | |
305 | cp_ctx(ctx, 0x400b20, 0x1); | |
306 | gr_def(ctx, 0x400b20, 0x0001629d); | |
307 | } | |
308 | ||
304424e1 | 309 | /* 0C00: VFETCH */ |
d5f3c90d MK |
310 | cp_ctx(ctx, 0x400c08, 0x2); |
311 | gr_def(ctx, 0x400c08, 0x0000fe0c); | |
312 | ||
313 | /* 1000 */ | |
314 | if (dev_priv->chipset < 0xa0) { | |
315 | cp_ctx(ctx, 0x401008, 0x4); | |
316 | gr_def(ctx, 0x401014, 0x00001000); | |
317 | } else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa) { | |
318 | cp_ctx(ctx, 0x401008, 0x5); | |
319 | gr_def(ctx, 0x401018, 0x00001000); | |
320 | } else { | |
321 | cp_ctx(ctx, 0x401008, 0x5); | |
322 | gr_def(ctx, 0x401018, 0x00004000); | |
323 | } | |
324 | ||
325 | /* 1400 */ | |
326 | cp_ctx(ctx, 0x401400, 0x8); | |
327 | cp_ctx(ctx, 0x401424, 0x3); | |
328 | if (dev_priv->chipset == 0x50) | |
329 | gr_def(ctx, 0x40142c, 0x0001fd87); | |
330 | else | |
331 | gr_def(ctx, 0x40142c, 0x00000187); | |
332 | cp_ctx(ctx, 0x401540, 0x5); | |
333 | gr_def(ctx, 0x401550, 0x00001018); | |
334 | ||
304424e1 | 335 | /* 1800: STREAMOUT */ |
d5f3c90d MK |
336 | cp_ctx(ctx, 0x401814, 0x1); |
337 | gr_def(ctx, 0x401814, 0x000000ff); | |
338 | if (dev_priv->chipset == 0x50) { | |
339 | cp_ctx(ctx, 0x40181c, 0xe); | |
340 | gr_def(ctx, 0x401850, 0x00000004); | |
341 | } else if (dev_priv->chipset < 0xa0) { | |
342 | cp_ctx(ctx, 0x40181c, 0xf); | |
343 | gr_def(ctx, 0x401854, 0x00000004); | |
344 | } else { | |
345 | cp_ctx(ctx, 0x40181c, 0x13); | |
346 | gr_def(ctx, 0x401864, 0x00000004); | |
347 | } | |
348 | ||
349 | /* 1C00 */ | |
350 | cp_ctx(ctx, 0x401c00, 0x1); | |
351 | switch (dev_priv->chipset) { | |
352 | case 0x50: | |
353 | gr_def(ctx, 0x401c00, 0x0001005f); | |
354 | break; | |
355 | case 0x84: | |
356 | case 0x86: | |
357 | case 0x94: | |
358 | gr_def(ctx, 0x401c00, 0x044d00df); | |
359 | break; | |
360 | case 0x92: | |
361 | case 0x96: | |
362 | case 0x98: | |
363 | case 0xa0: | |
364 | case 0xaa: | |
365 | case 0xac: | |
366 | gr_def(ctx, 0x401c00, 0x042500df); | |
367 | break; | |
eaeefba1 | 368 | case 0xa3: |
d5f3c90d MK |
369 | case 0xa5: |
370 | case 0xa8: | |
371 | gr_def(ctx, 0x401c00, 0x142500df); | |
372 | break; | |
373 | } | |
374 | ||
375 | /* 2400 */ | |
376 | cp_ctx(ctx, 0x402400, 0x1); | |
377 | if (dev_priv->chipset == 0x50) | |
378 | cp_ctx(ctx, 0x402408, 0x1); | |
379 | else | |
380 | cp_ctx(ctx, 0x402408, 0x2); | |
381 | gr_def(ctx, 0x402408, 0x00000600); | |
382 | ||
383 | /* 2800 */ | |
384 | cp_ctx(ctx, 0x402800, 0x1); | |
385 | if (dev_priv->chipset == 0x50) | |
386 | gr_def(ctx, 0x402800, 0x00000006); | |
387 | ||
388 | /* 2C00 */ | |
389 | cp_ctx(ctx, 0x402c08, 0x6); | |
390 | if (dev_priv->chipset != 0x50) | |
391 | gr_def(ctx, 0x402c14, 0x01000000); | |
392 | gr_def(ctx, 0x402c18, 0x000000ff); | |
393 | if (dev_priv->chipset == 0x50) | |
394 | cp_ctx(ctx, 0x402ca0, 0x1); | |
395 | else | |
396 | cp_ctx(ctx, 0x402ca0, 0x2); | |
397 | if (dev_priv->chipset < 0xa0) | |
398 | gr_def(ctx, 0x402ca0, 0x00000400); | |
399 | else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa) | |
400 | gr_def(ctx, 0x402ca0, 0x00000800); | |
401 | else | |
402 | gr_def(ctx, 0x402ca0, 0x00000400); | |
403 | cp_ctx(ctx, 0x402cac, 0x4); | |
404 | ||
405 | /* 3000 */ | |
406 | cp_ctx(ctx, 0x403004, 0x1); | |
407 | gr_def(ctx, 0x403004, 0x00000001); | |
408 | ||
409 | /* 3404 */ | |
410 | if (dev_priv->chipset >= 0xa0) { | |
411 | cp_ctx(ctx, 0x403404, 0x1); | |
412 | gr_def(ctx, 0x403404, 0x00000001); | |
413 | } | |
414 | ||
415 | /* 5000 */ | |
416 | cp_ctx(ctx, 0x405000, 0x1); | |
417 | switch (dev_priv->chipset) { | |
418 | case 0x50: | |
419 | gr_def(ctx, 0x405000, 0x00300080); | |
420 | break; | |
421 | case 0x84: | |
422 | case 0xa0: | |
eaeefba1 | 423 | case 0xa3: |
d5f3c90d MK |
424 | case 0xa5: |
425 | case 0xa8: | |
426 | case 0xaa: | |
427 | case 0xac: | |
428 | gr_def(ctx, 0x405000, 0x000e0080); | |
429 | break; | |
430 | case 0x86: | |
431 | case 0x92: | |
432 | case 0x94: | |
433 | case 0x96: | |
434 | case 0x98: | |
435 | gr_def(ctx, 0x405000, 0x00000080); | |
436 | break; | |
437 | } | |
438 | cp_ctx(ctx, 0x405014, 0x1); | |
439 | gr_def(ctx, 0x405014, 0x00000004); | |
440 | cp_ctx(ctx, 0x40501c, 0x1); | |
441 | cp_ctx(ctx, 0x405024, 0x1); | |
442 | cp_ctx(ctx, 0x40502c, 0x1); | |
443 | ||
444 | /* 5400 or maybe 4800 */ | |
445 | if (dev_priv->chipset == 0x50) { | |
446 | offset = 0x405400; | |
447 | cp_ctx(ctx, 0x405400, 0xea); | |
448 | } else if (dev_priv->chipset < 0x94) { | |
449 | offset = 0x405400; | |
450 | cp_ctx(ctx, 0x405400, 0xcb); | |
451 | } else if (dev_priv->chipset < 0xa0) { | |
452 | offset = 0x405400; | |
453 | cp_ctx(ctx, 0x405400, 0xcc); | |
454 | } else if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
455 | offset = 0x404800; | |
456 | cp_ctx(ctx, 0x404800, 0xda); | |
457 | } else { | |
458 | offset = 0x405400; | |
459 | cp_ctx(ctx, 0x405400, 0xd4); | |
460 | } | |
461 | gr_def(ctx, offset + 0x0c, 0x00000002); | |
462 | gr_def(ctx, offset + 0x10, 0x00000001); | |
463 | if (dev_priv->chipset >= 0x94) | |
464 | offset += 4; | |
465 | gr_def(ctx, offset + 0x1c, 0x00000001); | |
466 | gr_def(ctx, offset + 0x20, 0x00000100); | |
467 | gr_def(ctx, offset + 0x38, 0x00000002); | |
468 | gr_def(ctx, offset + 0x3c, 0x00000001); | |
469 | gr_def(ctx, offset + 0x40, 0x00000001); | |
470 | gr_def(ctx, offset + 0x50, 0x00000001); | |
471 | gr_def(ctx, offset + 0x54, 0x003fffff); | |
472 | gr_def(ctx, offset + 0x58, 0x00001fff); | |
473 | gr_def(ctx, offset + 0x60, 0x00000001); | |
474 | gr_def(ctx, offset + 0x64, 0x00000001); | |
475 | gr_def(ctx, offset + 0x6c, 0x00000001); | |
476 | gr_def(ctx, offset + 0x70, 0x00000001); | |
477 | gr_def(ctx, offset + 0x74, 0x00000001); | |
478 | gr_def(ctx, offset + 0x78, 0x00000004); | |
479 | gr_def(ctx, offset + 0x7c, 0x00000001); | |
480 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
481 | offset += 4; | |
482 | gr_def(ctx, offset + 0x80, 0x00000001); | |
483 | gr_def(ctx, offset + 0x84, 0x00000001); | |
484 | gr_def(ctx, offset + 0x88, 0x00000007); | |
485 | gr_def(ctx, offset + 0x8c, 0x00000001); | |
486 | gr_def(ctx, offset + 0x90, 0x00000007); | |
487 | gr_def(ctx, offset + 0x94, 0x00000001); | |
488 | gr_def(ctx, offset + 0x98, 0x00000001); | |
489 | gr_def(ctx, offset + 0x9c, 0x00000001); | |
490 | if (dev_priv->chipset == 0x50) { | |
491 | gr_def(ctx, offset + 0xb0, 0x00000001); | |
492 | gr_def(ctx, offset + 0xb4, 0x00000001); | |
493 | gr_def(ctx, offset + 0xbc, 0x00000001); | |
494 | gr_def(ctx, offset + 0xc0, 0x0000000a); | |
495 | gr_def(ctx, offset + 0xd0, 0x00000040); | |
496 | gr_def(ctx, offset + 0xd8, 0x00000002); | |
497 | gr_def(ctx, offset + 0xdc, 0x00000100); | |
498 | gr_def(ctx, offset + 0xe0, 0x00000001); | |
499 | gr_def(ctx, offset + 0xe4, 0x00000100); | |
500 | gr_def(ctx, offset + 0x100, 0x00000001); | |
501 | gr_def(ctx, offset + 0x124, 0x00000004); | |
502 | gr_def(ctx, offset + 0x13c, 0x00000001); | |
503 | gr_def(ctx, offset + 0x140, 0x00000100); | |
504 | gr_def(ctx, offset + 0x148, 0x00000001); | |
505 | gr_def(ctx, offset + 0x154, 0x00000100); | |
506 | gr_def(ctx, offset + 0x158, 0x00000001); | |
507 | gr_def(ctx, offset + 0x15c, 0x00000100); | |
508 | gr_def(ctx, offset + 0x164, 0x00000001); | |
509 | gr_def(ctx, offset + 0x170, 0x00000100); | |
510 | gr_def(ctx, offset + 0x174, 0x00000001); | |
511 | gr_def(ctx, offset + 0x17c, 0x00000001); | |
512 | gr_def(ctx, offset + 0x188, 0x00000002); | |
513 | gr_def(ctx, offset + 0x190, 0x00000001); | |
514 | gr_def(ctx, offset + 0x198, 0x00000001); | |
515 | gr_def(ctx, offset + 0x1ac, 0x00000003); | |
516 | offset += 0xd0; | |
517 | } else { | |
518 | gr_def(ctx, offset + 0xb0, 0x00000001); | |
519 | gr_def(ctx, offset + 0xb4, 0x00000100); | |
520 | gr_def(ctx, offset + 0xbc, 0x00000001); | |
521 | gr_def(ctx, offset + 0xc8, 0x00000100); | |
522 | gr_def(ctx, offset + 0xcc, 0x00000001); | |
523 | gr_def(ctx, offset + 0xd0, 0x00000100); | |
524 | gr_def(ctx, offset + 0xd8, 0x00000001); | |
525 | gr_def(ctx, offset + 0xe4, 0x00000100); | |
526 | } | |
527 | gr_def(ctx, offset + 0xf8, 0x00000004); | |
528 | gr_def(ctx, offset + 0xfc, 0x00000070); | |
529 | gr_def(ctx, offset + 0x100, 0x00000080); | |
530 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
531 | offset += 4; | |
532 | gr_def(ctx, offset + 0x114, 0x0000000c); | |
533 | if (dev_priv->chipset == 0x50) | |
534 | offset -= 4; | |
535 | gr_def(ctx, offset + 0x11c, 0x00000008); | |
536 | gr_def(ctx, offset + 0x120, 0x00000014); | |
537 | if (dev_priv->chipset == 0x50) { | |
538 | gr_def(ctx, offset + 0x124, 0x00000026); | |
539 | offset -= 0x18; | |
540 | } else { | |
541 | gr_def(ctx, offset + 0x128, 0x00000029); | |
542 | gr_def(ctx, offset + 0x12c, 0x00000027); | |
543 | gr_def(ctx, offset + 0x130, 0x00000026); | |
544 | gr_def(ctx, offset + 0x134, 0x00000008); | |
545 | gr_def(ctx, offset + 0x138, 0x00000004); | |
546 | gr_def(ctx, offset + 0x13c, 0x00000027); | |
547 | } | |
548 | gr_def(ctx, offset + 0x148, 0x00000001); | |
549 | gr_def(ctx, offset + 0x14c, 0x00000002); | |
550 | gr_def(ctx, offset + 0x150, 0x00000003); | |
551 | gr_def(ctx, offset + 0x154, 0x00000004); | |
552 | gr_def(ctx, offset + 0x158, 0x00000005); | |
553 | gr_def(ctx, offset + 0x15c, 0x00000006); | |
554 | gr_def(ctx, offset + 0x160, 0x00000007); | |
555 | gr_def(ctx, offset + 0x164, 0x00000001); | |
556 | gr_def(ctx, offset + 0x1a8, 0x000000cf); | |
557 | if (dev_priv->chipset == 0x50) | |
558 | offset -= 4; | |
559 | gr_def(ctx, offset + 0x1d8, 0x00000080); | |
560 | gr_def(ctx, offset + 0x1dc, 0x00000004); | |
561 | gr_def(ctx, offset + 0x1e0, 0x00000004); | |
562 | if (dev_priv->chipset == 0x50) | |
563 | offset -= 4; | |
564 | else | |
565 | gr_def(ctx, offset + 0x1e4, 0x00000003); | |
566 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
567 | gr_def(ctx, offset + 0x1ec, 0x00000003); | |
568 | offset += 8; | |
569 | } | |
570 | gr_def(ctx, offset + 0x1e8, 0x00000001); | |
571 | if (dev_priv->chipset == 0x50) | |
572 | offset -= 4; | |
573 | gr_def(ctx, offset + 0x1f4, 0x00000012); | |
574 | gr_def(ctx, offset + 0x1f8, 0x00000010); | |
575 | gr_def(ctx, offset + 0x1fc, 0x0000000c); | |
576 | gr_def(ctx, offset + 0x200, 0x00000001); | |
577 | gr_def(ctx, offset + 0x210, 0x00000004); | |
578 | gr_def(ctx, offset + 0x214, 0x00000002); | |
579 | gr_def(ctx, offset + 0x218, 0x00000004); | |
580 | if (dev_priv->chipset >= 0xa0) | |
581 | offset += 4; | |
582 | gr_def(ctx, offset + 0x224, 0x003fffff); | |
583 | gr_def(ctx, offset + 0x228, 0x00001fff); | |
584 | if (dev_priv->chipset == 0x50) | |
585 | offset -= 0x20; | |
586 | else if (dev_priv->chipset >= 0xa0) { | |
587 | gr_def(ctx, offset + 0x250, 0x00000001); | |
588 | gr_def(ctx, offset + 0x254, 0x00000001); | |
589 | gr_def(ctx, offset + 0x258, 0x00000002); | |
590 | offset += 0x10; | |
591 | } | |
592 | gr_def(ctx, offset + 0x250, 0x00000004); | |
593 | gr_def(ctx, offset + 0x254, 0x00000014); | |
594 | gr_def(ctx, offset + 0x258, 0x00000001); | |
595 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
596 | offset += 4; | |
597 | gr_def(ctx, offset + 0x264, 0x00000002); | |
598 | if (dev_priv->chipset >= 0xa0) | |
599 | offset += 8; | |
600 | gr_def(ctx, offset + 0x270, 0x00000001); | |
601 | gr_def(ctx, offset + 0x278, 0x00000002); | |
602 | gr_def(ctx, offset + 0x27c, 0x00001000); | |
603 | if (dev_priv->chipset == 0x50) | |
604 | offset -= 0xc; | |
605 | else { | |
606 | gr_def(ctx, offset + 0x280, 0x00000e00); | |
607 | gr_def(ctx, offset + 0x284, 0x00001000); | |
608 | gr_def(ctx, offset + 0x288, 0x00001e00); | |
609 | } | |
610 | gr_def(ctx, offset + 0x290, 0x00000001); | |
611 | gr_def(ctx, offset + 0x294, 0x00000001); | |
612 | gr_def(ctx, offset + 0x298, 0x00000001); | |
613 | gr_def(ctx, offset + 0x29c, 0x00000001); | |
614 | gr_def(ctx, offset + 0x2a0, 0x00000001); | |
615 | gr_def(ctx, offset + 0x2b0, 0x00000200); | |
616 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
617 | gr_def(ctx, offset + 0x2b4, 0x00000200); | |
618 | offset += 4; | |
619 | } | |
620 | if (dev_priv->chipset < 0xa0) { | |
621 | gr_def(ctx, offset + 0x2b8, 0x00000001); | |
622 | gr_def(ctx, offset + 0x2bc, 0x00000070); | |
623 | gr_def(ctx, offset + 0x2c0, 0x00000080); | |
624 | gr_def(ctx, offset + 0x2cc, 0x00000001); | |
625 | gr_def(ctx, offset + 0x2d0, 0x00000070); | |
626 | gr_def(ctx, offset + 0x2d4, 0x00000080); | |
627 | } else { | |
628 | gr_def(ctx, offset + 0x2b8, 0x00000001); | |
629 | gr_def(ctx, offset + 0x2bc, 0x000000f0); | |
630 | gr_def(ctx, offset + 0x2c0, 0x000000ff); | |
631 | gr_def(ctx, offset + 0x2cc, 0x00000001); | |
632 | gr_def(ctx, offset + 0x2d0, 0x000000f0); | |
633 | gr_def(ctx, offset + 0x2d4, 0x000000ff); | |
634 | gr_def(ctx, offset + 0x2dc, 0x00000009); | |
635 | offset += 4; | |
636 | } | |
637 | gr_def(ctx, offset + 0x2e4, 0x00000001); | |
638 | gr_def(ctx, offset + 0x2e8, 0x000000cf); | |
639 | gr_def(ctx, offset + 0x2f0, 0x00000001); | |
640 | gr_def(ctx, offset + 0x300, 0x000000cf); | |
641 | gr_def(ctx, offset + 0x308, 0x00000002); | |
642 | gr_def(ctx, offset + 0x310, 0x00000001); | |
643 | gr_def(ctx, offset + 0x318, 0x00000001); | |
644 | gr_def(ctx, offset + 0x320, 0x000000cf); | |
645 | gr_def(ctx, offset + 0x324, 0x000000cf); | |
646 | gr_def(ctx, offset + 0x328, 0x00000001); | |
647 | ||
648 | /* 6000? */ | |
649 | if (dev_priv->chipset == 0x50) | |
650 | cp_ctx(ctx, 0x4063e0, 0x1); | |
651 | ||
304424e1 | 652 | /* 6800: M2MF */ |
d5f3c90d MK |
653 | if (dev_priv->chipset < 0x90) { |
654 | cp_ctx(ctx, 0x406814, 0x2b); | |
655 | gr_def(ctx, 0x406818, 0x00000f80); | |
656 | gr_def(ctx, 0x406860, 0x007f0080); | |
657 | gr_def(ctx, 0x40689c, 0x007f0080); | |
658 | } else { | |
659 | cp_ctx(ctx, 0x406814, 0x4); | |
660 | if (dev_priv->chipset == 0x98) | |
661 | gr_def(ctx, 0x406818, 0x00000f80); | |
662 | else | |
663 | gr_def(ctx, 0x406818, 0x00001f80); | |
664 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
665 | gr_def(ctx, 0x40681c, 0x00000030); | |
666 | cp_ctx(ctx, 0x406830, 0x3); | |
667 | } | |
668 | ||
669 | /* 7000: per-ROP group state */ | |
670 | for (i = 0; i < 8; i++) { | |
671 | if (units & (1<<(i+16))) { | |
672 | cp_ctx(ctx, 0x407000 + (i<<8), 3); | |
673 | if (dev_priv->chipset == 0x50) | |
674 | gr_def(ctx, 0x407000 + (i<<8), 0x1b74f820); | |
675 | else if (dev_priv->chipset != 0xa5) | |
676 | gr_def(ctx, 0x407000 + (i<<8), 0x3b74f821); | |
677 | else | |
678 | gr_def(ctx, 0x407000 + (i<<8), 0x7b74f821); | |
679 | gr_def(ctx, 0x407004 + (i<<8), 0x89058001); | |
680 | ||
681 | if (dev_priv->chipset == 0x50) { | |
682 | cp_ctx(ctx, 0x407010 + (i<<8), 1); | |
683 | } else if (dev_priv->chipset < 0xa0) { | |
684 | cp_ctx(ctx, 0x407010 + (i<<8), 2); | |
685 | gr_def(ctx, 0x407010 + (i<<8), 0x00001000); | |
686 | gr_def(ctx, 0x407014 + (i<<8), 0x0000001f); | |
687 | } else { | |
688 | cp_ctx(ctx, 0x407010 + (i<<8), 3); | |
689 | gr_def(ctx, 0x407010 + (i<<8), 0x00001000); | |
690 | if (dev_priv->chipset != 0xa5) | |
691 | gr_def(ctx, 0x407014 + (i<<8), 0x000000ff); | |
692 | else | |
693 | gr_def(ctx, 0x407014 + (i<<8), 0x000001ff); | |
694 | } | |
695 | ||
696 | cp_ctx(ctx, 0x407080 + (i<<8), 4); | |
697 | if (dev_priv->chipset != 0xa5) | |
698 | gr_def(ctx, 0x407080 + (i<<8), 0x027c10fa); | |
699 | else | |
700 | gr_def(ctx, 0x407080 + (i<<8), 0x827c10fa); | |
701 | if (dev_priv->chipset == 0x50) | |
702 | gr_def(ctx, 0x407084 + (i<<8), 0x000000c0); | |
703 | else | |
704 | gr_def(ctx, 0x407084 + (i<<8), 0x400000c0); | |
705 | gr_def(ctx, 0x407088 + (i<<8), 0xb7892080); | |
706 | ||
707 | if (dev_priv->chipset < 0xa0) | |
708 | cp_ctx(ctx, 0x407094 + (i<<8), 1); | |
709 | else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) | |
710 | cp_ctx(ctx, 0x407094 + (i<<8), 3); | |
711 | else { | |
712 | cp_ctx(ctx, 0x407094 + (i<<8), 4); | |
713 | gr_def(ctx, 0x4070a0 + (i<<8), 1); | |
714 | } | |
715 | } | |
716 | } | |
717 | ||
718 | cp_ctx(ctx, 0x407c00, 0x3); | |
719 | if (dev_priv->chipset < 0x90) | |
720 | gr_def(ctx, 0x407c00, 0x00010040); | |
721 | else if (dev_priv->chipset < 0xa0) | |
722 | gr_def(ctx, 0x407c00, 0x00390040); | |
723 | else | |
724 | gr_def(ctx, 0x407c00, 0x003d0040); | |
725 | gr_def(ctx, 0x407c08, 0x00000022); | |
726 | if (dev_priv->chipset >= 0xa0) { | |
727 | cp_ctx(ctx, 0x407c10, 0x3); | |
728 | cp_ctx(ctx, 0x407c20, 0x1); | |
729 | cp_ctx(ctx, 0x407c2c, 0x1); | |
730 | } | |
731 | ||
732 | if (dev_priv->chipset < 0xa0) { | |
733 | cp_ctx(ctx, 0x407d00, 0x9); | |
734 | } else { | |
735 | cp_ctx(ctx, 0x407d00, 0x15); | |
736 | } | |
737 | if (dev_priv->chipset == 0x98) | |
738 | gr_def(ctx, 0x407d08, 0x00380040); | |
739 | else { | |
740 | if (dev_priv->chipset < 0x90) | |
741 | gr_def(ctx, 0x407d08, 0x00010040); | |
742 | else if (dev_priv->chipset < 0xa0) | |
743 | gr_def(ctx, 0x407d08, 0x00390040); | |
744 | else | |
745 | gr_def(ctx, 0x407d08, 0x003d0040); | |
746 | gr_def(ctx, 0x407d0c, 0x00000022); | |
747 | } | |
748 | ||
749 | /* 8000+: per-TP state */ | |
750 | for (i = 0; i < 10; i++) { | |
751 | if (units & (1<<i)) { | |
752 | if (dev_priv->chipset < 0xa0) | |
753 | base = 0x408000 + (i<<12); | |
754 | else | |
755 | base = 0x408000 + (i<<11); | |
756 | if (dev_priv->chipset < 0xa0) | |
757 | offset = base + 0xc00; | |
758 | else | |
759 | offset = base + 0x80; | |
760 | cp_ctx(ctx, offset + 0x00, 1); | |
761 | gr_def(ctx, offset + 0x00, 0x0000ff0a); | |
762 | cp_ctx(ctx, offset + 0x08, 1); | |
763 | ||
764 | /* per-MP state */ | |
765 | for (j = 0; j < (dev_priv->chipset < 0xa0 ? 2 : 4); j++) { | |
766 | if (!(units & (1 << (j+24)))) continue; | |
767 | if (dev_priv->chipset < 0xa0) | |
768 | offset = base + 0x200 + (j<<7); | |
769 | else | |
770 | offset = base + 0x100 + (j<<7); | |
771 | cp_ctx(ctx, offset, 0x20); | |
772 | gr_def(ctx, offset + 0x00, 0x01800000); | |
773 | gr_def(ctx, offset + 0x04, 0x00160000); | |
774 | gr_def(ctx, offset + 0x08, 0x01800000); | |
775 | gr_def(ctx, offset + 0x18, 0x0003ffff); | |
776 | switch (dev_priv->chipset) { | |
777 | case 0x50: | |
778 | gr_def(ctx, offset + 0x1c, 0x00080000); | |
779 | break; | |
780 | case 0x84: | |
781 | gr_def(ctx, offset + 0x1c, 0x00880000); | |
782 | break; | |
783 | case 0x86: | |
784 | gr_def(ctx, offset + 0x1c, 0x008c0000); | |
785 | break; | |
786 | case 0x92: | |
787 | case 0x96: | |
788 | case 0x98: | |
789 | gr_def(ctx, offset + 0x1c, 0x118c0000); | |
790 | break; | |
791 | case 0x94: | |
792 | gr_def(ctx, offset + 0x1c, 0x10880000); | |
793 | break; | |
794 | case 0xa0: | |
795 | case 0xa5: | |
796 | gr_def(ctx, offset + 0x1c, 0x310c0000); | |
797 | break; | |
eaeefba1 | 798 | case 0xa3: |
d5f3c90d MK |
799 | case 0xa8: |
800 | case 0xaa: | |
801 | case 0xac: | |
802 | gr_def(ctx, offset + 0x1c, 0x300c0000); | |
803 | break; | |
804 | } | |
805 | gr_def(ctx, offset + 0x40, 0x00010401); | |
806 | if (dev_priv->chipset == 0x50) | |
807 | gr_def(ctx, offset + 0x48, 0x00000040); | |
808 | else | |
809 | gr_def(ctx, offset + 0x48, 0x00000078); | |
810 | gr_def(ctx, offset + 0x50, 0x000000bf); | |
811 | gr_def(ctx, offset + 0x58, 0x00001210); | |
812 | if (dev_priv->chipset == 0x50) | |
813 | gr_def(ctx, offset + 0x5c, 0x00000080); | |
814 | else | |
815 | gr_def(ctx, offset + 0x5c, 0x08000080); | |
816 | if (dev_priv->chipset >= 0xa0) | |
817 | gr_def(ctx, offset + 0x68, 0x0000003e); | |
818 | } | |
819 | ||
820 | if (dev_priv->chipset < 0xa0) | |
821 | cp_ctx(ctx, base + 0x300, 0x4); | |
822 | else | |
823 | cp_ctx(ctx, base + 0x300, 0x5); | |
824 | if (dev_priv->chipset == 0x50) | |
825 | gr_def(ctx, base + 0x304, 0x00007070); | |
826 | else if (dev_priv->chipset < 0xa0) | |
827 | gr_def(ctx, base + 0x304, 0x00027070); | |
828 | else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) | |
829 | gr_def(ctx, base + 0x304, 0x01127070); | |
830 | else | |
831 | gr_def(ctx, base + 0x304, 0x05127070); | |
832 | ||
833 | if (dev_priv->chipset < 0xa0) | |
834 | cp_ctx(ctx, base + 0x318, 1); | |
835 | else | |
836 | cp_ctx(ctx, base + 0x320, 1); | |
837 | if (dev_priv->chipset == 0x50) | |
838 | gr_def(ctx, base + 0x318, 0x0003ffff); | |
839 | else if (dev_priv->chipset < 0xa0) | |
840 | gr_def(ctx, base + 0x318, 0x03ffffff); | |
841 | else | |
842 | gr_def(ctx, base + 0x320, 0x07ffffff); | |
843 | ||
844 | if (dev_priv->chipset < 0xa0) | |
845 | cp_ctx(ctx, base + 0x324, 5); | |
846 | else | |
847 | cp_ctx(ctx, base + 0x328, 4); | |
848 | ||
849 | if (dev_priv->chipset < 0xa0) { | |
850 | cp_ctx(ctx, base + 0x340, 9); | |
851 | offset = base + 0x340; | |
852 | } else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) { | |
853 | cp_ctx(ctx, base + 0x33c, 0xb); | |
854 | offset = base + 0x344; | |
855 | } else { | |
856 | cp_ctx(ctx, base + 0x33c, 0xd); | |
857 | offset = base + 0x344; | |
858 | } | |
859 | gr_def(ctx, offset + 0x0, 0x00120407); | |
860 | gr_def(ctx, offset + 0x4, 0x05091507); | |
861 | if (dev_priv->chipset == 0x84) | |
862 | gr_def(ctx, offset + 0x8, 0x05100202); | |
863 | else | |
864 | gr_def(ctx, offset + 0x8, 0x05010202); | |
865 | gr_def(ctx, offset + 0xc, 0x00030201); | |
eaeefba1 MK |
866 | if (dev_priv->chipset == 0xa3) |
867 | cp_ctx(ctx, base + 0x36c, 1); | |
d5f3c90d MK |
868 | |
869 | cp_ctx(ctx, base + 0x400, 2); | |
870 | gr_def(ctx, base + 0x404, 0x00000040); | |
871 | cp_ctx(ctx, base + 0x40c, 2); | |
872 | gr_def(ctx, base + 0x40c, 0x0d0c0b0a); | |
873 | gr_def(ctx, base + 0x410, 0x00141210); | |
874 | ||
875 | if (dev_priv->chipset < 0xa0) | |
876 | offset = base + 0x800; | |
877 | else | |
878 | offset = base + 0x500; | |
879 | cp_ctx(ctx, offset, 6); | |
880 | gr_def(ctx, offset + 0x0, 0x000001f0); | |
881 | gr_def(ctx, offset + 0x4, 0x00000001); | |
882 | gr_def(ctx, offset + 0x8, 0x00000003); | |
883 | if (dev_priv->chipset == 0x50 || dev_priv->chipset >= 0xaa) | |
884 | gr_def(ctx, offset + 0xc, 0x00008000); | |
885 | gr_def(ctx, offset + 0x14, 0x00039e00); | |
886 | cp_ctx(ctx, offset + 0x1c, 2); | |
887 | if (dev_priv->chipset == 0x50) | |
888 | gr_def(ctx, offset + 0x1c, 0x00000040); | |
889 | else | |
890 | gr_def(ctx, offset + 0x1c, 0x00000100); | |
891 | gr_def(ctx, offset + 0x20, 0x00003800); | |
892 | ||
893 | if (dev_priv->chipset >= 0xa0) { | |
894 | cp_ctx(ctx, base + 0x54c, 2); | |
895 | if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) | |
896 | gr_def(ctx, base + 0x54c, 0x003fe006); | |
897 | else | |
898 | gr_def(ctx, base + 0x54c, 0x003fe007); | |
899 | gr_def(ctx, base + 0x550, 0x003fe000); | |
900 | } | |
901 | ||
902 | if (dev_priv->chipset < 0xa0) | |
903 | offset = base + 0xa00; | |
904 | else | |
905 | offset = base + 0x680; | |
906 | cp_ctx(ctx, offset, 1); | |
907 | gr_def(ctx, offset, 0x00404040); | |
908 | ||
909 | if (dev_priv->chipset < 0xa0) | |
910 | offset = base + 0xe00; | |
911 | else | |
912 | offset = base + 0x700; | |
913 | cp_ctx(ctx, offset, 2); | |
914 | if (dev_priv->chipset < 0xa0) | |
915 | gr_def(ctx, offset, 0x0077f005); | |
916 | else if (dev_priv->chipset == 0xa5) | |
917 | gr_def(ctx, offset, 0x6cf7f007); | |
918 | else if (dev_priv->chipset == 0xa8) | |
919 | gr_def(ctx, offset, 0x6cfff007); | |
920 | else if (dev_priv->chipset == 0xac) | |
921 | gr_def(ctx, offset, 0x0cfff007); | |
922 | else | |
923 | gr_def(ctx, offset, 0x0cf7f007); | |
924 | if (dev_priv->chipset == 0x50) | |
925 | gr_def(ctx, offset + 0x4, 0x00007fff); | |
926 | else if (dev_priv->chipset < 0xa0) | |
927 | gr_def(ctx, offset + 0x4, 0x003f7fff); | |
928 | else | |
929 | gr_def(ctx, offset + 0x4, 0x02bf7fff); | |
930 | cp_ctx(ctx, offset + 0x2c, 1); | |
931 | if (dev_priv->chipset == 0x50) { | |
932 | cp_ctx(ctx, offset + 0x50, 9); | |
933 | gr_def(ctx, offset + 0x54, 0x000003ff); | |
934 | gr_def(ctx, offset + 0x58, 0x00000003); | |
935 | gr_def(ctx, offset + 0x5c, 0x00000003); | |
936 | gr_def(ctx, offset + 0x60, 0x000001ff); | |
937 | gr_def(ctx, offset + 0x64, 0x0000001f); | |
938 | gr_def(ctx, offset + 0x68, 0x0000000f); | |
939 | gr_def(ctx, offset + 0x6c, 0x0000000f); | |
940 | } else if(dev_priv->chipset < 0xa0) { | |
941 | cp_ctx(ctx, offset + 0x50, 1); | |
942 | cp_ctx(ctx, offset + 0x70, 1); | |
943 | } else { | |
944 | cp_ctx(ctx, offset + 0x50, 1); | |
945 | cp_ctx(ctx, offset + 0x60, 5); | |
946 | } | |
947 | } | |
948 | } | |
949 | } | |
950 | ||
951 | /* | |
952 | * xfer areas. These are a pain. | |
953 | * | |
954 | * There are 2 xfer areas: the first one is big and contains all sorts of | |
955 | * stuff, the second is small and contains some per-TP context. | |
956 | * | |
957 | * Each area is split into 8 "strands". The areas, when saved to grctx, | |
958 | * are made of 8-word blocks. Each block contains a single word from | |
959 | * each strand. The strands are independent of each other, their | |
960 | * addresses are unrelated to each other, and data in them is closely | |
961 | * packed together. The strand layout varies a bit between cards: here | |
962 | * and there, a single word is thrown out in the middle and the whole | |
963 | * strand is offset by a bit from corresponding one on another chipset. | |
964 | * For this reason, addresses of stuff in strands are almost useless. | |
965 | * Knowing sequence of stuff and size of gaps between them is much more | |
966 | * useful, and that's how we build the strands in our generator. | |
967 | * | |
968 | * NVA0 takes this mess to a whole new level by cutting the old strands | |
969 | * into a few dozen pieces [known as genes], rearranging them randomly, | |
970 | * and putting them back together to make new strands. Hopefully these | |
971 | * genes correspond more or less directly to the same PGRAPH subunits | |
972 | * as in 400040 register. | |
973 | * | |
974 | * The most common value in default context is 0, and when the genes | |
975 | * are separated by 0's, gene bounduaries are quite speculative... | |
976 | * some of them can be clearly deduced, others can be guessed, and yet | |
977 | * others won't be resolved without figuring out the real meaning of | |
978 | * given ctxval. For the same reason, ending point of each strand | |
979 | * is unknown. Except for strand 0, which is the longest strand and | |
980 | * its end corresponds to end of the whole xfer. | |
981 | * | |
982 | * An unsolved mystery is the seek instruction: it takes an argument | |
983 | * in bits 8-18, and that argument is clearly the place in strands to | |
984 | * seek to... but the offsets don't seem to correspond to offsets as | |
985 | * seen in grctx. Perhaps there's another, real, not randomly-changing | |
986 | * addressing in strands, and the xfer insn just happens to skip over | |
987 | * the unused bits? NV10-NV30 PIPE comes to mind... | |
988 | * | |
989 | * As far as I know, there's no way to access the xfer areas directly | |
990 | * without the help of ctxprog. | |
991 | */ | |
992 | ||
993 | static inline void | |
994 | xf_emit(struct nouveau_grctx *ctx, int num, uint32_t val) { | |
995 | int i; | |
996 | if (val && ctx->mode == NOUVEAU_GRCTX_VALS) | |
997 | for (i = 0; i < num; i++) | |
998 | nv_wo32(ctx->dev, ctx->data, ctx->ctxvals_pos + (i << 3), val); | |
999 | ctx->ctxvals_pos += num << 3; | |
1000 | } | |
1001 | ||
1002 | /* Gene declarations... */ | |
1003 | ||
1004 | static void nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx); | |
1005 | static void nv50_graph_construct_gene_unk1(struct nouveau_grctx *ctx); | |
1006 | static void nv50_graph_construct_gene_unk2(struct nouveau_grctx *ctx); | |
1007 | static void nv50_graph_construct_gene_unk3(struct nouveau_grctx *ctx); | |
1008 | static void nv50_graph_construct_gene_unk4(struct nouveau_grctx *ctx); | |
1009 | static void nv50_graph_construct_gene_unk5(struct nouveau_grctx *ctx); | |
1010 | static void nv50_graph_construct_gene_unk6(struct nouveau_grctx *ctx); | |
1011 | static void nv50_graph_construct_gene_unk7(struct nouveau_grctx *ctx); | |
1012 | static void nv50_graph_construct_gene_unk8(struct nouveau_grctx *ctx); | |
1013 | static void nv50_graph_construct_gene_unk9(struct nouveau_grctx *ctx); | |
1014 | static void nv50_graph_construct_gene_unk10(struct nouveau_grctx *ctx); | |
1015 | static void nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx); | |
1016 | static void nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx); | |
1017 | ||
1018 | static void | |
1019 | nv50_graph_construct_xfer1(struct nouveau_grctx *ctx) | |
1020 | { | |
1021 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1022 | int i; | |
1023 | int offset; | |
1024 | int size = 0; | |
1025 | uint32_t units = nv_rd32 (ctx->dev, 0x1540); | |
1026 | ||
1027 | offset = (ctx->ctxvals_pos+0x3f)&~0x3f; | |
1028 | ctx->ctxvals_base = offset; | |
1029 | ||
1030 | if (dev_priv->chipset < 0xa0) { | |
1031 | /* Strand 0 */ | |
1032 | ctx->ctxvals_pos = offset; | |
1033 | switch (dev_priv->chipset) { | |
1034 | case 0x50: | |
1035 | xf_emit(ctx, 0x99, 0); | |
1036 | break; | |
1037 | case 0x84: | |
1038 | case 0x86: | |
1039 | xf_emit(ctx, 0x384, 0); | |
1040 | break; | |
1041 | case 0x92: | |
1042 | case 0x94: | |
1043 | case 0x96: | |
1044 | case 0x98: | |
1045 | xf_emit(ctx, 0x380, 0); | |
1046 | break; | |
1047 | } | |
1048 | nv50_graph_construct_gene_m2mf (ctx); | |
1049 | switch (dev_priv->chipset) { | |
1050 | case 0x50: | |
1051 | case 0x84: | |
1052 | case 0x86: | |
1053 | case 0x98: | |
1054 | xf_emit(ctx, 0x4c4, 0); | |
1055 | break; | |
1056 | case 0x92: | |
1057 | case 0x94: | |
1058 | case 0x96: | |
1059 | xf_emit(ctx, 0x984, 0); | |
1060 | break; | |
1061 | } | |
1062 | nv50_graph_construct_gene_unk5(ctx); | |
1063 | if (dev_priv->chipset == 0x50) | |
1064 | xf_emit(ctx, 0xa, 0); | |
1065 | else | |
1066 | xf_emit(ctx, 0xb, 0); | |
1067 | nv50_graph_construct_gene_unk4(ctx); | |
1068 | nv50_graph_construct_gene_unk3(ctx); | |
1069 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1070 | size = (ctx->ctxvals_pos-offset)/8; | |
1071 | ||
1072 | /* Strand 1 */ | |
1073 | ctx->ctxvals_pos = offset + 0x1; | |
1074 | nv50_graph_construct_gene_unk6(ctx); | |
1075 | nv50_graph_construct_gene_unk7(ctx); | |
1076 | nv50_graph_construct_gene_unk8(ctx); | |
1077 | switch (dev_priv->chipset) { | |
1078 | case 0x50: | |
1079 | case 0x92: | |
1080 | xf_emit(ctx, 0xfb, 0); | |
1081 | break; | |
1082 | case 0x84: | |
1083 | xf_emit(ctx, 0xd3, 0); | |
1084 | break; | |
1085 | case 0x94: | |
1086 | case 0x96: | |
1087 | xf_emit(ctx, 0xab, 0); | |
1088 | break; | |
1089 | case 0x86: | |
1090 | case 0x98: | |
1091 | xf_emit(ctx, 0x6b, 0); | |
1092 | break; | |
1093 | } | |
1094 | xf_emit(ctx, 2, 0x4e3bfdf); | |
1095 | xf_emit(ctx, 4, 0); | |
1096 | xf_emit(ctx, 1, 0x0fac6881); | |
1097 | xf_emit(ctx, 0xb, 0); | |
1098 | xf_emit(ctx, 2, 0x4e3bfdf); | |
1099 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1100 | size = (ctx->ctxvals_pos-offset)/8; | |
1101 | ||
1102 | /* Strand 2 */ | |
1103 | ctx->ctxvals_pos = offset + 0x2; | |
1104 | switch (dev_priv->chipset) { | |
1105 | case 0x50: | |
1106 | case 0x92: | |
1107 | xf_emit(ctx, 0xa80, 0); | |
1108 | break; | |
1109 | case 0x84: | |
1110 | xf_emit(ctx, 0xa7e, 0); | |
1111 | break; | |
1112 | case 0x94: | |
1113 | case 0x96: | |
1114 | xf_emit(ctx, 0xa7c, 0); | |
1115 | break; | |
1116 | case 0x86: | |
1117 | case 0x98: | |
1118 | xf_emit(ctx, 0xa7a, 0); | |
1119 | break; | |
1120 | } | |
1121 | xf_emit(ctx, 1, 0x3fffff); | |
1122 | xf_emit(ctx, 2, 0); | |
1123 | xf_emit(ctx, 1, 0x1fff); | |
1124 | xf_emit(ctx, 0xe, 0); | |
1125 | nv50_graph_construct_gene_unk9(ctx); | |
1126 | nv50_graph_construct_gene_unk2(ctx); | |
1127 | nv50_graph_construct_gene_unk1(ctx); | |
1128 | nv50_graph_construct_gene_unk10(ctx); | |
1129 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1130 | size = (ctx->ctxvals_pos-offset)/8; | |
1131 | ||
1132 | /* Strand 3: per-ROP group state */ | |
1133 | ctx->ctxvals_pos = offset + 3; | |
1134 | for (i = 0; i < 6; i++) | |
1135 | if (units & (1 << (i + 16))) | |
1136 | nv50_graph_construct_gene_ropc(ctx); | |
1137 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1138 | size = (ctx->ctxvals_pos-offset)/8; | |
1139 | ||
1140 | /* Strands 4-7: per-TP state */ | |
1141 | for (i = 0; i < 4; i++) { | |
1142 | ctx->ctxvals_pos = offset + 4 + i; | |
1143 | if (units & (1 << (2 * i))) | |
1144 | nv50_graph_construct_xfer_tp(ctx); | |
1145 | if (units & (1 << (2 * i + 1))) | |
1146 | nv50_graph_construct_xfer_tp(ctx); | |
1147 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1148 | size = (ctx->ctxvals_pos-offset)/8; | |
1149 | } | |
1150 | } else { | |
1151 | /* Strand 0 */ | |
1152 | ctx->ctxvals_pos = offset; | |
1153 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1154 | xf_emit(ctx, 0x385, 0); | |
1155 | else | |
1156 | xf_emit(ctx, 0x384, 0); | |
1157 | nv50_graph_construct_gene_m2mf(ctx); | |
1158 | xf_emit(ctx, 0x950, 0); | |
1159 | nv50_graph_construct_gene_unk10(ctx); | |
1160 | xf_emit(ctx, 1, 0x0fac6881); | |
1161 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
1162 | xf_emit(ctx, 1, 1); | |
1163 | xf_emit(ctx, 3, 0); | |
1164 | } | |
1165 | nv50_graph_construct_gene_unk8(ctx); | |
1166 | if (dev_priv->chipset == 0xa0) | |
1167 | xf_emit(ctx, 0x189, 0); | |
eaeefba1 MK |
1168 | else if (dev_priv->chipset == 0xa3) |
1169 | xf_emit(ctx, 0xd5, 0); | |
1170 | else if (dev_priv->chipset == 0xa5) | |
d5f3c90d MK |
1171 | xf_emit(ctx, 0x99, 0); |
1172 | else if (dev_priv->chipset == 0xaa) | |
1173 | xf_emit(ctx, 0x65, 0); | |
1174 | else | |
1175 | xf_emit(ctx, 0x6d, 0); | |
1176 | nv50_graph_construct_gene_unk9(ctx); | |
1177 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1178 | size = (ctx->ctxvals_pos-offset)/8; | |
1179 | ||
1180 | /* Strand 1 */ | |
1181 | ctx->ctxvals_pos = offset + 1; | |
1182 | nv50_graph_construct_gene_unk1(ctx); | |
1183 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1184 | size = (ctx->ctxvals_pos-offset)/8; | |
1185 | ||
1186 | /* Strand 2 */ | |
1187 | ctx->ctxvals_pos = offset + 2; | |
1188 | if (dev_priv->chipset == 0xa0) { | |
1189 | nv50_graph_construct_gene_unk2(ctx); | |
1190 | } | |
1191 | xf_emit(ctx, 0x36, 0); | |
1192 | nv50_graph_construct_gene_unk5(ctx); | |
1193 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1194 | size = (ctx->ctxvals_pos-offset)/8; | |
1195 | ||
1196 | /* Strand 3 */ | |
1197 | ctx->ctxvals_pos = offset + 3; | |
1198 | xf_emit(ctx, 1, 0); | |
1199 | xf_emit(ctx, 1, 1); | |
1200 | nv50_graph_construct_gene_unk6(ctx); | |
1201 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1202 | size = (ctx->ctxvals_pos-offset)/8; | |
1203 | ||
1204 | /* Strand 4 */ | |
1205 | ctx->ctxvals_pos = offset + 4; | |
1206 | if (dev_priv->chipset == 0xa0) | |
1207 | xf_emit(ctx, 0xa80, 0); | |
eaeefba1 MK |
1208 | else if (dev_priv->chipset == 0xa3) |
1209 | xf_emit(ctx, 0xa7c, 0); | |
d5f3c90d MK |
1210 | else |
1211 | xf_emit(ctx, 0xa7a, 0); | |
1212 | xf_emit(ctx, 1, 0x3fffff); | |
1213 | xf_emit(ctx, 2, 0); | |
1214 | xf_emit(ctx, 1, 0x1fff); | |
1215 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1216 | size = (ctx->ctxvals_pos-offset)/8; | |
1217 | ||
1218 | /* Strand 5 */ | |
1219 | ctx->ctxvals_pos = offset + 5; | |
1220 | xf_emit(ctx, 1, 0); | |
1221 | xf_emit(ctx, 1, 0x0fac6881); | |
1222 | xf_emit(ctx, 0xb, 0); | |
1223 | xf_emit(ctx, 2, 0x4e3bfdf); | |
1224 | xf_emit(ctx, 3, 0); | |
1225 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1226 | xf_emit(ctx, 1, 0x11); | |
1227 | xf_emit(ctx, 1, 0); | |
1228 | xf_emit(ctx, 2, 0x4e3bfdf); | |
1229 | xf_emit(ctx, 2, 0); | |
1230 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1231 | xf_emit(ctx, 1, 0x11); | |
1232 | xf_emit(ctx, 1, 0); | |
1233 | for (i = 0; i < 8; i++) | |
1234 | if (units & (1<<(i+16))) | |
1235 | nv50_graph_construct_gene_ropc(ctx); | |
1236 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1237 | size = (ctx->ctxvals_pos-offset)/8; | |
1238 | ||
1239 | /* Strand 6 */ | |
1240 | ctx->ctxvals_pos = offset + 6; | |
1241 | nv50_graph_construct_gene_unk3(ctx); | |
1242 | xf_emit(ctx, 0xb, 0); | |
1243 | nv50_graph_construct_gene_unk4(ctx); | |
1244 | nv50_graph_construct_gene_unk7(ctx); | |
1245 | if (units & (1 << 0)) | |
1246 | nv50_graph_construct_xfer_tp(ctx); | |
1247 | if (units & (1 << 1)) | |
1248 | nv50_graph_construct_xfer_tp(ctx); | |
1249 | if (units & (1 << 2)) | |
1250 | nv50_graph_construct_xfer_tp(ctx); | |
1251 | if (units & (1 << 3)) | |
1252 | nv50_graph_construct_xfer_tp(ctx); | |
1253 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1254 | size = (ctx->ctxvals_pos-offset)/8; | |
1255 | ||
1256 | /* Strand 7 */ | |
1257 | ctx->ctxvals_pos = offset + 7; | |
1258 | if (dev_priv->chipset == 0xa0) { | |
1259 | if (units & (1 << 4)) | |
1260 | nv50_graph_construct_xfer_tp(ctx); | |
1261 | if (units & (1 << 5)) | |
1262 | nv50_graph_construct_xfer_tp(ctx); | |
1263 | if (units & (1 << 6)) | |
1264 | nv50_graph_construct_xfer_tp(ctx); | |
1265 | if (units & (1 << 7)) | |
1266 | nv50_graph_construct_xfer_tp(ctx); | |
1267 | if (units & (1 << 8)) | |
1268 | nv50_graph_construct_xfer_tp(ctx); | |
1269 | if (units & (1 << 9)) | |
1270 | nv50_graph_construct_xfer_tp(ctx); | |
1271 | } else { | |
1272 | nv50_graph_construct_gene_unk2(ctx); | |
1273 | } | |
1274 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
1275 | size = (ctx->ctxvals_pos-offset)/8; | |
1276 | } | |
1277 | ||
1278 | ctx->ctxvals_pos = offset + size * 8; | |
1279 | ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; | |
1280 | cp_lsr (ctx, offset); | |
1281 | cp_out (ctx, CP_SET_XFER_POINTER); | |
1282 | cp_lsr (ctx, size); | |
1283 | cp_out (ctx, CP_SEEK_1); | |
1284 | cp_out (ctx, CP_XFER_1); | |
1285 | cp_wait(ctx, XFER, BUSY); | |
1286 | } | |
1287 | ||
1288 | /* | |
1289 | * non-trivial demagiced parts of ctx init go here | |
1290 | */ | |
1291 | ||
1292 | static void | |
1293 | nv50_graph_construct_gene_m2mf(struct nouveau_grctx *ctx) | |
1294 | { | |
1295 | /* m2mf state */ | |
1296 | xf_emit (ctx, 1, 0); /* DMA_NOTIFY instance >> 4 */ | |
1297 | xf_emit (ctx, 1, 0); /* DMA_BUFFER_IN instance >> 4 */ | |
1298 | xf_emit (ctx, 1, 0); /* DMA_BUFFER_OUT instance >> 4 */ | |
1299 | xf_emit (ctx, 1, 0); /* OFFSET_IN */ | |
1300 | xf_emit (ctx, 1, 0); /* OFFSET_OUT */ | |
1301 | xf_emit (ctx, 1, 0); /* PITCH_IN */ | |
1302 | xf_emit (ctx, 1, 0); /* PITCH_OUT */ | |
1303 | xf_emit (ctx, 1, 0); /* LINE_LENGTH */ | |
1304 | xf_emit (ctx, 1, 0); /* LINE_COUNT */ | |
1305 | xf_emit (ctx, 1, 0x21); /* FORMAT: bits 0-4 INPUT_INC, bits 5-9 OUTPUT_INC */ | |
1306 | xf_emit (ctx, 1, 1); /* LINEAR_IN */ | |
1307 | xf_emit (ctx, 1, 0x2); /* TILING_MODE_IN: bits 0-2 y tiling, bits 3-5 z tiling */ | |
1308 | xf_emit (ctx, 1, 0x100); /* TILING_PITCH_IN */ | |
1309 | xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_IN */ | |
1310 | xf_emit (ctx, 1, 1); /* TILING_DEPTH_IN */ | |
1311 | xf_emit (ctx, 1, 0); /* TILING_POSITION_IN_Z */ | |
1312 | xf_emit (ctx, 1, 0); /* TILING_POSITION_IN */ | |
1313 | xf_emit (ctx, 1, 1); /* LINEAR_OUT */ | |
1314 | xf_emit (ctx, 1, 0x2); /* TILING_MODE_OUT: bits 0-2 y tiling, bits 3-5 z tiling */ | |
1315 | xf_emit (ctx, 1, 0x100); /* TILING_PITCH_OUT */ | |
1316 | xf_emit (ctx, 1, 0x100); /* TILING_HEIGHT_OUT */ | |
1317 | xf_emit (ctx, 1, 1); /* TILING_DEPTH_OUT */ | |
1318 | xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT_Z */ | |
1319 | xf_emit (ctx, 1, 0); /* TILING_POSITION_OUT */ | |
1320 | xf_emit (ctx, 1, 0); /* OFFSET_IN_HIGH */ | |
1321 | xf_emit (ctx, 1, 0); /* OFFSET_OUT_HIGH */ | |
1322 | } | |
1323 | ||
1324 | static void | |
1325 | nv50_graph_construct_gene_unk1(struct nouveau_grctx *ctx) | |
1326 | { | |
1327 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1328 | /* end of area 2 on pre-NVA0, area 1 on NVAx */ | |
1329 | xf_emit(ctx, 2, 4); | |
1330 | xf_emit(ctx, 1, 0); | |
1331 | xf_emit(ctx, 1, 0x80); | |
1332 | xf_emit(ctx, 1, 4); | |
1333 | xf_emit(ctx, 1, 0x80c14); | |
1334 | xf_emit(ctx, 1, 0); | |
1335 | if (dev_priv->chipset == 0x50) | |
1336 | xf_emit(ctx, 1, 0x3ff); | |
1337 | else | |
1338 | xf_emit(ctx, 1, 0x7ff); | |
1339 | switch (dev_priv->chipset) { | |
1340 | case 0x50: | |
1341 | case 0x86: | |
1342 | case 0x98: | |
1343 | case 0xaa: | |
1344 | case 0xac: | |
1345 | xf_emit(ctx, 0x542, 0); | |
1346 | break; | |
1347 | case 0x84: | |
1348 | case 0x92: | |
1349 | case 0x94: | |
1350 | case 0x96: | |
1351 | xf_emit(ctx, 0x942, 0); | |
1352 | break; | |
1353 | case 0xa0: | |
eaeefba1 | 1354 | case 0xa3: |
d5f3c90d MK |
1355 | xf_emit(ctx, 0x2042, 0); |
1356 | break; | |
1357 | case 0xa5: | |
1358 | case 0xa8: | |
1359 | xf_emit(ctx, 0x842, 0); | |
1360 | break; | |
1361 | } | |
1362 | xf_emit(ctx, 2, 4); | |
1363 | xf_emit(ctx, 1, 0); | |
1364 | xf_emit(ctx, 1, 0x80); | |
1365 | xf_emit(ctx, 1, 4); | |
1366 | xf_emit(ctx, 1, 1); | |
1367 | xf_emit(ctx, 1, 0); | |
1368 | xf_emit(ctx, 1, 0x27); | |
1369 | xf_emit(ctx, 1, 0); | |
1370 | xf_emit(ctx, 1, 0x26); | |
1371 | xf_emit(ctx, 3, 0); | |
1372 | } | |
1373 | ||
1374 | static void | |
1375 | nv50_graph_construct_gene_unk10(struct nouveau_grctx *ctx) | |
1376 | { | |
1377 | /* end of area 2 on pre-NVA0, area 1 on NVAx */ | |
1378 | xf_emit(ctx, 0x10, 0x04000000); | |
1379 | xf_emit(ctx, 0x24, 0); | |
1380 | xf_emit(ctx, 2, 0x04e3bfdf); | |
1381 | xf_emit(ctx, 2, 0); | |
1382 | xf_emit(ctx, 1, 0x1fe21); | |
1383 | } | |
1384 | ||
1385 | static void | |
1386 | nv50_graph_construct_gene_unk2(struct nouveau_grctx *ctx) | |
1387 | { | |
1388 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1389 | /* middle of area 2 on pre-NVA0, beginning of area 2 on NVA0, area 7 on >NVA0 */ | |
1390 | if (dev_priv->chipset != 0x50) { | |
1391 | xf_emit(ctx, 5, 0); | |
1392 | xf_emit(ctx, 1, 0x80c14); | |
1393 | xf_emit(ctx, 2, 0); | |
1394 | xf_emit(ctx, 1, 0x804); | |
1395 | xf_emit(ctx, 1, 0); | |
1396 | xf_emit(ctx, 2, 4); | |
1397 | xf_emit(ctx, 1, 0x8100c12); | |
1398 | } | |
1399 | xf_emit(ctx, 1, 0); | |
1400 | xf_emit(ctx, 2, 4); | |
1401 | xf_emit(ctx, 1, 0); | |
1402 | xf_emit(ctx, 1, 0x10); | |
1403 | if (dev_priv->chipset == 0x50) | |
1404 | xf_emit(ctx, 3, 0); | |
1405 | else | |
1406 | xf_emit(ctx, 4, 0); | |
1407 | xf_emit(ctx, 1, 0x804); | |
1408 | xf_emit(ctx, 1, 1); | |
1409 | xf_emit(ctx, 1, 0x1a); | |
1410 | if (dev_priv->chipset != 0x50) | |
1411 | xf_emit(ctx, 1, 0x7f); | |
1412 | xf_emit(ctx, 1, 0); | |
1413 | xf_emit(ctx, 1, 1); | |
1414 | xf_emit(ctx, 1, 0x80c14); | |
1415 | xf_emit(ctx, 1, 0); | |
1416 | xf_emit(ctx, 1, 0x8100c12); | |
1417 | xf_emit(ctx, 2, 4); | |
1418 | xf_emit(ctx, 1, 0); | |
1419 | xf_emit(ctx, 1, 0x10); | |
1420 | xf_emit(ctx, 3, 0); | |
1421 | xf_emit(ctx, 1, 1); | |
1422 | xf_emit(ctx, 1, 0x8100c12); | |
1423 | xf_emit(ctx, 6, 0); | |
1424 | if (dev_priv->chipset == 0x50) | |
1425 | xf_emit(ctx, 1, 0x3ff); | |
1426 | else | |
1427 | xf_emit(ctx, 1, 0x7ff); | |
1428 | xf_emit(ctx, 1, 0x80c14); | |
1429 | xf_emit(ctx, 0x38, 0); | |
1430 | xf_emit(ctx, 1, 1); | |
1431 | xf_emit(ctx, 2, 0); | |
1432 | xf_emit(ctx, 1, 0x10); | |
1433 | xf_emit(ctx, 0x38, 0); | |
1434 | xf_emit(ctx, 2, 0x88); | |
1435 | xf_emit(ctx, 2, 0); | |
1436 | xf_emit(ctx, 1, 4); | |
1437 | xf_emit(ctx, 0x16, 0); | |
1438 | xf_emit(ctx, 1, 0x26); | |
1439 | xf_emit(ctx, 2, 0); | |
1440 | xf_emit(ctx, 1, 0x3f800000); | |
1441 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1442 | xf_emit(ctx, 4, 0); | |
1443 | else | |
1444 | xf_emit(ctx, 3, 0); | |
1445 | xf_emit(ctx, 1, 0x1a); | |
1446 | xf_emit(ctx, 1, 0x10); | |
1447 | if (dev_priv->chipset != 0x50) | |
1448 | xf_emit(ctx, 0x28, 0); | |
1449 | else | |
1450 | xf_emit(ctx, 0x25, 0); | |
1451 | xf_emit(ctx, 1, 0x52); | |
1452 | xf_emit(ctx, 1, 0); | |
1453 | xf_emit(ctx, 1, 0x26); | |
1454 | xf_emit(ctx, 1, 0); | |
1455 | xf_emit(ctx, 2, 4); | |
1456 | xf_emit(ctx, 1, 0); | |
1457 | xf_emit(ctx, 1, 0x1a); | |
1458 | xf_emit(ctx, 2, 0); | |
1459 | xf_emit(ctx, 1, 0x00ffff00); | |
1460 | xf_emit(ctx, 1, 0); | |
1461 | } | |
1462 | ||
1463 | static void | |
1464 | nv50_graph_construct_gene_unk3(struct nouveau_grctx *ctx) | |
1465 | { | |
1466 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1467 | /* end of area 0 on pre-NVA0, beginning of area 6 on NVAx */ | |
1468 | xf_emit(ctx, 1, 0x3f); | |
1469 | xf_emit(ctx, 0xa, 0); | |
1470 | xf_emit(ctx, 1, 2); | |
1471 | xf_emit(ctx, 2, 0x04000000); | |
1472 | xf_emit(ctx, 8, 0); | |
1473 | xf_emit(ctx, 1, 4); | |
1474 | xf_emit(ctx, 3, 0); | |
1475 | xf_emit(ctx, 1, 4); | |
1476 | if (dev_priv->chipset == 0x50) | |
1477 | xf_emit(ctx, 0x10, 0); | |
1478 | else | |
1479 | xf_emit(ctx, 0x11, 0); | |
1480 | xf_emit(ctx, 1, 1); | |
1481 | xf_emit(ctx, 1, 0x1001); | |
1482 | xf_emit(ctx, 4, 0xffff); | |
1483 | xf_emit(ctx, 0x20, 0); | |
1484 | xf_emit(ctx, 0x10, 0x3f800000); | |
1485 | xf_emit(ctx, 1, 0x10); | |
1486 | if (dev_priv->chipset == 0x50) | |
1487 | xf_emit(ctx, 1, 0); | |
1488 | else | |
1489 | xf_emit(ctx, 2, 0); | |
1490 | xf_emit(ctx, 1, 3); | |
1491 | xf_emit(ctx, 2, 0); | |
1492 | } | |
1493 | ||
1494 | static void | |
1495 | nv50_graph_construct_gene_unk4(struct nouveau_grctx *ctx) | |
1496 | { | |
1497 | /* middle of area 0 on pre-NVA0, middle of area 6 on NVAx */ | |
1498 | xf_emit(ctx, 2, 0x04000000); | |
1499 | xf_emit(ctx, 1, 0); | |
1500 | xf_emit(ctx, 1, 0x80); | |
1501 | xf_emit(ctx, 3, 0); | |
1502 | xf_emit(ctx, 1, 0x80); | |
1503 | xf_emit(ctx, 1, 0); | |
1504 | } | |
1505 | ||
1506 | static void | |
1507 | nv50_graph_construct_gene_unk5(struct nouveau_grctx *ctx) | |
1508 | { | |
1509 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1510 | /* middle of area 0 on pre-NVA0 [after m2mf], end of area 2 on NVAx */ | |
1511 | xf_emit(ctx, 2, 4); | |
1512 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1513 | xf_emit(ctx, 0x1c4d, 0); | |
1514 | else | |
1515 | xf_emit(ctx, 0x1c4b, 0); | |
1516 | xf_emit(ctx, 2, 4); | |
1517 | xf_emit(ctx, 1, 0x8100c12); | |
1518 | if (dev_priv->chipset != 0x50) | |
1519 | xf_emit(ctx, 1, 3); | |
1520 | xf_emit(ctx, 1, 0); | |
1521 | xf_emit(ctx, 1, 0x8100c12); | |
1522 | xf_emit(ctx, 1, 0); | |
1523 | xf_emit(ctx, 1, 0x80c14); | |
1524 | xf_emit(ctx, 1, 1); | |
1525 | if (dev_priv->chipset >= 0xa0) | |
1526 | xf_emit(ctx, 2, 4); | |
1527 | xf_emit(ctx, 1, 0x80c14); | |
1528 | xf_emit(ctx, 2, 0); | |
1529 | xf_emit(ctx, 1, 0x8100c12); | |
1530 | xf_emit(ctx, 1, 0x27); | |
1531 | xf_emit(ctx, 2, 0); | |
1532 | xf_emit(ctx, 1, 1); | |
1533 | xf_emit(ctx, 0x3c1, 0); | |
1534 | xf_emit(ctx, 1, 1); | |
1535 | xf_emit(ctx, 0x16, 0); | |
1536 | xf_emit(ctx, 1, 0x8100c12); | |
1537 | xf_emit(ctx, 1, 0); | |
1538 | } | |
1539 | ||
1540 | static void | |
1541 | nv50_graph_construct_gene_unk6(struct nouveau_grctx *ctx) | |
1542 | { | |
1543 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1544 | /* beginning of area 1 on pre-NVA0 [after m2mf], area 3 on NVAx */ | |
1545 | xf_emit(ctx, 4, 0); | |
1546 | xf_emit(ctx, 1, 0xf); | |
1547 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1548 | xf_emit(ctx, 8, 0); | |
1549 | else | |
1550 | xf_emit(ctx, 4, 0); | |
1551 | xf_emit(ctx, 1, 0x20); | |
1552 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1553 | xf_emit(ctx, 0x11, 0); | |
1554 | else if (dev_priv->chipset >= 0xa0) | |
1555 | xf_emit(ctx, 0xf, 0); | |
1556 | else | |
1557 | xf_emit(ctx, 0xe, 0); | |
1558 | xf_emit(ctx, 1, 0x1a); | |
1559 | xf_emit(ctx, 0xd, 0); | |
1560 | xf_emit(ctx, 2, 4); | |
1561 | xf_emit(ctx, 1, 0); | |
1562 | xf_emit(ctx, 1, 4); | |
1563 | xf_emit(ctx, 1, 8); | |
1564 | xf_emit(ctx, 1, 0); | |
1565 | if (dev_priv->chipset == 0x50) | |
1566 | xf_emit(ctx, 1, 0x3ff); | |
1567 | else | |
1568 | xf_emit(ctx, 1, 0x7ff); | |
1569 | if (dev_priv->chipset == 0xa8) | |
1570 | xf_emit(ctx, 1, 0x1e00); | |
1571 | xf_emit(ctx, 0xc, 0); | |
1572 | xf_emit(ctx, 1, 0xf); | |
1573 | if (dev_priv->chipset == 0x50) | |
1574 | xf_emit(ctx, 0x125, 0); | |
1575 | else if (dev_priv->chipset < 0xa0) | |
1576 | xf_emit(ctx, 0x126, 0); | |
1577 | else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa) | |
1578 | xf_emit(ctx, 0x124, 0); | |
1579 | else | |
1580 | xf_emit(ctx, 0x1f7, 0); | |
1581 | xf_emit(ctx, 1, 0xf); | |
1582 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1583 | xf_emit(ctx, 3, 0); | |
1584 | else | |
1585 | xf_emit(ctx, 1, 0); | |
1586 | xf_emit(ctx, 1, 1); | |
1587 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1588 | xf_emit(ctx, 0xa1, 0); | |
1589 | else | |
1590 | xf_emit(ctx, 0x5a, 0); | |
1591 | xf_emit(ctx, 1, 0xf); | |
1592 | if (dev_priv->chipset < 0xa0) | |
1593 | xf_emit(ctx, 0x834, 0); | |
1594 | else if (dev_priv->chipset == 0xa0) | |
1595 | xf_emit(ctx, 0x1873, 0); | |
1596 | else if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1597 | xf_emit(ctx, 0x8ba, 0); | |
1598 | else | |
1599 | xf_emit(ctx, 0x833, 0); | |
1600 | xf_emit(ctx, 1, 0xf); | |
1601 | xf_emit(ctx, 0xf, 0); | |
1602 | } | |
1603 | ||
1604 | static void | |
1605 | nv50_graph_construct_gene_unk7(struct nouveau_grctx *ctx) | |
1606 | { | |
1607 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1608 | /* middle of area 1 on pre-NVA0 [after m2mf], middle of area 6 on NVAx */ | |
1609 | xf_emit(ctx, 2, 0); | |
1610 | if (dev_priv->chipset == 0x50) | |
1611 | xf_emit(ctx, 2, 1); | |
1612 | else | |
1613 | xf_emit(ctx, 2, 0); | |
1614 | xf_emit(ctx, 1, 0); | |
1615 | xf_emit(ctx, 1, 1); | |
1616 | xf_emit(ctx, 2, 0x100); | |
1617 | xf_emit(ctx, 1, 0x11); | |
1618 | xf_emit(ctx, 1, 0); | |
1619 | xf_emit(ctx, 1, 8); | |
1620 | xf_emit(ctx, 5, 0); | |
1621 | xf_emit(ctx, 1, 1); | |
1622 | xf_emit(ctx, 1, 0); | |
1623 | xf_emit(ctx, 3, 1); | |
1624 | xf_emit(ctx, 1, 0xcf); | |
1625 | xf_emit(ctx, 1, 2); | |
1626 | xf_emit(ctx, 6, 0); | |
1627 | xf_emit(ctx, 1, 1); | |
1628 | xf_emit(ctx, 1, 0); | |
1629 | xf_emit(ctx, 3, 1); | |
1630 | xf_emit(ctx, 4, 0); | |
1631 | xf_emit(ctx, 1, 4); | |
1632 | xf_emit(ctx, 1, 0); | |
1633 | xf_emit(ctx, 1, 1); | |
1634 | xf_emit(ctx, 1, 0x15); | |
1635 | xf_emit(ctx, 3, 0); | |
1636 | xf_emit(ctx, 1, 0x4444480); | |
1637 | xf_emit(ctx, 0x37, 0); | |
1638 | } | |
1639 | ||
1640 | static void | |
1641 | nv50_graph_construct_gene_unk8(struct nouveau_grctx *ctx) | |
1642 | { | |
1643 | /* middle of area 1 on pre-NVA0 [after m2mf], middle of area 0 on NVAx */ | |
1644 | xf_emit(ctx, 4, 0); | |
1645 | xf_emit(ctx, 1, 0x8100c12); | |
1646 | xf_emit(ctx, 4, 0); | |
1647 | xf_emit(ctx, 1, 0x100); | |
1648 | xf_emit(ctx, 2, 0); | |
1649 | xf_emit(ctx, 1, 0x10001); | |
1650 | xf_emit(ctx, 1, 0); | |
1651 | xf_emit(ctx, 1, 0x10001); | |
1652 | xf_emit(ctx, 1, 1); | |
1653 | xf_emit(ctx, 1, 0x10001); | |
1654 | xf_emit(ctx, 1, 1); | |
1655 | xf_emit(ctx, 1, 4); | |
1656 | xf_emit(ctx, 1, 2); | |
1657 | } | |
1658 | ||
1659 | static void | |
1660 | nv50_graph_construct_gene_unk9(struct nouveau_grctx *ctx) | |
1661 | { | |
1662 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1663 | /* middle of area 2 on pre-NVA0 [after m2mf], end of area 0 on NVAx */ | |
1664 | xf_emit(ctx, 1, 0x3f800000); | |
1665 | xf_emit(ctx, 6, 0); | |
1666 | xf_emit(ctx, 1, 4); | |
1667 | xf_emit(ctx, 1, 0x1a); | |
1668 | xf_emit(ctx, 2, 0); | |
1669 | xf_emit(ctx, 1, 1); | |
1670 | xf_emit(ctx, 0x12, 0); | |
1671 | xf_emit(ctx, 1, 0x00ffff00); | |
1672 | xf_emit(ctx, 6, 0); | |
1673 | xf_emit(ctx, 1, 0xf); | |
1674 | xf_emit(ctx, 7, 0); | |
1675 | xf_emit(ctx, 1, 0x0fac6881); | |
1676 | xf_emit(ctx, 1, 0x11); | |
1677 | xf_emit(ctx, 0xf, 0); | |
1678 | xf_emit(ctx, 1, 4); | |
1679 | xf_emit(ctx, 2, 0); | |
1680 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1681 | xf_emit(ctx, 1, 3); | |
1682 | else if (dev_priv->chipset >= 0xa0) | |
1683 | xf_emit(ctx, 1, 1); | |
1684 | xf_emit(ctx, 2, 0); | |
1685 | xf_emit(ctx, 1, 2); | |
1686 | xf_emit(ctx, 2, 0x04000000); | |
1687 | xf_emit(ctx, 3, 0); | |
1688 | xf_emit(ctx, 1, 5); | |
1689 | xf_emit(ctx, 1, 0x52); | |
1690 | if (dev_priv->chipset == 0x50) { | |
1691 | xf_emit(ctx, 0x13, 0); | |
1692 | } else { | |
1693 | xf_emit(ctx, 4, 0); | |
1694 | xf_emit(ctx, 1, 1); | |
1695 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1696 | xf_emit(ctx, 0x11, 0); | |
1697 | else | |
1698 | xf_emit(ctx, 0x10, 0); | |
1699 | } | |
1700 | xf_emit(ctx, 0x10, 0x3f800000); | |
1701 | xf_emit(ctx, 1, 0x10); | |
1702 | xf_emit(ctx, 0x26, 0); | |
1703 | xf_emit(ctx, 1, 0x8100c12); | |
1704 | xf_emit(ctx, 1, 5); | |
1705 | xf_emit(ctx, 2, 0); | |
1706 | xf_emit(ctx, 1, 1); | |
1707 | xf_emit(ctx, 1, 0); | |
1708 | xf_emit(ctx, 4, 0xffff); | |
1709 | if (dev_priv->chipset != 0x50) | |
1710 | xf_emit(ctx, 1, 3); | |
1711 | if (dev_priv->chipset < 0xa0) | |
1712 | xf_emit(ctx, 0x1f, 0); | |
1713 | else if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1714 | xf_emit(ctx, 0xc, 0); | |
1715 | else | |
1716 | xf_emit(ctx, 3, 0); | |
1717 | xf_emit(ctx, 1, 0x00ffff00); | |
1718 | xf_emit(ctx, 1, 0x1a); | |
1719 | if (dev_priv->chipset != 0x50) { | |
1720 | xf_emit(ctx, 1, 0); | |
1721 | xf_emit(ctx, 1, 3); | |
1722 | } | |
1723 | if (dev_priv->chipset < 0xa0) | |
1724 | xf_emit(ctx, 0x26, 0); | |
1725 | else | |
1726 | xf_emit(ctx, 0x3c, 0); | |
1727 | xf_emit(ctx, 1, 0x102); | |
1728 | xf_emit(ctx, 1, 0); | |
1729 | xf_emit(ctx, 4, 4); | |
1730 | if (dev_priv->chipset >= 0xa0) | |
1731 | xf_emit(ctx, 8, 0); | |
1732 | xf_emit(ctx, 2, 4); | |
1733 | xf_emit(ctx, 1, 0); | |
1734 | if (dev_priv->chipset == 0x50) | |
1735 | xf_emit(ctx, 1, 0x3ff); | |
1736 | else | |
1737 | xf_emit(ctx, 1, 0x7ff); | |
1738 | xf_emit(ctx, 1, 0); | |
1739 | xf_emit(ctx, 1, 0x102); | |
1740 | xf_emit(ctx, 9, 0); | |
1741 | xf_emit(ctx, 4, 4); | |
1742 | xf_emit(ctx, 0x2c, 0); | |
1743 | } | |
1744 | ||
1745 | static void | |
1746 | nv50_graph_construct_gene_ropc(struct nouveau_grctx *ctx) | |
1747 | { | |
1748 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1749 | int magic2; | |
1750 | if (dev_priv->chipset == 0x50) { | |
1751 | magic2 = 0x00003e60; | |
1752 | } else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) { | |
1753 | magic2 = 0x001ffe67; | |
1754 | } else { | |
1755 | magic2 = 0x00087e67; | |
1756 | } | |
1757 | xf_emit(ctx, 8, 0); | |
1758 | xf_emit(ctx, 1, 2); | |
1759 | xf_emit(ctx, 1, 0); | |
1760 | xf_emit(ctx, 1, magic2); | |
1761 | xf_emit(ctx, 4, 0); | |
1762 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1763 | xf_emit(ctx, 1, 1); | |
1764 | xf_emit(ctx, 7, 0); | |
1765 | if (dev_priv->chipset >= 0xa0 && dev_priv->chipset < 0xaa) | |
1766 | xf_emit(ctx, 1, 0x15); | |
1767 | xf_emit(ctx, 1, 0); | |
1768 | xf_emit(ctx, 1, 1); | |
1769 | xf_emit(ctx, 1, 0x10); | |
1770 | xf_emit(ctx, 2, 0); | |
1771 | xf_emit(ctx, 1, 1); | |
1772 | xf_emit(ctx, 4, 0); | |
1773 | if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x92 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa0) { | |
1774 | xf_emit(ctx, 1, 4); | |
1775 | xf_emit(ctx, 1, 0x400); | |
1776 | xf_emit(ctx, 1, 0x300); | |
1777 | xf_emit(ctx, 1, 0x1001); | |
1778 | if (dev_priv->chipset != 0xa0) { | |
1779 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1780 | xf_emit(ctx, 1, 0); | |
1781 | else | |
1782 | xf_emit(ctx, 1, 0x15); | |
1783 | } | |
1784 | xf_emit(ctx, 3, 0); | |
1785 | } | |
1786 | xf_emit(ctx, 2, 0); | |
1787 | xf_emit(ctx, 1, 2); | |
1788 | xf_emit(ctx, 8, 0); | |
1789 | xf_emit(ctx, 1, 1); | |
1790 | xf_emit(ctx, 1, 0x10); | |
1791 | xf_emit(ctx, 1, 0); | |
1792 | xf_emit(ctx, 1, 1); | |
1793 | xf_emit(ctx, 0x13, 0); | |
1794 | xf_emit(ctx, 1, 0x10); | |
1795 | xf_emit(ctx, 0x10, 0); | |
1796 | xf_emit(ctx, 0x10, 0x3f800000); | |
1797 | xf_emit(ctx, 0x19, 0); | |
1798 | xf_emit(ctx, 1, 0x10); | |
1799 | xf_emit(ctx, 1, 0); | |
1800 | xf_emit(ctx, 1, 0x3f); | |
1801 | xf_emit(ctx, 6, 0); | |
1802 | xf_emit(ctx, 1, 1); | |
1803 | xf_emit(ctx, 1, 0); | |
1804 | xf_emit(ctx, 1, 1); | |
1805 | xf_emit(ctx, 1, 0); | |
1806 | xf_emit(ctx, 1, 1); | |
1807 | if (dev_priv->chipset >= 0xa0) { | |
1808 | xf_emit(ctx, 2, 0); | |
1809 | xf_emit(ctx, 1, 0x1001); | |
1810 | xf_emit(ctx, 0xb, 0); | |
1811 | } else { | |
1812 | xf_emit(ctx, 0xc, 0); | |
1813 | } | |
1814 | xf_emit(ctx, 1, 0x11); | |
1815 | xf_emit(ctx, 7, 0); | |
1816 | xf_emit(ctx, 1, 0xf); | |
1817 | xf_emit(ctx, 7, 0); | |
1818 | xf_emit(ctx, 1, 0x11); | |
1819 | if (dev_priv->chipset == 0x50) | |
1820 | xf_emit(ctx, 4, 0); | |
1821 | else | |
1822 | xf_emit(ctx, 6, 0); | |
1823 | xf_emit(ctx, 3, 1); | |
1824 | xf_emit(ctx, 1, 2); | |
1825 | xf_emit(ctx, 1, 1); | |
1826 | xf_emit(ctx, 1, 2); | |
1827 | xf_emit(ctx, 1, 1); | |
1828 | xf_emit(ctx, 1, 0); | |
1829 | xf_emit(ctx, 1, magic2); | |
1830 | xf_emit(ctx, 1, 0); | |
1831 | xf_emit(ctx, 1, 0x0fac6881); | |
1832 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
1833 | xf_emit(ctx, 1, 0); | |
1834 | xf_emit(ctx, 0x18, 1); | |
1835 | xf_emit(ctx, 8, 2); | |
1836 | xf_emit(ctx, 8, 1); | |
1837 | xf_emit(ctx, 8, 2); | |
1838 | xf_emit(ctx, 8, 1); | |
1839 | xf_emit(ctx, 3, 0); | |
1840 | xf_emit(ctx, 1, 1); | |
1841 | xf_emit(ctx, 5, 0); | |
1842 | xf_emit(ctx, 1, 1); | |
1843 | xf_emit(ctx, 0x16, 0); | |
1844 | } else { | |
1845 | if (dev_priv->chipset >= 0xa0) | |
1846 | xf_emit(ctx, 0x1b, 0); | |
1847 | else | |
1848 | xf_emit(ctx, 0x15, 0); | |
1849 | } | |
1850 | xf_emit(ctx, 1, 1); | |
1851 | xf_emit(ctx, 1, 2); | |
1852 | xf_emit(ctx, 2, 1); | |
1853 | xf_emit(ctx, 1, 2); | |
1854 | xf_emit(ctx, 2, 1); | |
1855 | if (dev_priv->chipset >= 0xa0) | |
1856 | xf_emit(ctx, 4, 0); | |
1857 | else | |
1858 | xf_emit(ctx, 3, 0); | |
1859 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
1860 | xf_emit(ctx, 0x10, 1); | |
1861 | xf_emit(ctx, 8, 2); | |
1862 | xf_emit(ctx, 0x10, 1); | |
1863 | xf_emit(ctx, 8, 2); | |
1864 | xf_emit(ctx, 8, 1); | |
1865 | xf_emit(ctx, 3, 0); | |
1866 | } | |
1867 | xf_emit(ctx, 1, 0x11); | |
1868 | xf_emit(ctx, 1, 1); | |
1869 | xf_emit(ctx, 0x5b, 0); | |
1870 | } | |
1871 | ||
1872 | static void | |
1873 | nv50_graph_construct_xfer_tp_x1(struct nouveau_grctx *ctx) | |
1874 | { | |
1875 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1876 | int magic3; | |
1877 | if (dev_priv->chipset == 0x50) | |
1878 | magic3 = 0x1000; | |
1879 | else if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa8) | |
1880 | magic3 = 0x1e00; | |
1881 | else | |
1882 | magic3 = 0; | |
1883 | xf_emit(ctx, 1, 0); | |
1884 | xf_emit(ctx, 1, 4); | |
1885 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1886 | xf_emit(ctx, 0x24, 0); | |
1887 | else if (dev_priv->chipset >= 0xa0) | |
1888 | xf_emit(ctx, 0x14, 0); | |
1889 | else | |
1890 | xf_emit(ctx, 0x15, 0); | |
1891 | xf_emit(ctx, 2, 4); | |
1892 | if (dev_priv->chipset >= 0xa0) | |
1893 | xf_emit(ctx, 1, 0x03020100); | |
1894 | else | |
1895 | xf_emit(ctx, 1, 0x00608080); | |
1896 | xf_emit(ctx, 4, 0); | |
1897 | xf_emit(ctx, 1, 4); | |
1898 | xf_emit(ctx, 2, 0); | |
1899 | xf_emit(ctx, 2, 4); | |
1900 | xf_emit(ctx, 1, 0x80); | |
1901 | if (magic3) | |
1902 | xf_emit(ctx, 1, magic3); | |
1903 | xf_emit(ctx, 1, 4); | |
1904 | xf_emit(ctx, 0x24, 0); | |
1905 | xf_emit(ctx, 1, 4); | |
1906 | xf_emit(ctx, 1, 0x80); | |
1907 | xf_emit(ctx, 1, 4); | |
1908 | xf_emit(ctx, 1, 0x03020100); | |
1909 | xf_emit(ctx, 1, 3); | |
1910 | if (magic3) | |
1911 | xf_emit(ctx, 1, magic3); | |
1912 | xf_emit(ctx, 1, 4); | |
1913 | xf_emit(ctx, 4, 0); | |
1914 | xf_emit(ctx, 1, 4); | |
1915 | xf_emit(ctx, 1, 3); | |
1916 | xf_emit(ctx, 3, 0); | |
1917 | xf_emit(ctx, 1, 4); | |
1918 | if (dev_priv->chipset == 0x94 || dev_priv->chipset == 0x96) | |
1919 | xf_emit(ctx, 0x1024, 0); | |
1920 | else if (dev_priv->chipset < 0xa0) | |
1921 | xf_emit(ctx, 0xa24, 0); | |
1922 | else if (dev_priv->chipset == 0xa0 || dev_priv->chipset >= 0xaa) | |
1923 | xf_emit(ctx, 0x214, 0); | |
1924 | else | |
1925 | xf_emit(ctx, 0x414, 0); | |
1926 | xf_emit(ctx, 1, 4); | |
1927 | xf_emit(ctx, 1, 3); | |
1928 | xf_emit(ctx, 2, 0); | |
1929 | } | |
1930 | ||
1931 | static void | |
1932 | nv50_graph_construct_xfer_tp_x2(struct nouveau_grctx *ctx) | |
1933 | { | |
1934 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
1935 | int magic1, magic2; | |
1936 | if (dev_priv->chipset == 0x50) { | |
1937 | magic1 = 0x3ff; | |
1938 | magic2 = 0x00003e60; | |
1939 | } else if (dev_priv->chipset <= 0xa0 || dev_priv->chipset >= 0xaa) { | |
1940 | magic1 = 0x7ff; | |
1941 | magic2 = 0x001ffe67; | |
1942 | } else { | |
1943 | magic1 = 0x7ff; | |
1944 | magic2 = 0x00087e67; | |
1945 | } | |
1946 | xf_emit(ctx, 3, 0); | |
1947 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1948 | xf_emit(ctx, 1, 1); | |
1949 | xf_emit(ctx, 0xc, 0); | |
1950 | xf_emit(ctx, 1, 0xf); | |
1951 | xf_emit(ctx, 0xb, 0); | |
1952 | xf_emit(ctx, 1, 4); | |
1953 | xf_emit(ctx, 4, 0xffff); | |
1954 | xf_emit(ctx, 8, 0); | |
1955 | xf_emit(ctx, 1, 1); | |
1956 | xf_emit(ctx, 3, 0); | |
1957 | xf_emit(ctx, 1, 1); | |
1958 | xf_emit(ctx, 5, 0); | |
1959 | xf_emit(ctx, 1, 1); | |
1960 | xf_emit(ctx, 2, 0); | |
1961 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
1962 | xf_emit(ctx, 1, 3); | |
1963 | xf_emit(ctx, 1, 0); | |
1964 | } else if (dev_priv->chipset >= 0xa0) | |
1965 | xf_emit(ctx, 1, 1); | |
1966 | xf_emit(ctx, 0xa, 0); | |
1967 | xf_emit(ctx, 2, 1); | |
1968 | xf_emit(ctx, 1, 2); | |
1969 | xf_emit(ctx, 2, 1); | |
1970 | xf_emit(ctx, 1, 2); | |
1971 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
1972 | xf_emit(ctx, 1, 0); | |
1973 | xf_emit(ctx, 0x18, 1); | |
1974 | xf_emit(ctx, 8, 2); | |
1975 | xf_emit(ctx, 8, 1); | |
1976 | xf_emit(ctx, 8, 2); | |
1977 | xf_emit(ctx, 8, 1); | |
1978 | xf_emit(ctx, 1, 0); | |
1979 | } | |
1980 | xf_emit(ctx, 1, 1); | |
1981 | xf_emit(ctx, 1, 0); | |
1982 | xf_emit(ctx, 1, 0x11); | |
1983 | xf_emit(ctx, 7, 0); | |
1984 | xf_emit(ctx, 1, 0x0fac6881); | |
1985 | xf_emit(ctx, 2, 0); | |
1986 | xf_emit(ctx, 1, 4); | |
1987 | xf_emit(ctx, 3, 0); | |
1988 | xf_emit(ctx, 1, 0x11); | |
1989 | xf_emit(ctx, 1, 1); | |
1990 | xf_emit(ctx, 1, 0); | |
1991 | xf_emit(ctx, 3, 0xcf); | |
1992 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
1993 | xf_emit(ctx, 1, 1); | |
1994 | xf_emit(ctx, 0xa, 0); | |
1995 | xf_emit(ctx, 2, 1); | |
1996 | xf_emit(ctx, 1, 2); | |
1997 | xf_emit(ctx, 2, 1); | |
1998 | xf_emit(ctx, 1, 2); | |
1999 | xf_emit(ctx, 1, 1); | |
2000 | xf_emit(ctx, 1, 0); | |
2001 | xf_emit(ctx, 8, 1); | |
2002 | xf_emit(ctx, 1, 0x11); | |
2003 | xf_emit(ctx, 7, 0); | |
2004 | xf_emit(ctx, 1, 0x0fac6881); | |
2005 | xf_emit(ctx, 1, 0xf); | |
2006 | xf_emit(ctx, 7, 0); | |
2007 | xf_emit(ctx, 1, magic2); | |
2008 | xf_emit(ctx, 2, 0); | |
2009 | xf_emit(ctx, 1, 0x11); | |
2010 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2011 | xf_emit(ctx, 2, 1); | |
2012 | else | |
2013 | xf_emit(ctx, 1, 1); | |
2014 | if(dev_priv->chipset == 0x50) | |
2015 | xf_emit(ctx, 1, 0); | |
2016 | else | |
2017 | xf_emit(ctx, 3, 0); | |
2018 | xf_emit(ctx, 1, 4); | |
2019 | xf_emit(ctx, 5, 0); | |
2020 | xf_emit(ctx, 1, 1); | |
2021 | xf_emit(ctx, 4, 0); | |
2022 | xf_emit(ctx, 1, 0x11); | |
2023 | xf_emit(ctx, 7, 0); | |
2024 | xf_emit(ctx, 1, 0x0fac6881); | |
2025 | xf_emit(ctx, 3, 0); | |
2026 | xf_emit(ctx, 1, 0x11); | |
2027 | xf_emit(ctx, 1, 1); | |
2028 | xf_emit(ctx, 1, 0); | |
2029 | xf_emit(ctx, 1, 1); | |
2030 | xf_emit(ctx, 1, 0); | |
2031 | xf_emit(ctx, 1, 1); | |
2032 | xf_emit(ctx, 1, 0); | |
2033 | xf_emit(ctx, 1, magic1); | |
2034 | xf_emit(ctx, 1, 0); | |
2035 | xf_emit(ctx, 1, 1); | |
2036 | xf_emit(ctx, 1, 0); | |
2037 | xf_emit(ctx, 1, 1); | |
2038 | xf_emit(ctx, 2, 0); | |
2039 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2040 | xf_emit(ctx, 1, 1); | |
2041 | xf_emit(ctx, 0x28, 0); | |
2042 | xf_emit(ctx, 8, 8); | |
2043 | xf_emit(ctx, 1, 0x11); | |
2044 | xf_emit(ctx, 7, 0); | |
2045 | xf_emit(ctx, 1, 0x0fac6881); | |
2046 | xf_emit(ctx, 8, 0x400); | |
2047 | xf_emit(ctx, 8, 0x300); | |
2048 | xf_emit(ctx, 1, 1); | |
2049 | xf_emit(ctx, 1, 0xf); | |
2050 | xf_emit(ctx, 7, 0); | |
2051 | xf_emit(ctx, 1, 0x20); | |
2052 | xf_emit(ctx, 1, 0x11); | |
2053 | xf_emit(ctx, 1, 0x100); | |
2054 | xf_emit(ctx, 1, 0); | |
2055 | xf_emit(ctx, 1, 1); | |
2056 | xf_emit(ctx, 2, 0); | |
2057 | xf_emit(ctx, 1, 0x40); | |
2058 | xf_emit(ctx, 1, 0x100); | |
2059 | xf_emit(ctx, 1, 0); | |
2060 | xf_emit(ctx, 1, 3); | |
2061 | xf_emit(ctx, 4, 0); | |
2062 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2063 | xf_emit(ctx, 1, 1); | |
2064 | xf_emit(ctx, 1, magic2); | |
2065 | xf_emit(ctx, 3, 0); | |
2066 | xf_emit(ctx, 1, 2); | |
2067 | xf_emit(ctx, 1, 0x0fac6881); | |
2068 | xf_emit(ctx, 9, 0); | |
2069 | xf_emit(ctx, 1, 1); | |
2070 | xf_emit(ctx, 4, 0); | |
2071 | xf_emit(ctx, 1, 4); | |
2072 | xf_emit(ctx, 1, 0); | |
2073 | xf_emit(ctx, 1, 1); | |
2074 | xf_emit(ctx, 1, 0x400); | |
2075 | xf_emit(ctx, 1, 0x300); | |
2076 | xf_emit(ctx, 1, 0x1001); | |
2077 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2078 | xf_emit(ctx, 4, 0); | |
2079 | else | |
2080 | xf_emit(ctx, 3, 0); | |
2081 | xf_emit(ctx, 1, 0x11); | |
2082 | xf_emit(ctx, 7, 0); | |
2083 | xf_emit(ctx, 1, 0x0fac6881); | |
2084 | xf_emit(ctx, 1, 0xf); | |
2085 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
2086 | xf_emit(ctx, 0x15, 0); | |
2087 | xf_emit(ctx, 1, 1); | |
2088 | xf_emit(ctx, 3, 0); | |
2089 | } else | |
2090 | xf_emit(ctx, 0x17, 0); | |
2091 | if (dev_priv->chipset >= 0xa0) | |
2092 | xf_emit(ctx, 1, 0x0fac6881); | |
2093 | xf_emit(ctx, 1, magic2); | |
2094 | xf_emit(ctx, 3, 0); | |
2095 | xf_emit(ctx, 1, 0x11); | |
2096 | xf_emit(ctx, 2, 0); | |
2097 | xf_emit(ctx, 1, 4); | |
2098 | xf_emit(ctx, 1, 0); | |
2099 | xf_emit(ctx, 2, 1); | |
2100 | xf_emit(ctx, 3, 0); | |
2101 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2102 | xf_emit(ctx, 2, 1); | |
2103 | else | |
2104 | xf_emit(ctx, 1, 1); | |
2105 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2106 | xf_emit(ctx, 2, 0); | |
2107 | else if (dev_priv->chipset != 0x50) | |
2108 | xf_emit(ctx, 1, 0); | |
2109 | } | |
2110 | ||
2111 | static void | |
2112 | nv50_graph_construct_xfer_tp_x3(struct nouveau_grctx *ctx) | |
2113 | { | |
2114 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
2115 | xf_emit(ctx, 3, 0); | |
2116 | xf_emit(ctx, 1, 1); | |
2117 | xf_emit(ctx, 1, 0); | |
2118 | xf_emit(ctx, 1, 1); | |
2119 | if (dev_priv->chipset == 0x50) | |
2120 | xf_emit(ctx, 2, 0); | |
2121 | else | |
2122 | xf_emit(ctx, 3, 0); | |
2123 | xf_emit(ctx, 1, 0x2a712488); | |
2124 | xf_emit(ctx, 1, 0); | |
2125 | xf_emit(ctx, 1, 0x4085c000); | |
2126 | xf_emit(ctx, 1, 0x40); | |
2127 | xf_emit(ctx, 1, 0x100); | |
2128 | xf_emit(ctx, 1, 0x10100); | |
2129 | xf_emit(ctx, 1, 0x02800000); | |
2130 | } | |
2131 | ||
2132 | static void | |
2133 | nv50_graph_construct_xfer_tp_x4(struct nouveau_grctx *ctx) | |
2134 | { | |
2135 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
2136 | xf_emit(ctx, 2, 0x04e3bfdf); | |
2137 | xf_emit(ctx, 1, 1); | |
2138 | xf_emit(ctx, 1, 0); | |
2139 | xf_emit(ctx, 1, 0x00ffff00); | |
2140 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2141 | xf_emit(ctx, 2, 1); | |
2142 | else | |
2143 | xf_emit(ctx, 1, 1); | |
2144 | xf_emit(ctx, 2, 0); | |
2145 | xf_emit(ctx, 1, 0x00ffff00); | |
2146 | xf_emit(ctx, 8, 0); | |
2147 | xf_emit(ctx, 1, 1); | |
2148 | xf_emit(ctx, 1, 0); | |
2149 | xf_emit(ctx, 1, 1); | |
2150 | xf_emit(ctx, 1, 0x30201000); | |
2151 | xf_emit(ctx, 1, 0x70605040); | |
2152 | xf_emit(ctx, 1, 0xb8a89888); | |
2153 | xf_emit(ctx, 1, 0xf8e8d8c8); | |
2154 | xf_emit(ctx, 1, 0); | |
2155 | xf_emit(ctx, 1, 0x1a); | |
2156 | } | |
2157 | ||
2158 | static void | |
2159 | nv50_graph_construct_xfer_tp_x5(struct nouveau_grctx *ctx) | |
2160 | { | |
2161 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
2162 | xf_emit(ctx, 3, 0); | |
2163 | xf_emit(ctx, 1, 0xfac6881); | |
2164 | xf_emit(ctx, 4, 0); | |
2165 | xf_emit(ctx, 1, 4); | |
2166 | xf_emit(ctx, 1, 0); | |
2167 | xf_emit(ctx, 2, 1); | |
2168 | xf_emit(ctx, 2, 0); | |
2169 | xf_emit(ctx, 1, 1); | |
2170 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2171 | xf_emit(ctx, 0xb, 0); | |
2172 | else | |
2173 | xf_emit(ctx, 0xa, 0); | |
2174 | xf_emit(ctx, 8, 1); | |
2175 | xf_emit(ctx, 1, 0x11); | |
2176 | xf_emit(ctx, 7, 0); | |
2177 | xf_emit(ctx, 1, 0xfac6881); | |
2178 | xf_emit(ctx, 1, 0xf); | |
2179 | xf_emit(ctx, 7, 0); | |
2180 | xf_emit(ctx, 1, 0x11); | |
2181 | xf_emit(ctx, 1, 1); | |
2182 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
2183 | xf_emit(ctx, 6, 0); | |
2184 | xf_emit(ctx, 1, 1); | |
2185 | xf_emit(ctx, 6, 0); | |
2186 | } else { | |
2187 | xf_emit(ctx, 0xb, 0); | |
2188 | } | |
2189 | } | |
2190 | ||
2191 | static void | |
2192 | nv50_graph_construct_xfer_tp(struct nouveau_grctx *ctx) | |
2193 | { | |
2194 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
2195 | if (dev_priv->chipset < 0xa0) { | |
2196 | nv50_graph_construct_xfer_tp_x1(ctx); | |
2197 | nv50_graph_construct_xfer_tp_x2(ctx); | |
2198 | nv50_graph_construct_xfer_tp_x3(ctx); | |
2199 | if (dev_priv->chipset == 0x50) | |
2200 | xf_emit(ctx, 0xf, 0); | |
2201 | else | |
2202 | xf_emit(ctx, 0x12, 0); | |
2203 | nv50_graph_construct_xfer_tp_x4(ctx); | |
2204 | } else { | |
2205 | nv50_graph_construct_xfer_tp_x3(ctx); | |
2206 | if (dev_priv->chipset < 0xaa) | |
2207 | xf_emit(ctx, 0xc, 0); | |
2208 | else | |
2209 | xf_emit(ctx, 0xa, 0); | |
2210 | nv50_graph_construct_xfer_tp_x2(ctx); | |
2211 | nv50_graph_construct_xfer_tp_x5(ctx); | |
2212 | nv50_graph_construct_xfer_tp_x4(ctx); | |
2213 | nv50_graph_construct_xfer_tp_x1(ctx); | |
2214 | } | |
2215 | } | |
2216 | ||
2217 | static void | |
2218 | nv50_graph_construct_xfer_tp2(struct nouveau_grctx *ctx) | |
2219 | { | |
2220 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
2221 | int i, mpcnt; | |
2222 | if (dev_priv->chipset == 0x98 || dev_priv->chipset == 0xaa) | |
2223 | mpcnt = 1; | |
2224 | else if (dev_priv->chipset < 0xa0 || dev_priv->chipset >= 0xa8) | |
2225 | mpcnt = 2; | |
2226 | else | |
2227 | mpcnt = 3; | |
2228 | for (i = 0; i < mpcnt; i++) { | |
2229 | xf_emit(ctx, 1, 0); | |
2230 | xf_emit(ctx, 1, 0x80); | |
2231 | xf_emit(ctx, 1, 0x80007004); | |
2232 | xf_emit(ctx, 1, 0x04000400); | |
2233 | if (dev_priv->chipset >= 0xa0) | |
2234 | xf_emit(ctx, 1, 0xc0); | |
2235 | xf_emit(ctx, 1, 0x1000); | |
2236 | xf_emit(ctx, 2, 0); | |
2237 | if (dev_priv->chipset == 0x86 || dev_priv->chipset == 0x98 || dev_priv->chipset >= 0xa8) { | |
2238 | xf_emit(ctx, 1, 0xe00); | |
2239 | xf_emit(ctx, 1, 0x1e00); | |
2240 | } | |
2241 | xf_emit(ctx, 1, 1); | |
2242 | xf_emit(ctx, 2, 0); | |
2243 | if (dev_priv->chipset == 0x50) | |
2244 | xf_emit(ctx, 2, 0x1000); | |
2245 | xf_emit(ctx, 1, 1); | |
2246 | xf_emit(ctx, 1, 0); | |
2247 | xf_emit(ctx, 1, 4); | |
2248 | xf_emit(ctx, 1, 2); | |
2249 | if (dev_priv->chipset >= 0xaa) | |
2250 | xf_emit(ctx, 0xb, 0); | |
2251 | else if (dev_priv->chipset >= 0xa0) | |
2252 | xf_emit(ctx, 0xc, 0); | |
2253 | else | |
2254 | xf_emit(ctx, 0xa, 0); | |
2255 | } | |
2256 | xf_emit(ctx, 1, 0x08100c12); | |
2257 | xf_emit(ctx, 1, 0); | |
2258 | if (dev_priv->chipset >= 0xa0) { | |
2259 | xf_emit(ctx, 1, 0x1fe21); | |
2260 | } | |
2261 | xf_emit(ctx, 5, 0); | |
2262 | xf_emit(ctx, 4, 0xffff); | |
2263 | xf_emit(ctx, 1, 1); | |
2264 | xf_emit(ctx, 2, 0x10001); | |
2265 | xf_emit(ctx, 1, 1); | |
2266 | xf_emit(ctx, 1, 0); | |
2267 | xf_emit(ctx, 1, 0x1fe21); | |
2268 | xf_emit(ctx, 1, 0); | |
2269 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2270 | xf_emit(ctx, 1, 1); | |
2271 | xf_emit(ctx, 4, 0); | |
2272 | xf_emit(ctx, 1, 0x08100c12); | |
2273 | xf_emit(ctx, 1, 4); | |
2274 | xf_emit(ctx, 1, 0); | |
2275 | xf_emit(ctx, 1, 2); | |
2276 | xf_emit(ctx, 1, 0x11); | |
2277 | xf_emit(ctx, 8, 0); | |
2278 | xf_emit(ctx, 1, 0xfac6881); | |
2279 | xf_emit(ctx, 1, 0); | |
2280 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) | |
2281 | xf_emit(ctx, 1, 3); | |
2282 | xf_emit(ctx, 3, 0); | |
2283 | xf_emit(ctx, 1, 4); | |
2284 | xf_emit(ctx, 9, 0); | |
2285 | xf_emit(ctx, 1, 2); | |
2286 | xf_emit(ctx, 2, 1); | |
2287 | xf_emit(ctx, 1, 2); | |
2288 | xf_emit(ctx, 3, 1); | |
2289 | xf_emit(ctx, 1, 0); | |
2290 | if (dev_priv->chipset > 0xa0 && dev_priv->chipset < 0xaa) { | |
2291 | xf_emit(ctx, 8, 2); | |
2292 | xf_emit(ctx, 0x10, 1); | |
2293 | xf_emit(ctx, 8, 2); | |
2294 | xf_emit(ctx, 0x18, 1); | |
2295 | xf_emit(ctx, 3, 0); | |
2296 | } | |
2297 | xf_emit(ctx, 1, 4); | |
2298 | if (dev_priv->chipset == 0x50) | |
2299 | xf_emit(ctx, 0x3a0, 0); | |
2300 | else if (dev_priv->chipset < 0x94) | |
2301 | xf_emit(ctx, 0x3a2, 0); | |
2302 | else if (dev_priv->chipset == 0x98 || dev_priv->chipset == 0xaa) | |
2303 | xf_emit(ctx, 0x39f, 0); | |
2304 | else | |
2305 | xf_emit(ctx, 0x3a3, 0); | |
2306 | xf_emit(ctx, 1, 0x11); | |
2307 | xf_emit(ctx, 1, 0); | |
2308 | xf_emit(ctx, 1, 1); | |
2309 | xf_emit(ctx, 0x2d, 0); | |
2310 | } | |
2311 | ||
2312 | static void | |
2313 | nv50_graph_construct_xfer2(struct nouveau_grctx *ctx) | |
2314 | { | |
2315 | struct drm_nouveau_private *dev_priv = ctx->dev->dev_private; | |
2316 | int i; | |
2317 | uint32_t offset; | |
2318 | uint32_t units = nv_rd32 (ctx->dev, 0x1540); | |
2319 | int size = 0; | |
2320 | ||
2321 | offset = (ctx->ctxvals_pos+0x3f)&~0x3f; | |
2322 | ||
2323 | if (dev_priv->chipset < 0xa0) { | |
2324 | for (i = 0; i < 8; i++) { | |
2325 | ctx->ctxvals_pos = offset + i; | |
2326 | if (i == 0) | |
2327 | xf_emit(ctx, 1, 0x08100c12); | |
2328 | if (units & (1 << i)) | |
2329 | nv50_graph_construct_xfer_tp2(ctx); | |
2330 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
2331 | size = (ctx->ctxvals_pos-offset)/8; | |
2332 | } | |
2333 | } else { | |
2334 | /* Strand 0: TPs 0, 1 */ | |
2335 | ctx->ctxvals_pos = offset; | |
2336 | xf_emit(ctx, 1, 0x08100c12); | |
2337 | if (units & (1 << 0)) | |
2338 | nv50_graph_construct_xfer_tp2(ctx); | |
2339 | if (units & (1 << 1)) | |
2340 | nv50_graph_construct_xfer_tp2(ctx); | |
2341 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
2342 | size = (ctx->ctxvals_pos-offset)/8; | |
2343 | ||
2344 | /* Strand 0: TPs 2, 3 */ | |
2345 | ctx->ctxvals_pos = offset + 1; | |
2346 | if (units & (1 << 2)) | |
2347 | nv50_graph_construct_xfer_tp2(ctx); | |
2348 | if (units & (1 << 3)) | |
2349 | nv50_graph_construct_xfer_tp2(ctx); | |
2350 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
2351 | size = (ctx->ctxvals_pos-offset)/8; | |
2352 | ||
2353 | /* Strand 0: TPs 4, 5, 6 */ | |
2354 | ctx->ctxvals_pos = offset + 2; | |
2355 | if (units & (1 << 4)) | |
2356 | nv50_graph_construct_xfer_tp2(ctx); | |
2357 | if (units & (1 << 5)) | |
2358 | nv50_graph_construct_xfer_tp2(ctx); | |
2359 | if (units & (1 << 6)) | |
2360 | nv50_graph_construct_xfer_tp2(ctx); | |
2361 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
2362 | size = (ctx->ctxvals_pos-offset)/8; | |
2363 | ||
2364 | /* Strand 0: TPs 7, 8, 9 */ | |
2365 | ctx->ctxvals_pos = offset + 3; | |
2366 | if (units & (1 << 7)) | |
2367 | nv50_graph_construct_xfer_tp2(ctx); | |
2368 | if (units & (1 << 8)) | |
2369 | nv50_graph_construct_xfer_tp2(ctx); | |
2370 | if (units & (1 << 9)) | |
2371 | nv50_graph_construct_xfer_tp2(ctx); | |
2372 | if ((ctx->ctxvals_pos-offset)/8 > size) | |
2373 | size = (ctx->ctxvals_pos-offset)/8; | |
2374 | } | |
2375 | ctx->ctxvals_pos = offset + size * 8; | |
2376 | ctx->ctxvals_pos = (ctx->ctxvals_pos+0x3f)&~0x3f; | |
2377 | cp_lsr (ctx, offset); | |
2378 | cp_out (ctx, CP_SET_XFER_POINTER); | |
2379 | cp_lsr (ctx, size); | |
2380 | cp_out (ctx, CP_SEEK_2); | |
2381 | cp_out (ctx, CP_XFER_2); | |
2382 | cp_wait(ctx, XFER, BUSY); | |
2383 | } |