Commit | Line | Data |
---|---|---|
20abd163 BS |
1 | /* |
2 | * Copyright 2012 Red Hat Inc. | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice shall be included in | |
12 | * all copies or substantial portions of the Software. | |
13 | * | |
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
20 | * OTHER DEALINGS IN THE SOFTWARE. | |
21 | * | |
22 | * Authors: Ben Skeggs | |
23 | */ | |
24 | ||
25 | #include "drmP.h" | |
35bcf5d5 | 26 | |
20abd163 | 27 | #include "nouveau_drv.h" |
02a841d4 | 28 | #include <core/ramht.h> |
20abd163 BS |
29 | #include "nouveau_software.h" |
30 | ||
35bcf5d5 BS |
31 | #include "nv50_display.h" |
32 | ||
20abd163 BS |
33 | struct nv50_software_priv { |
34 | struct nouveau_software_priv base; | |
35 | }; | |
36 | ||
37 | struct nv50_software_chan { | |
38 | struct nouveau_software_chan base; | |
20abd163 BS |
39 | }; |
40 | ||
41 | static int | |
42 | mthd_dma_vblsem(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data) | |
43 | { | |
44 | struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW]; | |
45 | struct nouveau_gpuobj *gpuobj; | |
46 | ||
47 | gpuobj = nouveau_ramht_find(chan, data); | |
48 | if (!gpuobj) | |
49 | return -ENOENT; | |
50 | ||
3863c9bc | 51 | pch->base.vblank.ctxdma = gpuobj->node->offset >> 4; |
20abd163 BS |
52 | return 0; |
53 | } | |
54 | ||
55 | static int | |
56 | mthd_vblsem_offset(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data) | |
57 | { | |
58 | struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW]; | |
0ade74b6 | 59 | pch->base.vblank.offset = data; |
20abd163 BS |
60 | return 0; |
61 | } | |
62 | ||
63 | static int | |
64 | mthd_vblsem_value(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data) | |
65 | { | |
66 | struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW]; | |
67 | pch->base.vblank.value = data; | |
68 | return 0; | |
69 | } | |
70 | ||
71 | static int | |
72 | mthd_vblsem_release(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data) | |
73 | { | |
74 | struct nv50_software_priv *psw = nv_engine(chan->dev, NVOBJ_ENGINE_SW); | |
75 | struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW]; | |
76 | struct drm_device *dev = chan->dev; | |
77 | ||
0ade74b6 | 78 | if (data > 1) |
20abd163 BS |
79 | return -EINVAL; |
80 | ||
81 | drm_vblank_get(dev, data); | |
82 | ||
83 | pch->base.vblank.head = data; | |
84 | list_add(&pch->base.vblank.list, &psw->base.vblank); | |
85 | return 0; | |
86 | } | |
87 | ||
88 | static int | |
89 | mthd_flip(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data) | |
90 | { | |
f589be88 BS |
91 | struct nv50_software_chan *pch = chan->engctx[NVOBJ_ENGINE_SW]; |
92 | return pch->base.flip(pch->base.flip_data); | |
20abd163 BS |
93 | } |
94 | ||
95 | static int | |
96 | nv50_software_context_new(struct nouveau_channel *chan, int engine) | |
97 | { | |
98 | struct nv50_software_chan *pch; | |
99 | ||
100 | pch = kzalloc(sizeof(*pch), GFP_KERNEL); | |
101 | if (!pch) | |
102 | return -ENOMEM; | |
103 | ||
f589be88 | 104 | nouveau_software_context_new(chan, &pch->base); |
3863c9bc | 105 | pch->base.vblank.channel = chan->ramin->addr >> 12; |
20abd163 | 106 | chan->engctx[engine] = pch; |
f589be88 | 107 | return 0; |
20abd163 BS |
108 | } |
109 | ||
110 | static void | |
111 | nv50_software_context_del(struct nouveau_channel *chan, int engine) | |
112 | { | |
113 | struct nv50_software_chan *pch = chan->engctx[engine]; | |
114 | chan->engctx[engine] = NULL; | |
115 | kfree(pch); | |
116 | } | |
117 | ||
118 | static int | |
119 | nv50_software_object_new(struct nouveau_channel *chan, int engine, | |
120 | u32 handle, u16 class) | |
121 | { | |
122 | struct drm_device *dev = chan->dev; | |
123 | struct nouveau_gpuobj *obj = NULL; | |
124 | int ret; | |
125 | ||
126 | ret = nouveau_gpuobj_new(dev, chan, 16, 16, 0, &obj); | |
127 | if (ret) | |
128 | return ret; | |
129 | obj->engine = 0; | |
130 | obj->class = class; | |
131 | ||
132 | ret = nouveau_ramht_insert(chan, handle, obj); | |
133 | nouveau_gpuobj_ref(NULL, &obj); | |
134 | return ret; | |
135 | } | |
136 | ||
137 | static int | |
138 | nv50_software_init(struct drm_device *dev, int engine) | |
139 | { | |
140 | return 0; | |
141 | } | |
142 | ||
143 | static int | |
144 | nv50_software_fini(struct drm_device *dev, int engine, bool suspend) | |
145 | { | |
146 | return 0; | |
147 | } | |
148 | ||
149 | static void | |
150 | nv50_software_destroy(struct drm_device *dev, int engine) | |
151 | { | |
152 | struct nv50_software_priv *psw = nv_engine(dev, engine); | |
153 | ||
154 | NVOBJ_ENGINE_DEL(dev, SW); | |
155 | kfree(psw); | |
156 | } | |
157 | ||
158 | int | |
159 | nv50_software_create(struct drm_device *dev) | |
160 | { | |
161 | struct nv50_software_priv *psw = kzalloc(sizeof(*psw), GFP_KERNEL); | |
162 | if (!psw) | |
163 | return -ENOMEM; | |
164 | ||
165 | psw->base.base.destroy = nv50_software_destroy; | |
166 | psw->base.base.init = nv50_software_init; | |
167 | psw->base.base.fini = nv50_software_fini; | |
168 | psw->base.base.context_new = nv50_software_context_new; | |
169 | psw->base.base.context_del = nv50_software_context_del; | |
170 | psw->base.base.object_new = nv50_software_object_new; | |
171 | nouveau_software_create(&psw->base); | |
172 | ||
173 | NVOBJ_ENGINE_ADD(dev, SW, &psw->base.base); | |
174 | NVOBJ_CLASS(dev, 0x506e, SW); | |
175 | NVOBJ_MTHD (dev, 0x506e, 0x018c, mthd_dma_vblsem); | |
176 | NVOBJ_MTHD (dev, 0x506e, 0x0400, mthd_vblsem_offset); | |
177 | NVOBJ_MTHD (dev, 0x506e, 0x0404, mthd_vblsem_value); | |
178 | NVOBJ_MTHD (dev, 0x506e, 0x0408, mthd_vblsem_release); | |
179 | NVOBJ_MTHD (dev, 0x506e, 0x0500, mthd_flip); | |
180 | return 0; | |
181 | } |