[deliverable/linux.git] / drivers / gpu / drm / nouveau / nv50_vm.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include "drmP.h"

#include "nouveau_drv.h"
#include "nouveau_vm.h"

void
nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
		struct nouveau_gpuobj *pgt[2])
{
	struct drm_nouveau_private *dev_priv = pgd->dev->dev_private;
	u64 phys = 0xdeadcafe00000000ULL;
	u32 coverage = 0;

	if (pgt[0]) {
		phys = 0x00000003 | pgt[0]->vinst; /* present, 4KiB pages */
		coverage = (pgt[0]->size >> 3) << 12;
	} else
	if (pgt[1]) {
		phys = 0x00000001 | pgt[1]->vinst; /* present */
		coverage = (pgt[1]->size >> 3) << 16;
	}

	if (phys & 1) {
		if (coverage <= 32 * 1024 * 1024)
			phys |= 0x60;
		else if (coverage <= 64 * 1024 * 1024)
			phys |= 0x40;
		else if (coverage < 128 * 1024 * 1024)
			phys |= 0x20;
	}

	nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
	nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
}

static inline u64
nv50_vm_addr(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
	     u64 phys, u32 memtype, u32 target)
{
	struct drm_nouveau_private *dev_priv = pgt->dev->dev_private;

	phys |= 1; /* present */
	phys |= (u64)memtype << 40;

	/* IGPs don't have real VRAM, re-target to stolen system memory */
	if (target == 0 && dev_priv->vram_sys_base) {
		phys  += dev_priv->vram_sys_base;
		target = 3;
	}

	phys |= target << 4;

	if (vma->access & NV_MEM_ACCESS_SYS)
		phys |= (1 << 6);

	if (!(vma->access & NV_MEM_ACCESS_WO))
		phys |= (1 << 3);

	return phys;
}

void
nv50_vm_map(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
	    struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys)
{
	u32 block;
	int i;

	phys  = nv50_vm_addr(vma, pgt, phys, mem->memtype, 0);
	pte <<= 3;
	cnt <<= 3;

	while (cnt) {
		u32 offset_h = upper_32_bits(phys);
		u32 offset_l = lower_32_bits(phys);

		for (i = 7; i >= 0; i--) {
			block = 1 << (i + 3);
			if (cnt >= block && !(pte & (block - 1)))
				break;
		}
		offset_l |= (i << 7);

		phys += block << (vma->node->type - 3);
		cnt  -= block;

		while (block) {
			nv_wo32(pgt, pte + 0, offset_l);
			nv_wo32(pgt, pte + 4, offset_h);
			pte += 8;
			block -= 8;
		}
	}
}

void
nv50_vm_map_sg(struct nouveau_vma *vma, struct nouveau_gpuobj *pgt,
	       u32 pte, dma_addr_t *list, u32 cnt)
{
	pte <<= 3;
	while (cnt--) {
		u64 phys = nv50_vm_addr(vma, pgt, (u64)*list++, 0, 2);
		nv_wo32(pgt, pte + 0, lower_32_bits(phys));
		nv_wo32(pgt, pte + 4, upper_32_bits(phys));
		pte += 8;
	}
}

void
nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
{
	pte <<= 3;
	while (cnt--) {
		nv_wo32(pgt, pte + 0, 0x00000000);
		nv_wo32(pgt, pte + 4, 0x00000000);
		pte += 8;
	}
}

void
nv50_vm_flush(struct nouveau_vm *vm)
{
	struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;

	pinstmem->flush(vm->dev);

	/* BAR */
	if (vm != dev_priv->chan_vm) {
		nv50_vm_flush_engine(vm->dev, 6);
		return;
	}

	pfifo->tlb_flush(vm->dev);

	if (atomic_read(&vm->pgraph_refs))
		pgraph->tlb_flush(vm->dev);
	if (atomic_read(&vm->pcrypt_refs))
		pcrypt->tlb_flush(vm->dev);
}

void
nv50_vm_flush_engine(struct drm_device *dev, int engine)
{
	struct drm_nouveau_private *dev_priv = dev->dev_private;

	spin_lock(&dev_priv->ramin_lock);
	nv_wr32(dev, 0x100c80, (engine << 16) | 1);
	if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000))
		NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
	spin_unlock(&dev_priv->ramin_lock);
}
Commit	Line	Data
a11c3198 BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
	25	#include "drmP.h"
	26
	27	#include "nouveau_drv.h"
	28	#include "nouveau_vm.h"
	29
	30	void
3ee01281 BS	31	nv50_vm_map_pgt(struct nouveau_gpuobj *pgd, u32 pde,
3ee01281 BS	32	struct nouveau_gpuobj *pgt[2])
a11c3198 BS	33	{
a11c3198 BS	34	struct drm_nouveau_private *dev_priv = pgd->dev->dev_private;
3ee01281 BS	35	u64 phys = 0xdeadcafe00000000ULL;
3ee01281 BS	36	u32 coverage = 0;
a11c3198	37
3ee01281 BS	38	if (pgt[0]) {
	39	phys = 0x00000003 \| pgt[0]->vinst; /* present, 4KiB pages */
	40	coverage = (pgt[0]->size >> 3) << 12;
	41	} else
	42	if (pgt[1]) {
	43	phys = 0x00000001 \| pgt[1]->vinst; /* present */
	44	coverage = (pgt[1]->size >> 3) << 16;
a11c3198 BS	45	}
a11c3198 BS	46
3ee01281	47	if (phys & 1) {
3ee01281 BS	48	if (coverage <= 32 * 1024 * 1024)
	49	phys \|= 0x60;
	50	else if (coverage <= 64 * 1024 * 1024)
	51	phys \|= 0x40;
	52	else if (coverage < 128 * 1024 * 1024)
	53	phys \|= 0x20;
	54	}
a11c3198 BS	55
	56	nv_wo32(pgd, (pde * 8) + 0, lower_32_bits(phys));
	57	nv_wo32(pgd, (pde * 8) + 4, upper_32_bits(phys));
	58	}
	59
a11c3198 BS	60	static inline u64
	61	nv50_vm_addr(struct nouveau_vma vma, struct nouveau_gpuobj pgt,
	62	u64 phys, u32 memtype, u32 target)
	63	{
	64	struct drm_nouveau_private *dev_priv = pgt->dev->dev_private;
	65
	66	phys \|= 1; /* present */
	67	phys \|= (u64)memtype << 40;
	68
	69	/* IGPs don't have real VRAM, re-target to stolen system memory */
	70	if (target == 0 && dev_priv->vram_sys_base) {
	71	phys += dev_priv->vram_sys_base;
	72	target = 3;
	73	}
	74
	75	phys \|= target << 4;
	76
	77	if (vma->access & NV_MEM_ACCESS_SYS)
	78	phys \|= (1 << 6);
	79
	80	if (!(vma->access & NV_MEM_ACCESS_WO))
	81	phys \|= (1 << 3);
	82
	83	return phys;
	84	}
	85
	86	void
	87	nv50_vm_map(struct nouveau_vma vma, struct nouveau_gpuobj pgt,
	88	struct nouveau_vram *mem, u32 pte, u32 cnt, u64 phys)
	89	{
910d1b3a BS	90	u32 block;
910d1b3a BS	91	int i;
a11c3198 BS	92
	93	phys = nv50_vm_addr(vma, pgt, phys, mem->memtype, 0);
	94	pte <<= 3;
	95	cnt <<= 3;
	96
	97	while (cnt) {
	98	u32 offset_h = upper_32_bits(phys);
	99	u32 offset_l = lower_32_bits(phys);
	100
	101	for (i = 7; i >= 0; i--) {
	102	block = 1 << (i + 3);
	103	if (cnt >= block && !(pte & (block - 1)))
	104	break;
	105	}
	106	offset_l \|= (i << 7);
	107
	108	phys += block << (vma->node->type - 3);
	109	cnt -= block;
	110
	111	while (block) {
	112	nv_wo32(pgt, pte + 0, offset_l);
	113	nv_wo32(pgt, pte + 4, offset_h);
	114	pte += 8;
	115	block -= 8;
	116	}
	117	}
	118	}
	119
	120	void
	121	nv50_vm_map_sg(struct nouveau_vma vma, struct nouveau_gpuobj pgt,
	122	u32 pte, dma_addr_t *list, u32 cnt)
	123	{
	124	pte <<= 3;
	125	while (cnt--) {
	126	u64 phys = nv50_vm_addr(vma, pgt, (u64)*list++, 0, 2);
	127	nv_wo32(pgt, pte + 0, lower_32_bits(phys));
	128	nv_wo32(pgt, pte + 4, upper_32_bits(phys));
	129	pte += 8;
	130	}
	131	}
	132
	133	void
	134	nv50_vm_unmap(struct nouveau_gpuobj *pgt, u32 pte, u32 cnt)
	135	{
	136	pte <<= 3;
	137	while (cnt--) {
	138	nv_wo32(pgt, pte + 0, 0x00000000);
	139	nv_wo32(pgt, pte + 4, 0x00000000);
	140	pte += 8;
	141	}
	142	}
	143
	144	void
	145	nv50_vm_flush(struct nouveau_vm *vm)
	146	{
	147	struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
	148	struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
4c136142 BS	149	struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
	150	struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
	151	struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
a11c3198 BS	152
a11c3198 BS	153	pinstmem->flush(vm->dev);
4c136142 BS	154
	155	/* BAR */
	156	if (vm != dev_priv->chan_vm) {
	157	nv50_vm_flush_engine(vm->dev, 6);
	158	return;
	159	}
	160
	161	pfifo->tlb_flush(vm->dev);
	162
	163	if (atomic_read(&vm->pgraph_refs))
	164	pgraph->tlb_flush(vm->dev);
	165	if (atomic_read(&vm->pcrypt_refs))
	166	pcrypt->tlb_flush(vm->dev);
a11c3198 BS	167	}
	168
	169	void
	170	nv50_vm_flush_engine(struct drm_device *dev, int engine)
	171	{
6f70a4c3 BS	172	struct drm_nouveau_private *dev_priv = dev->dev_private;
	173
	174	spin_lock(&dev_priv->ramin_lock);
a11c3198 BS	175	nv_wr32(dev, 0x100c80, (engine << 16) \| 1);
	176	if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000))
	177	NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
6f70a4c3	178	spin_unlock(&dev_priv->ramin_lock);
a11c3198	179	}